From 90a477ce32b6e77959898610a16155adaaef44ad Mon Sep 17 00:00:00 2001
From: Antoni Zwolski <antoni.zwolski@intel.com>
Date: Fri, 19 Sep 2025 16:18:47 +0200
Subject: [PATCH 1/4] Add pr159723.ll test with invalid comparison

---
 llvm/test/CodeGen/X86/pr159723.ll | 131 ++++++++++++++++++++++++++++++
 1 file changed, 131 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/pr159723.ll

diff --git a/llvm/test/CodeGen/X86/pr159723.ll b/llvm/test/CodeGen/X86/pr159723.ll
new file mode 100644
index 0000000000000..f11a058d97c63
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr159723.ll
@@ -0,0 +1,131 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16 -mattr=+avx512vl -O2| FileCheck %s
+
+declare <8 x half> @test_call_8()
+
+declare <16 x half> @test_call_16()
+
+declare <32 x half> @test_call_32()
+
+define <8 x i1> @test_cmp_v8half_ogt(<8 x half> %rhs, <8 x i1> %mask) nounwind {
+; CHECK-LABEL: test_cmp_v8half_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    subq $40, %rsp
+; CHECK-NEXT:    vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT:    vpsllw $15, %xmm1, %xmm0
+; CHECK-NEXT:    vpmovw2m %xmm0, %k1
+; CHECK-NEXT:    kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
+; CHECK-NEXT:    callq test_call_8@PLT
+; CHECK-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
+; CHECK-NEXT:    vcmpltph {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %k0 {%k1} # 16-byte Folded Reload
+; CHECK-NEXT:    vpmovm2w %k0, %xmm0
+; CHECK-NEXT:    addq $40, %rsp
+; CHECK-NEXT:    retq
+    %lhs = call <8 x half> @test_call_8()
+    %comp = fcmp ogt <8 x half> %lhs, %rhs
+    %res = and <8 x i1> %comp, %mask
+    ret <8 x i1> %res
+}
+
+define <8 x i1> @test_cmp_v8half_ogt_rev(<8 x half> %rhs, <8 x i1> %mask) nounwind {
+; CHECK-LABEL: test_cmp_v8half_ogt_rev:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    subq $40, %rsp
+; CHECK-NEXT:    vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT:    vpsllw $15, %xmm1, %xmm0
+; CHECK-NEXT:    vpmovw2m %xmm0, %k1
+; CHECK-NEXT:    kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
+; CHECK-NEXT:    callq test_call_8@PLT
+; CHECK-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
+; CHECK-NEXT:    vcmpltph {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %k0 {%k1} # 16-byte Folded Reload
+; CHECK-NEXT:    vpmovm2w %k0, %xmm0
+; CHECK-NEXT:    addq $40, %rsp
+; CHECK-NEXT:    retq
+    %lhs = call <8 x half> @test_call_8()
+    %comp = fcmp ogt <8 x half> %rhs, %lhs
+    %res = and <8 x i1> %comp, %mask
+    ret <8 x i1> %res
+}
+
+
+define <16 x i1> @test_cmp_v16half_olt(<16 x half> %rhs, <16 x i1> %mask) nounwind {
+; CHECK-LABEL: test_cmp_v16half_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    subq $56, %rsp
+; CHECK-NEXT:    vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT:    vpsllw $7, %xmm1, %xmm0
+; CHECK-NEXT:    vpmovb2m %xmm0, %k1
+; CHECK-NEXT:    kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
+; CHECK-NEXT:    callq test_call_16@PLT
+; CHECK-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
+; CHECK-NEXT:    vcmpltph {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %k0 {%k1} # 32-byte Folded Reload
+; CHECK-NEXT:    vpmovm2b %k0, %xmm0
+; CHECK-NEXT:    addq $56, %rsp
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+    %lhs = call <16 x half> @test_call_16()
+    %comp = fcmp olt <16 x half> %lhs, %rhs
+    %res = and <16 x i1> %comp, %mask
+    ret <16 x i1> %res
+}
+
+define <16 x i1> @test_cmp_v16half_olt_rev(<16 x half> %rhs, <16 x i1> %mask) nounwind {
+; CHECK-LABEL: test_cmp_v16half_olt_rev:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    subq $56, %rsp
+; CHECK-NEXT:    vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT:    vpsllw $7, %xmm1, %xmm0
+; CHECK-NEXT:    vpmovb2m %xmm0, %k1
+; CHECK-NEXT:    kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
+; CHECK-NEXT:    callq test_call_16@PLT
+; CHECK-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
+; CHECK-NEXT:    vcmpltph {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %k0 {%k1} # 32-byte Folded Reload
+; CHECK-NEXT:    vpmovm2b %k0, %xmm0
+; CHECK-NEXT:    addq $56, %rsp
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+    %lhs = call <16 x half> @test_call_16()
+    %comp = fcmp olt <16 x half> %rhs, %lhs
+    %res = and <16 x i1> %comp, %mask
+    ret <16 x i1> %res
+}
+
+define <32 x i1> @test_cmp_v32half_oge(<32 x half> %rhs, <32 x i1> %mask) nounwind {
+; CHECK-LABEL: test_cmp_v32half_oge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    subq $88, %rsp
+; CHECK-NEXT:    vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
+; CHECK-NEXT:    vpsllw $7, %ymm1, %ymm0
+; CHECK-NEXT:    vpmovb2m %ymm0, %k1
+; CHECK-NEXT:    kmovd %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT:    callq test_call_32@PLT
+; CHECK-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 4-byte Reload
+; CHECK-NEXT:    vcmpleph {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k0 {%k1} # 64-byte Folded Reload
+; CHECK-NEXT:    vpmovm2b %k0, %ymm0
+; CHECK-NEXT:    addq $88, %rsp
+; CHECK-NEXT:    retq
+    %lhs = call <32 x half> @test_call_32()
+    %comp = fcmp oge <32 x half> %lhs, %rhs
+    %res = and <32 x i1> %comp, %mask
+    ret <32 x i1> %res
+}
+
+define <32 x i1> @test_cmp_v32half_oge_rev(<32 x half> %rhs, <32 x i1> %mask) nounwind {
+; CHECK-LABEL: test_cmp_v32half_oge_rev:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    subq $88, %rsp
+; CHECK-NEXT:    vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
+; CHECK-NEXT:    vpsllw $7, %ymm1, %ymm0
+; CHECK-NEXT:    vpmovb2m %ymm0, %k1
+; CHECK-NEXT:    kmovd %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT:    callq test_call_32@PLT
+; CHECK-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 4-byte Reload
+; CHECK-NEXT:    vcmpleph {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k0 {%k1} # 64-byte Folded Reload
+; CHECK-NEXT:    vpmovm2b %k0, %ymm0
+; CHECK-NEXT:    addq $88, %rsp
+; CHECK-NEXT:    retq
+    %lhs = call <32 x half> @test_call_32()
+    %comp = fcmp oge <32 x half> %rhs, %lhs
+    %res = and <32 x i1> %comp, %mask
+    ret <32 x i1> %res
+}

From 2d4c39e5b669b010fd0736132bef49c0e1859f5d Mon Sep 17 00:00:00 2001
From: Antoni Zwolski <antoni.zwolski@intel.com>
Date: Mon, 22 Sep 2025 11:37:21 +0200
Subject: [PATCH 2/4] [X86] Rename _rev to _commute

---
 llvm/test/CodeGen/X86/pr159723.ll | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/llvm/test/CodeGen/X86/pr159723.ll b/llvm/test/CodeGen/X86/pr159723.ll
index f11a058d97c63..cab4abb043639 100644
--- a/llvm/test/CodeGen/X86/pr159723.ll
+++ b/llvm/test/CodeGen/X86/pr159723.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16 -mattr=+avx512vl -O2| FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl| FileCheck %s
 
 declare <8 x half> @test_call_8()
 
@@ -27,8 +27,8 @@ define <8 x i1> @test_cmp_v8half_ogt(<8 x half> %rhs, <8 x i1> %mask) nounwind {
     ret <8 x i1> %res
 }
 
-define <8 x i1> @test_cmp_v8half_ogt_rev(<8 x half> %rhs, <8 x i1> %mask) nounwind {
-; CHECK-LABEL: test_cmp_v8half_ogt_rev:
+define <8 x i1> @test_cmp_v8half_ogt_commute(<8 x half> %rhs, <8 x i1> %mask) nounwind {
+; CHECK-LABEL: test_cmp_v8half_ogt_commute:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subq $40, %rsp
 ; CHECK-NEXT:    vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -69,8 +69,8 @@ define <16 x i1> @test_cmp_v16half_olt(<16 x half> %rhs, <16 x i1> %mask) nounwi
     ret <16 x i1> %res
 }
 
-define <16 x i1> @test_cmp_v16half_olt_rev(<16 x half> %rhs, <16 x i1> %mask) nounwind {
-; CHECK-LABEL: test_cmp_v16half_olt_rev:
+define <16 x i1> @test_cmp_v16half_olt_commute(<16 x half> %rhs, <16 x i1> %mask) nounwind {
+; CHECK-LABEL: test_cmp_v16half_olt_commute:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subq $56, %rsp
 ; CHECK-NEXT:    vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -110,8 +110,8 @@ define <32 x i1> @test_cmp_v32half_oge(<32 x half> %rhs, <32 x i1> %mask) nounwi
     ret <32 x i1> %res
 }
 
-define <32 x i1> @test_cmp_v32half_oge_rev(<32 x half> %rhs, <32 x i1> %mask) nounwind {
-; CHECK-LABEL: test_cmp_v32half_oge_rev:
+define <32 x i1> @test_cmp_v32half_oge_commute(<32 x half> %rhs, <32 x i1> %mask) nounwind {
+; CHECK-LABEL: test_cmp_v32half_oge_commute:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subq $88, %rsp
 ; CHECK-NEXT:    vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill

From 6387c24417157f0d412dffbd1ba5ae6cb0e95d86 Mon Sep 17 00:00:00 2001
From: Antoni Zwolski <antoni.zwolski@intel.com>
Date: Mon, 1 Sep 2025 13:04:17 +0200
Subject: [PATCH 3/4] Support masked VCMPPHZ instruction cases in
 commuteInstructionImpl and findCommutedOpIndices

---
 llvm/lib/Target/X86/X86InstrInfo.cpp | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 58d526269ff3c..497441d8b6f93 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -2573,10 +2573,13 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
   case X86::VCMPPSZ256rri:
   case X86::VCMPPDZrrik:
   case X86::VCMPPSZrrik:
+  case X86::VCMPPHZrrik:
   case X86::VCMPPDZ128rrik:
   case X86::VCMPPSZ128rrik:
+  case X86::VCMPPHZ128rrik:
   case X86::VCMPPDZ256rrik:
   case X86::VCMPPSZ256rrik:
+  case X86::VCMPPHZ256rrik:
     WorkingMI = CloneIfNew(MI);
     WorkingMI->getOperand(MI.getNumExplicitOperands() - 1)
         .setImm(X86::getSwappedVCMPImm(
@@ -2830,10 +2833,13 @@ bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
   case X86::VCMPPSZ256rri:
   case X86::VCMPPDZrrik:
   case X86::VCMPPSZrrik:
+  case X86::VCMPPHZrrik:
   case X86::VCMPPDZ128rrik:
   case X86::VCMPPSZ128rrik:
+  case X86::VCMPPHZ128rrik:
   case X86::VCMPPDZ256rrik:
-  case X86::VCMPPSZ256rrik: {
+  case X86::VCMPPSZ256rrik:
+  case X86::VCMPPHZ256rrik: {
     unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
 
     // Float comparison can be safely commuted for

From 2bf1f6f8b755a1698e938a8756281d18b3d395cd Mon Sep 17 00:00:00 2001
From: Antoni Zwolski <antoni.zwolski@intel.com>
Date: Tue, 23 Sep 2025 15:26:11 +0200
Subject: [PATCH 4/4] [X86] Update llc test checks for pr159723.ll

---
 llvm/test/CodeGen/X86/pr159723.ll | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/test/CodeGen/X86/pr159723.ll b/llvm/test/CodeGen/X86/pr159723.ll
index cab4abb043639..c66b101fff990 100644
--- a/llvm/test/CodeGen/X86/pr159723.ll
+++ b/llvm/test/CodeGen/X86/pr159723.ll
@@ -17,7 +17,7 @@ define <8 x i1> @test_cmp_v8half_ogt(<8 x half> %rhs, <8 x i1> %mask) nounwind {
 ; CHECK-NEXT:    kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
 ; CHECK-NEXT:    callq test_call_8@PLT
 ; CHECK-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
-; CHECK-NEXT:    vcmpltph {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %k0 {%k1} # 16-byte Folded Reload
+; CHECK-NEXT:    vcmpgtph {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %k0 {%k1} # 16-byte Folded Reload
 ; CHECK-NEXT:    vpmovm2w %k0, %xmm0
 ; CHECK-NEXT:    addq $40, %rsp
 ; CHECK-NEXT:    retq
@@ -79,7 +79,7 @@ define <16 x i1> @test_cmp_v16half_olt_commute(<16 x half> %rhs, <16 x i1> %mask
 ; CHECK-NEXT:    kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
 ; CHECK-NEXT:    callq test_call_16@PLT
 ; CHECK-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
-; CHECK-NEXT:    vcmpltph {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %k0 {%k1} # 32-byte Folded Reload
+; CHECK-NEXT:    vcmpgtph {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %k0 {%k1} # 32-byte Folded Reload
 ; CHECK-NEXT:    vpmovm2b %k0, %xmm0
 ; CHECK-NEXT:    addq $56, %rsp
 ; CHECK-NEXT:    vzeroupper
@@ -100,7 +100,7 @@ define <32 x i1> @test_cmp_v32half_oge(<32 x half> %rhs, <32 x i1> %mask) nounwi
 ; CHECK-NEXT:    kmovd %k1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
 ; CHECK-NEXT:    callq test_call_32@PLT
 ; CHECK-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 4-byte Reload
-; CHECK-NEXT:    vcmpleph {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k0 {%k1} # 64-byte Folded Reload
+; CHECK-NEXT:    vcmpgeph {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k0 {%k1} # 64-byte Folded Reload
 ; CHECK-NEXT:    vpmovm2b %k0, %ymm0
 ; CHECK-NEXT:    addq $88, %rsp
 ; CHECK-NEXT:    retq