diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 50891da333f01..21dbb7cbc9844 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -811,6 +811,7 @@ struct RISCVOperand final : public MCParsedAsmOperand { bool isSImm6() const { return isSImm<6>(); } bool isSImm10() const { return isSImm<10>(); } bool isSImm11() const { return isSImm<11>(); } + bool isSImm12() const { return isSImm<12>(); } bool isSImm16() const { return isSImm<16>(); } bool isSImm26() const { return isSImm<26>(); } @@ -859,7 +860,7 @@ struct RISCVOperand final : public MCParsedAsmOperand { return SignExtend64<32>(Imm); } - bool isSImm12() const { + bool isSImm12LO() const { if (!isExpr()) return false; @@ -1599,6 +1600,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidUImm16NonZero: return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 16) - 1); case Match_InvalidSImm12: + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 11), + (1 << 11) - 1); + case Match_InvalidSImm12LO: return generateImmOutOfRangeError( Operands, ErrorInfo, -(1 << 11), (1 << 11) - 1, "operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an " diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td index a9ecf44e8da1e..2e5f30f8fe35a 100644 --- a/llvm/lib/Target/RISCV/RISCVGISel.td +++ b/llvm/lib/Target/RISCV/RISCVGISel.td @@ -41,12 +41,12 @@ def GIImmPlus1 : def PtrVT : PtrValueTypeByHwMode; // Define pattern expansions for pointer ult/slt conditional codes -def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12:$imm12)), - (SLTIU GPR:$rs1, simm12:$imm12)>; +def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12_lo:$imm12)), + (SLTIU GPR:$rs1, simm12_lo:$imm12)>; def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))), (SLTU GPR:$rs1, GPR:$rs2)>; -def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), simm12:$imm12)), - (SLTI GPR:$rs1, simm12:$imm12)>; +def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), simm12_lo:$imm12)), + (SLTI GPR:$rs1, simm12_lo:$imm12)>; def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))), (SLT GPR:$rs1, GPR:$rs2)>; @@ -72,12 +72,12 @@ def : Pat<(XLenVT (setgt (Ty GPR:$rs1), (Ty simm12Minus1Nonzero:$imm))), (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12Minus1Nonzero:$imm)), 1)>; def : Pat<(XLenVT (setgt (Ty GPR:$rs1), (Ty GPR:$rs2))), (SLT GPR:$rs2, GPR:$rs1)>; -def : Pat<(XLenVT (setuge (XLenVT GPR:$rs1), (Ty simm12:$imm))), - (XORI (SLTIU GPR:$rs1, simm12:$imm), 1)>; +def : Pat<(XLenVT (setuge (XLenVT GPR:$rs1), (Ty simm12_lo:$imm))), + (XORI (SLTIU GPR:$rs1, simm12_lo:$imm), 1)>; def : Pat<(XLenVT (setuge (Ty GPR:$rs1), (Ty GPR:$rs2))), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>; -def : Pat<(XLenVT (setge (Ty GPR:$rs1), (Ty simm12:$imm))), - (XORI (SLTI GPR:$rs1, simm12:$imm), 1)>; +def : Pat<(XLenVT (setge (Ty GPR:$rs1), (Ty simm12_lo:$imm))), + (XORI (SLTI GPR:$rs1, simm12_lo:$imm), 1)>; def : Pat<(XLenVT (setge (Ty GPR:$rs1), (Ty GPR:$rs2))), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>; def : Pat<(XLenVT (setule (Ty GPR:$rs1), (Ty simm12Minus1NonzeroNonNeg1:$imm))), @@ -143,8 +143,8 @@ def : Pat<(anyext (i32 GPR:$src)), (COPY GPR:$src)>; def : Pat<(sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>; def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>; -def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12:$imm)), i32), - (ADDIW GPR:$rs1, simm12:$imm)>; +def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12_lo:$imm)), i32), + (ADDIW GPR:$rs1, simm12_lo:$imm)>; // Use sext if the sign bit of the input is 0. def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 9825733e29897..9855c47a63392 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -340,7 +340,9 @@ def uimm16 : RISCVUImmOp<16>; def uimm32 : RISCVUImmOp<32>; def uimm48 : RISCVUImmOp<48>; def uimm64 : RISCVUImmOp<64>; -def simm12 : RISCVSImmLeafOp<12> { + +def simm12_lo : RISCVSImmLeafOp<12> { + let ParserMatchClass = SImmAsmOperand<12, "LO">; let MCOperandPredicate = [{ int64_t Imm; if (MCOp.evaluateAsConstantImm(Imm)) @@ -642,7 +644,7 @@ class BranchCC_rri funct3, string opcodestr> let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { class Load_ri funct3, string opcodestr, DAGOperand rty = GPR> - : RVInstI; class HLoad_r funct7, bits<5> funct5, string opcodestr> @@ -658,7 +660,7 @@ class HLoad_r funct7, bits<5> funct5, string opcodestr> let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { class Store_rri funct3, string opcodestr, DAGOperand rty = GPR> : RVInstS; class HStore_rr funct7, string opcodestr> @@ -671,7 +673,7 @@ class HStore_rr funct7, string opcodestr> let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class ALU_ri funct3, string opcodestr> - : RVInstI, Sched<[WriteIALU, ReadIALU]>; @@ -754,7 +756,7 @@ def JAL : RVInstJ, Sched<[WriteJal]>; def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd), - (ins GPR:$rs1, simm12:$imm12), + (ins GPR:$rs1, simm12_lo:$imm12), "jalr", "$rd, ${imm12}(${rs1})">, Sched<[WriteJalr, ReadJalr]>; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 @@ -894,7 +896,7 @@ def SD : Store_rri<0b011, "sd">, Sched<[WriteSTD, ReadStoreData, ReadMemBase] let IsSignExtendingOpW = 1 in { let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in def ADDIW : RVInstI<0b000, OPC_OP_IMM_32, (outs GPR:$rd), - (ins GPR:$rs1, simm12:$imm12), + (ins GPR:$rs1, simm12_lo:$imm12), "addiw", "$rd, $rs1, $imm12">, Sched<[WriteIALU32, ReadIALU32]>; @@ -1041,7 +1043,7 @@ def PseudoSD : PseudoStore<"sd">; } // Predicates = [IsRV64] def : InstAlias<"nop", (ADDI X0, X0, 0), 3>; -def : InstAlias<"li $rd, $imm", (ADDI GPR:$rd, X0, simm12:$imm), 2>; +def : InstAlias<"li $rd, $imm", (ADDI GPR:$rd, X0, simm12_lo:$imm), 2>; def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>; def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>; @@ -1094,16 +1096,16 @@ def : InstAlias<"jal $offset", (JAL X1, simm21_lsb0_jal:$offset)>; // Non-zero offset aliases of "jalr" are the lowest weight, followed by the // two-register form, then the one-register forms and finally "ret". def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0), 3>; -def : InstAlias<"jr ${offset}(${rs})", (JALR X0, GPR:$rs, simm12:$offset)>; +def : InstAlias<"jr ${offset}(${rs})", (JALR X0, GPR:$rs, simm12_lo:$offset)>; def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0), 3>; -def : InstAlias<"jalr ${offset}(${rs})", (JALR X1, GPR:$rs, simm12:$offset)>; +def : InstAlias<"jalr ${offset}(${rs})", (JALR X1, GPR:$rs, simm12_lo:$offset)>; def : InstAlias<"jalr $rd, $rs", (JALR GPR:$rd, GPR:$rs, 0), 2>; def : InstAlias<"ret", (JALR X0, X1, 0), 4>; // Non-canonical forms for jump targets also accepted by the assembler. -def : InstAlias<"jr $rs, $offset", (JALR X0, GPR:$rs, simm12:$offset), 0>; -def : InstAlias<"jalr $rs, $offset", (JALR X1, GPR:$rs, simm12:$offset), 0>; -def : InstAlias<"jalr $rd, $rs, $offset", (JALR GPR:$rd, GPR:$rs, simm12:$offset), 0>; +def : InstAlias<"jr $rs, $offset", (JALR X0, GPR:$rs, simm12_lo:$offset), 0>; +def : InstAlias<"jalr $rs, $offset", (JALR X1, GPR:$rs, simm12_lo:$offset), 0>; +def : InstAlias<"jalr $rd, $rs, $offset", (JALR GPR:$rd, GPR:$rs, simm12_lo:$offset), 0>; def : InstAlias<"jr (${rs})", (JALR X0, GPR:$rs, 0), 0>; def : InstAlias<"jalr (${rs})", (JALR X1, GPR:$rs, 0), 0>; def : InstAlias<"jalr $rd, (${rs})", (JALR GPR:$rd, GPR:$rs, 0), 0>; @@ -1178,13 +1180,13 @@ def : InstAlias<"sw $rs2, (${rs1})", (SW GPR:$rs2, GPR:$rs1, 0)>; def : InstAlias<"add $rd, $rs1, $imm12", - (ADDI GPR:$rd, GPR:$rs1, simm12:$imm12)>; + (ADDI GPR:$rd, GPR:$rs1, simm12_lo:$imm12)>; def : InstAlias<"and $rd, $rs1, $imm12", - (ANDI GPR:$rd, GPR:$rs1, simm12:$imm12)>; + (ANDI GPR:$rd, GPR:$rs1, simm12_lo:$imm12)>; def : InstAlias<"xor $rd, $rs1, $imm12", - (XORI GPR:$rd, GPR:$rs1, simm12:$imm12)>; + (XORI GPR:$rd, GPR:$rs1, simm12_lo:$imm12)>; def : InstAlias<"or $rd, $rs1, $imm12", - (ORI GPR:$rd, GPR:$rs1, simm12:$imm12)>; + (ORI GPR:$rd, GPR:$rs1, simm12_lo:$imm12)>; def : InstAlias<"sll $rd, $rs1, $shamt", (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; def : InstAlias<"srl $rd, $rs1, $shamt", @@ -1200,7 +1202,7 @@ def : InstAlias<"sd $rs2, (${rs1})", (SD GPR:$rs2, GPR:$rs1, 0)>; def : InstAlias<"addw $rd, $rs1, $imm12", - (ADDIW GPR:$rd, GPR:$rs1, simm12:$imm12)>; + (ADDIW GPR:$rd, GPR:$rs1, simm12_lo:$imm12)>; def : InstAlias<"sllw $rd, $rs1, $shamt", (SLLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; def : InstAlias<"srlw $rd, $rs1, $shamt", @@ -1209,9 +1211,9 @@ def : InstAlias<"sraw $rd, $rs1, $shamt", (SRAIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; } // Predicates = [IsRV64] def : InstAlias<"slt $rd, $rs1, $imm12", - (SLTI GPR:$rd, GPR:$rs1, simm12:$imm12)>; + (SLTI GPR:$rd, GPR:$rs1, simm12_lo:$imm12)>; def : InstAlias<"sltu $rd, $rs1, $imm12", - (SLTIU GPR:$rd, GPR:$rs1, simm12:$imm12)>; + (SLTIU GPR:$rd, GPR:$rs1, simm12_lo:$imm12)>; } def : MnemonicAlias<"move", "mv">; @@ -1284,12 +1286,12 @@ def InsnR4 : DirectiveInsnR4<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode, AnyReg:$rs3), "$opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3">; def InsnI : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode, uimm3:$funct3, - AnyReg:$rs1, simm12:$imm12), + AnyReg:$rs1, simm12_lo:$imm12), "$opcode, $funct3, $rd, $rs1, $imm12">; def InsnI_Mem : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1, - simm12:$imm12), + simm12_lo:$imm12), "$opcode, $funct3, $rd, ${imm12}(${rs1})">; def InsnB : DirectiveInsnB<(outs), (ins uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1, AnyReg:$rs2, @@ -1303,7 +1305,7 @@ def InsnJ : DirectiveInsnJ<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode, "$opcode, $rd, $imm20">; def InsnS : DirectiveInsnS<(outs), (ins uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs2, AnyReg:$rs1, - simm12:$imm12), + simm12_lo:$imm12), "$opcode, $funct3, $rs2, ${imm12}(${rs1})">; } // isCodeGenOnly, hasSideEffects, mayLoad, mayStore, hasNoSchedulingInfo @@ -1324,10 +1326,10 @@ def : InstAlias<".insn_r4 $opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3", AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>; def : InstAlias<".insn_i $opcode, $funct3, $rd, $rs1, $imm12", (InsnI AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1, - simm12:$imm12)>; + simm12_lo:$imm12)>; def : InstAlias<".insn_i $opcode, $funct3, $rd, ${imm12}(${rs1})", (InsnI_Mem AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3, - AnyReg:$rs1, simm12:$imm12)>; + AnyReg:$rs1, simm12_lo:$imm12)>; def : InstAlias<".insn_i $opcode, $funct3, $rd, (${rs1})", (InsnI_Mem AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1, 0)>; @@ -1347,7 +1349,7 @@ def : InstAlias<".insn_uj $opcode, $rd, $imm20", (InsnJ AnyReg:$rd, uimm7_opcode:$opcode, simm21_lsb0_jal:$imm20)>; def : InstAlias<".insn_s $opcode, $funct3, $rs2, ${imm12}(${rs1})", (InsnS uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs2, - AnyReg:$rs1, simm12:$imm12)>; + AnyReg:$rs1, simm12_lo:$imm12)>; def : InstAlias<".insn_s $opcode, $funct3, $rs2, (${rs1})", (InsnS uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs2, AnyReg:$rs1, 0)>; @@ -1374,7 +1376,7 @@ class PatGprImm; class PatGprSimm12 - : PatGprImm; + : PatGprImm; class PatGprUimmLog2XLen : PatGprImm; @@ -1542,8 +1544,8 @@ def : GICustomOperandRenderer<"renderFrameIndex">, def : Pat<(frameindex:$fi), (ADDI (iPTR (to_tframeindex $fi)), 0)>; -def : Pat<(add_like frameindex:$fi, simm12:$offset), - (ADDI (iPTR (to_tframeindex $fi)), simm12:$offset)>; +def : Pat<(add_like frameindex:$fi, simm12_lo:$offset), + (ADDI (iPTR (to_tframeindex $fi)), simm12_lo:$offset)>; def GIAddrRegImm : GIComplexOperandMatcher, @@ -1576,7 +1578,7 @@ def PROBED_STACKALLOC_DYN : Pseudo<(outs), // It will be expanded after register allocation. // FIXME: The scheduling information does not reflect the multiple instructions. let Size = 8, isReMaterializable = 1 in -def PseudoMovAddr : Pseudo<(outs GPR:$dst), (ins uimm20_lui:$hi, simm12:$lo), []>, +def PseudoMovAddr : Pseudo<(outs GPR:$dst), (ins uimm20_lui:$hi, simm12_lo:$lo), []>, Sched<[WriteIALU]>; def riscv_hi_oneuse : unop_oneuse; @@ -1673,7 +1675,7 @@ defm Select_GPR : SelectCC_GPR_rrirr; class SelectCompressOpt : Pat<(riscv_selectcc_frag:$select (XLenVT GPR:$lhs), simm12_no6:$Constant, Cond, (XLenVT GPR:$truev), GPR:$falsev), - (Select_GPR_Using_CC_GPR (XLenVT (ADDI GPR:$lhs, (NegImm simm12:$Constant))), (XLenVT X0), + (Select_GPR_Using_CC_GPR (XLenVT (ADDI GPR:$lhs, (NegImm simm12_lo:$Constant))), (XLenVT X0), (IntCCtoRISCVCC $select), GPR:$truev, GPR:$falsev)>; def OptForMinSize : Predicate<"MF ? MF->getFunction().hasMinSize() : false">; @@ -1712,7 +1714,7 @@ multiclass BccPat { class BrccCompressOpt : Pat<(riscv_brcc GPR:$lhs, simm12_no6:$Constant, Cond, bb:$place), - (Inst (XLenVT (ADDI GPR:$lhs, (NegImm simm12:$Constant))), + (Inst (XLenVT (ADDI GPR:$lhs, (NegImm simm12_lo:$Constant))), (XLenVT X0), bb:$place)>; defm : BccPat; @@ -1753,33 +1755,33 @@ def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>, let Predicates = [NoStdExtZicfilp], isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in -def PseudoBRIND : Pseudo<(outs), (ins GPRJALR:$rs1, simm12:$imm12), []>, - PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>; +def PseudoBRIND : Pseudo<(outs), (ins GPRJALR:$rs1, simm12_lo:$imm12), []>, + PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12_lo:$imm12)>; let Predicates = [HasStdExtZicfilp], isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in { -def PseudoBRINDNonX7 : Pseudo<(outs), (ins GPRJALRNonX7:$rs1, simm12:$imm12), []>, - PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>; -def PseudoBRINDX7 : Pseudo<(outs), (ins GPRX7:$rs1, simm12:$imm12), []>, - PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>; +def PseudoBRINDNonX7 : Pseudo<(outs), (ins GPRJALRNonX7:$rs1, simm12_lo:$imm12), []>, + PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12_lo:$imm12)>; +def PseudoBRINDX7 : Pseudo<(outs), (ins GPRX7:$rs1, simm12_lo:$imm12), []>, + PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12_lo:$imm12)>; } // For Zicfilp, need to avoid using X7/T2 for indirect branches which need // landing pad. let Predicates = [HasStdExtZicfilp] in { def : Pat<(brind GPRJALRNonX7:$rs1), (PseudoBRINDNonX7 GPRJALRNonX7:$rs1, 0)>; -def : Pat<(brind (add GPRJALRNonX7:$rs1, simm12:$imm12)), - (PseudoBRINDNonX7 GPRJALRNonX7:$rs1, simm12:$imm12)>; +def : Pat<(brind (add GPRJALRNonX7:$rs1, simm12_lo:$imm12)), + (PseudoBRINDNonX7 GPRJALRNonX7:$rs1, simm12_lo:$imm12)>; def : Pat<(riscv_sw_guarded_brind GPRX7:$rs1), (PseudoBRINDX7 GPRX7:$rs1, 0)>; -def : Pat<(riscv_sw_guarded_brind (add GPRX7:$rs1, simm12:$imm12)), - (PseudoBRINDX7 GPRX7:$rs1, simm12:$imm12)>; +def : Pat<(riscv_sw_guarded_brind (add GPRX7:$rs1, simm12_lo:$imm12)), + (PseudoBRINDX7 GPRX7:$rs1, simm12_lo:$imm12)>; } let Predicates = [NoStdExtZicfilp] in { def : Pat<(brind GPRJALR:$rs1), (PseudoBRIND GPRJALR:$rs1, 0)>; -def : Pat<(brind (add GPRJALR:$rs1, simm12:$imm12)), - (PseudoBRIND GPRJALR:$rs1, simm12:$imm12)>; +def : Pat<(brind (add GPRJALR:$rs1, simm12_lo:$imm12)), + (PseudoBRIND GPRJALR:$rs1, simm12_lo:$imm12)>; } // PseudoCALLReg is a generic pseudo instruction for calls which will eventually @@ -1942,7 +1944,7 @@ def tlsdesc_call_symbol : Operand { let isCall = 1, isBarrier = 1, isCodeGenOnly = 0, Size = 8, hasSideEffects = 0, mayStore = 0, mayLoad = 0 in def PseudoTLSDESCCall : Pseudo<(outs GPR:$rd), - (ins GPR:$rs1, simm12:$imm12, tlsdesc_call_symbol:$src), [], + (ins GPR:$rs1, simm12_lo:$imm12, tlsdesc_call_symbol:$src), [], "jalr", "$rd, ${imm12}(${rs1}), $src">, Sched<[WriteJalr, ReadJalr]> { let Defs = [X10]; @@ -1971,8 +1973,8 @@ def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs /// Loads class LdPat - : Pat<(vt (LoadOp (AddrRegImm (XLenVT GPRMem:$rs1), simm12:$imm12))), - (Inst GPRMem:$rs1, simm12:$imm12)>; + : Pat<(vt (LoadOp (AddrRegImm (XLenVT GPRMem:$rs1), simm12_lo:$imm12))), + (Inst GPRMem:$rs1, simm12_lo:$imm12)>; def : LdPat; def : LdPat; // Prefer unsigned due to no c.lb in Zcb. @@ -1987,8 +1989,8 @@ def : LdPat; class StPat : Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (XLenVT GPRMem:$rs1), - simm12:$imm12)), - (Inst StTy:$rs2, GPRMem:$rs1, simm12:$imm12)>; + simm12_lo:$imm12)), + (Inst StTy:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>; def : StPat; def : StPat; @@ -2228,8 +2230,8 @@ def : PatGprImm, XORI, u32simm12>; // Select 'or' as ADDIW if the immediate bits are known to be 0 in $rs1 and // $rs1 is sign extended. This can improve compressibility. Using ADDIW gives // more power to RISCVOptWInstrs. -def : Pat<(riscv_or_disjoint 33signbits_node:$rs1, simm12:$imm), - (ADDIW $rs1, simm12:$imm)>; +def : Pat<(riscv_or_disjoint 33signbits_node:$rs1, simm12_lo:$imm), + (ADDIW $rs1, simm12_lo:$imm)>; /// Loads diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td index 3d9737e3645d5..b9510efc2fba1 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -529,11 +529,11 @@ def PseudoFROUND_D_IN32X : PseudoFROUND; /// Loads let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in -def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12:$imm12), []>; +def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12_lo:$imm12), []>; /// Stores let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in -def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>; +def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12_lo:$imm12), []>; } // Predicates = [HasStdExtZdinx, IsRV32] let Predicates = [HasStdExtZdinx, HasStdExtZilsd, IsRV32] in { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td index 2c1cf77acff56..fde030ecc3b89 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -196,7 +196,7 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in class FPLoad_r funct3, string opcodestr, DAGOperand rty, SchedWrite sw> : RVInstI, Sched<[sw, ReadFMemBase]>; @@ -204,7 +204,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in class FPStore_r funct3, string opcodestr, DAGOperand rty, SchedWrite sw> : RVInstS, Sched<[sw, ReadFStoreData, ReadFMemBase]>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td index f732ab13e5f88..0114fbdc56302 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td @@ -60,7 +60,7 @@ class SFBALU_rr class SFBALU_ri : Pseudo<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, - simm12:$imm), []>, + simm12_lo:$imm), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]> { let hasSideEffects = 0; let mayLoad = 0; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td index 996e08bd0a27d..d8f5d3e09d374 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td @@ -271,7 +271,7 @@ class CVInstImmBranch funct3, dag outs, dag ins, let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { class CVLoad_ri_inc funct3, string opcodestr> : RVInstI { let Constraints = "$rs1_wb = $rs1"; } @@ -292,7 +292,7 @@ class CVLoad_rr funct7, bits<3> funct3, string opcodestr> let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { class CVStore_ri_inc funct3, string opcodestr> : RVInstS { let Constraints = "$rs1_wb = $rs1"; } @@ -332,7 +332,7 @@ class CVStore_rr funct3, bits<7> funct7, string opcodestr> class CVLoad_ri funct3, string opcodestr> : RVInstI; + (ins GPRMem:$rs1, simm12_lo:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">; //===----------------------------------------------------------------------===// // Instructions @@ -673,8 +673,8 @@ class CVLdrrPat (Inst CVrr:$regreg)>; class CVStriPat - : Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, simm12:$imm12), - (Inst GPR:$rs2, GPR:$rs1, simm12:$imm12)>; + : Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, simm12_lo:$imm12), + (Inst GPR:$rs2, GPR:$rs1, simm12_lo:$imm12)>; class CVStrriPat : Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, GPR:$rs3), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 808d9117a1746..13b02d1b2d6db 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -953,7 +953,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { } def QC_MULIADD : RVInstI<0b110, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb), - (ins GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12), + (ins GPRNoX0:$rd, GPRNoX0:$rs1, simm12_lo:$imm12), "qc.muliadd", "$rd, $rs1, $imm12"> { let Constraints = "$rd = $rd_wb"; } @@ -1411,8 +1411,8 @@ class SelectQCbi (IntCCtoRISCVCC $cc), GPRNoX0:$truev, GPRNoX0:$falsev)>; let Predicates = [HasVendorXqciac, IsRV32] in { -def : Pat<(i32 (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12:$imm12))), - (QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12)>; +def : Pat<(i32 (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12_lo:$imm12))), + (QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12_lo:$imm12)>; def : Pat<(i32 (add_like_non_imm12 (shl GPRNoX0:$rs1, uimm5gt3:$imm), GPRNoX0:$rs2)), (QC_SHLADD GPRNoX0:$rs1, GPRNoX0:$rs2, uimm5gt3:$imm)>; def : Pat<(i32 (riscv_shl_add GPRNoX0:$rs1, uimm5gt3:$imm, GPRNoX0:$rs2)), @@ -1667,27 +1667,27 @@ def : CompressPat<(QC_E_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm), (C_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>; def : CompressPat<(QC_E_LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm), (C_LWSP GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>; -def : CompressPat<(QC_E_LB GPR:$rd, GPRMem:$rs1, simm12:$imm12), - (LB GPR:$rd, GPRMem:$rs1, simm12:$imm12)>; -def : CompressPat<(QC_E_LBU GPR:$rd, GPRMem:$rs1, simm12:$imm12), - (LBU GPR:$rd, GPRMem:$rs1, simm12:$imm12)>; -def : CompressPat<(QC_E_LH GPR:$rd, GPRMem:$rs1, simm12:$imm12), - (LH GPR:$rd, GPRMem:$rs1, simm12:$imm12)>; -def : CompressPat<(QC_E_LHU GPR:$rd, GPRMem:$rs1, simm12:$imm12), - (LHU GPR:$rd, GPRMem:$rs1, simm12:$imm12)>; -def : CompressPat<(QC_E_LW GPR:$rd, GPRMem:$rs1, simm12:$imm12), - (LW GPR:$rd, GPRMem:$rs1, simm12:$imm12)>; +def : CompressPat<(QC_E_LB GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12), + (LB GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>; +def : CompressPat<(QC_E_LBU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12), + (LBU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>; +def : CompressPat<(QC_E_LH GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12), + (LH GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>; +def : CompressPat<(QC_E_LHU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12), + (LHU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>; +def : CompressPat<(QC_E_LW GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12), + (LW GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>; def : CompressPat<(QC_E_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm), (C_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>; def : CompressPat<(QC_E_SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm), (C_SWSP GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>; -def : CompressPat<(QC_E_SB GPR:$rs2, GPRMem:$rs1, simm12:$imm12), - (SB GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>; -def : CompressPat<(QC_E_SH GPR:$rs2, GPRMem:$rs1, simm12:$imm12), - (SH GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>; -def : CompressPat<(QC_E_SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12), - (SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>; +def : CompressPat<(QC_E_SB GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12), + (SB GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>; +def : CompressPat<(QC_E_SH GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12), + (SH GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>; +def : CompressPat<(QC_E_SW GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12), + (SW GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>; } // isCompressOnly = true, Predicates = [HasVendorXqcilo, IsRV32] let Predicates = [HasVendorXqcicm, IsRV32] in { @@ -1752,23 +1752,23 @@ def : CompressPat<(QC_E_ADDAI X2, simm10_lsb0000nonzero:$imm), def : CompressPat<(QC_E_ADDI X2, X2, simm10_lsb0000nonzero:$imm), (C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>; -def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm), - (ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>; -def : CompressPat<(QC_E_ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm), - (ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>; -def : CompressPat<(QC_E_ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm), - (ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>; -def : CompressPat<(QC_E_XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm), - (XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>; - -def : CompressPat<(QC_E_ADDAI GPRNoX0:$rd, simm12:$imm), - (ADDI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>; -def : CompressPat<(QC_E_ANDAI GPRNoX0:$rd, simm12:$imm), - (ANDI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>; -def : CompressPat<(QC_E_ORAI GPRNoX0:$rd, simm12:$imm), - (ORI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>; -def : CompressPat<(QC_E_XORAI GPRNoX0:$rd, simm12:$imm), - (XORI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>; +def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm), + (ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm)>; +def : CompressPat<(QC_E_ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm), + (ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm)>; +def : CompressPat<(QC_E_ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm), + (ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm)>; +def : CompressPat<(QC_E_XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm), + (XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm)>; + +def : CompressPat<(QC_E_ADDAI GPRNoX0:$rd, simm12_lo:$imm), + (ADDI GPRNoX0:$rd, GPRNoX0:$rd, simm12_lo:$imm)>; +def : CompressPat<(QC_E_ANDAI GPRNoX0:$rd, simm12_lo:$imm), + (ANDI GPRNoX0:$rd, GPRNoX0:$rd, simm12_lo:$imm)>; +def : CompressPat<(QC_E_ORAI GPRNoX0:$rd, simm12_lo:$imm), + (ORI GPRNoX0:$rd, GPRNoX0:$rd, simm12_lo:$imm)>; +def : CompressPat<(QC_E_XORAI GPRNoX0:$rd, simm12_lo:$imm), + (XORI GPRNoX0:$rd, GPRNoX0:$rd, simm12_lo:$imm)>; } // let isCompressOnly = true, Predicates = [HasVendorXqcilia, IsRV32] let isCompressOnly = true, Predicates = [HasVendorXqciac, IsRV32] in {