From 908c6b89967a9ee94d1e52abc11d8814b8374219 Mon Sep 17 00:00:00 2001 From: himadhith Date: Wed, 24 Sep 2025 09:36:23 +0000 Subject: [PATCH 1/2] [NFC] NFC patch to lockdown instructions of vspltisw for addition of vector of 1s --- llvm/test/CodeGen/PowerPC/vector-all-ones.ll | 35 ++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/vector-all-ones.ll diff --git a/llvm/test/CodeGen/PowerPC/vector-all-ones.ll b/llvm/test/CodeGen/PowerPC/vector-all-ones.ll new file mode 100644 index 0000000000000..0fa4b3417245a --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vector-all-ones.ll @@ -0,0 +1,35 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64LE + +; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc64-ibm-aix \ +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64 + +; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc-ibm-aix \ +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_32 + +; Currently the generated code uses `vspltisw` to generate vector of 1s followed by add operation. +; This pattern is expected to be optimized in a future patch by using `xxleqv` to generate vector of -1s +; followed by subtraction operation. +define dso_local noundef <4 x i32> @test1(<4 x i32> %a) { +; POWERPC_64LE-LABEL: test1: +; POWERPC_64LE: # %bb.0: # %entry +; POWERPC_64LE-NEXT: vspltisw v3, 1 +; POWERPC_64LE-NEXT: vadduwm v2, v2, v3 +; POWERPC_64LE-NEXT: blr +; +; POWERPC_64-LABEL: test1: +; POWERPC_64: # %bb.0: # %entry +; POWERPC_64-NEXT: vspltisw v3, 1 +; POWERPC_64-NEXT: vadduwm v2, v2, v3 +; POWERPC_64-NEXT: blr +; +; POWERPC_32-LABEL: test1: +; POWERPC_32: # %bb.0: # %entry +; POWERPC_32-NEXT: vspltisw v3, 1 +; POWERPC_32-NEXT: vadduwm v2, v2, v3 +; POWERPC_32-NEXT: blr +entry: + %add = add <4 x i32> %a, splat (i32 1) + ret <4 x i32> %add +} From e97366297bd8cf5d2f56fbe3dd54cd2532fe6e5e Mon Sep 17 00:00:00 2001 From: himadhith Date: Fri, 26 Sep 2025 18:24:48 +0000 Subject: [PATCH 2/2] Remove explicit --check-prefix and replace with default CHECKS --- llvm/test/CodeGen/PowerPC/vector-all-ones.ll | 28 ++++++-------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/llvm/test/CodeGen/PowerPC/vector-all-ones.ll b/llvm/test/CodeGen/PowerPC/vector-all-ones.ll index 0fa4b3417245a..e4c93adcf50a6 100644 --- a/llvm/test/CodeGen/PowerPC/vector-all-ones.ll +++ b/llvm/test/CodeGen/PowerPC/vector-all-ones.ll @@ -1,34 +1,22 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64LE +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc64-ibm-aix \ -; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64 +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc-ibm-aix \ -; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_32 +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s ; Currently the generated code uses `vspltisw` to generate vector of 1s followed by add operation. ; This pattern is expected to be optimized in a future patch by using `xxleqv` to generate vector of -1s ; followed by subtraction operation. define dso_local noundef <4 x i32> @test1(<4 x i32> %a) { -; POWERPC_64LE-LABEL: test1: -; POWERPC_64LE: # %bb.0: # %entry -; POWERPC_64LE-NEXT: vspltisw v3, 1 -; POWERPC_64LE-NEXT: vadduwm v2, v2, v3 -; POWERPC_64LE-NEXT: blr -; -; POWERPC_64-LABEL: test1: -; POWERPC_64: # %bb.0: # %entry -; POWERPC_64-NEXT: vspltisw v3, 1 -; POWERPC_64-NEXT: vadduwm v2, v2, v3 -; POWERPC_64-NEXT: blr -; -; POWERPC_32-LABEL: test1: -; POWERPC_32: # %bb.0: # %entry -; POWERPC_32-NEXT: vspltisw v3, 1 -; POWERPC_32-NEXT: vadduwm v2, v2, v3 -; POWERPC_32-NEXT: blr +; CHECK-LABEL: test1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vspltisw v3, 1 +; CHECK-NEXT: vadduwm v2, v2, v3 +; CHECK-NEXT: blr entry: %add = add <4 x i32> %a, splat (i32 1) ret <4 x i32> %add