diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index d89a9487c0da2..4ff2f8a54529f 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -360,8 +360,11 @@ def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true", //===----------------------------------------------------------------------===// // PowerPC Instruction Predicate Definitions. -def In32BitMode : Predicate<"!Subtarget->isPPC64()">; -def In64BitMode : Predicate<"Subtarget->isPPC64()">; + +def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">; +def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">; +def IsPPC32 : Predicate<"!Subtarget->isPPC64()">; +def IsPPC64 : Predicate<"Subtarget->isPPC64()">; def IsBookE : Predicate<"Subtarget->isBookE()">; def IsNotBookE : Predicate<"!Subtarget->isBookE()">; def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; @@ -379,27 +382,50 @@ def NaNsFPMath : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; +def HasFPU : Predicate<"Subtarget->hasFPU()">; +def HasHTM : Predicate<"Subtarget->hasHTM()">; +def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">; +def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">; +def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; +def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; +def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">; +def MMA : Predicate<"Subtarget->hasMMA()">; + +// Vector support predicates +def HasVSX : Predicate<"Subtarget->hasVSX()">; +def NoP8Vector : Predicate<"!Subtarget->hasP8Vector()">; +def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">; +def HasAltivec : Predicate<"Subtarget->hasAltivec()">; +def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">; +def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">; +def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">; +def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">; +def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">; +def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">; +def NoP10Vector : Predicate<"!Subtarget->hasP10Vector()">; +def HasP10Vector : Predicate<"Subtarget->hasP10Vector()">; + +// Predicates used to differenciate between different ISAs. def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; -def HasFPU : Predicate<"Subtarget->hasFPU()">; -def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; +def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; +def IsISAFuture : Predicate<"Subtarget->isISAFuture()">; +def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">; // AIX assembler may not be modern enough to support some extended mne. def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; def IsAIX : Predicate<"Subtarget->isAIXABI()">; def NotAIX : Predicate<"!Subtarget->isAIXABI()">; -def IsISAFuture : Predicate<"Subtarget->isISAFuture()">; -def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">; //===----------------------------------------------------------------------===// // HwModes //===----------------------------------------------------------------------===// defvar PPC32 = DefaultMode; -def PPC64 : HwMode<[In64BitMode]>; +def PPC64 : HwMode<[IsPPC64]>; // Since new processors generally contain a superset of features of those that // came before them, the idea is to make implementations of new processors diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index 269d30318bca8..60efa4c8f0a37 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -76,23 +76,23 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, - [(PPCretglue)]>, Requires<[In64BitMode]>; + [(PPCretglue)]>, Requires<[IsPPC64]>; let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { let isPredicable = 1 in def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, []>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond), "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, []>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI), "bcctr 12, $BI, 0", IIC_BrB, []>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI), "bcctr 4, $BI, 0", IIC_BrB, []>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; } } @@ -160,20 +160,20 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in { let isPredicable = 1 in def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), "bctrl", IIC_BrB, [(PPCbctrl)]>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; let isCodeGenOnly = 1 in { def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond), "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, []>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI), "bcctrl 12, $BI, 0", IIC_BrB, []>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI), "bcctrl 4, $BI, 0", IIC_BrB, []>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; } } } @@ -207,7 +207,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0, let isPredicable = 1 in def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; } } @@ -218,7 +218,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, (ins (memrix $D, $RA):$src), "bctrl\n\tld 2, $src", IIC_BrB, [(PPCbctrl_load_toc iaddrX4:$src)]>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; } let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, @@ -228,7 +228,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, (ins (memrix $D, $RA):$src), "bctrl\n\tld 2, $src", IIC_BrB, [(PPCbctrl_load_toc_rm iaddrX4:$src)]>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; } } // Interpretation64Bit @@ -449,7 +449,7 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, []>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in @@ -516,7 +516,7 @@ let hasSideEffects = 1 in { def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), "#EH_SJLJ_SETJMP64", [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; } let hasSideEffects = 1, isBarrier = 1 in { @@ -524,7 +524,7 @@ let hasSideEffects = 1, isBarrier = 1 in { def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), "#EH_SJLJ_LONGJMP64", [(PPCeh_sjlj_longjmp addr:$buf)]>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; } def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RST), (ins i32imm:$SPR), @@ -1948,7 +1948,7 @@ def : Pat<(atomic_load_nonext_64 XForm:$src), (LDX memrr:$src)>; def : Pat<(atomic_store_64 i64:$val, DSForm:$ptr), (STD g8rc:$val, memrix:$ptr)>; def : Pat<(atomic_store_64 i64:$val, XForm:$ptr), (STDX g8rc:$val, memrr:$ptr)>; -let Predicates = [IsISA3_0, In64BitMode] in { +let Predicates = [IsISA3_0, IsPPC64] in { def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)), (i64 (SETB8 (CMPEQB $a, $b)))>; def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)), @@ -1961,7 +1961,7 @@ def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)), (i64 (MADDLD8 $a, $b, $c))>; } -let Predicates = [In64BitMode] in { +let Predicates = [IsPPC64] in { def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)), (i64 (MULHD $a, $b))>; def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)), diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index 97d5e28963234..c616db4a1031c 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -343,7 +343,6 @@ class VXCR_Int_Ty xo, string opc, Intrinsic IntID, ValueType Ty> //===----------------------------------------------------------------------===// // Instruction Definitions. -def HasAltivec : Predicate<"Subtarget->hasAltivec()">; let Predicates = [HasAltivec] in { def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), @@ -1193,8 +1192,6 @@ class VX_VT5_VA5_VB5_XO9_o xo, string opc, list pattern> let PS = 0; } -def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">; -def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">; let Predicates = [HasP8Altivec] in { let isCommutable = 1 in { @@ -1420,7 +1417,6 @@ def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>; } // HasP8Crypto // The following altivec instructions were introduced in Power ISA 3.0 -def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">; let Predicates = [HasP9Altivec] in { // Vector Multiply-Sum diff --git a/llvm/lib/Target/PowerPC/PPCInstrHTM.td b/llvm/lib/Target/PowerPC/PPCInstrHTM.td index 8d0ac512b290d..6b5da44c91c2b 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrHTM.td +++ b/llvm/lib/Target/PowerPC/PPCInstrHTM.td @@ -11,10 +11,6 @@ // //===----------------------------------------------------------------------===// - - -def HasHTM : Predicate<"Subtarget->hasHTM()">; - def HTM_get_imm : SDNodeXFormgetZExtValue(), SDLoc(N)); }]>; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 1c45050cdf9ca..aca7abd5a45a7 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -1282,7 +1282,7 @@ def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, - [(PPCretglue)]>, Requires<[In32BitMode]>; + [(PPCretglue)]>, Requires<[IsPPC32]>; let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { let isPredicable = 1 in def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, @@ -1455,7 +1455,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { let isPredicable = 1 in def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), "bctrl", IIC_BrB, [(PPCbctrl)]>, - Requires<[In32BitMode]>; + Requires<[IsPPC32]>; let isCodeGenOnly = 1 in { def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond), @@ -1541,7 +1541,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in { let isPredicable = 1 in def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, - Requires<[In32BitMode]>; + Requires<[IsPPC32]>; } } @@ -1567,7 +1567,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, def BCTRL_LWZinto_toc: XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, - [(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>; + [(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[IsPPC32]>; } @@ -1576,7 +1576,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, def BCTRL_LWZinto_toc_RM: XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, - [(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>; + [(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[IsPPC32]>; } @@ -1585,7 +1585,7 @@ let isCodeGenOnly = 1, hasSideEffects = 0 in { let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, - []>, Requires<[In32BitMode]>; + []>, Requires<[IsPPC32]>; let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in @@ -1608,7 +1608,7 @@ let hasSideEffects = 1 in { def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), "#EH_SJLJ_SETJMP32", [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, - Requires<[In32BitMode]>; + Requires<[IsPPC32]>; } let hasSideEffects = 1, isBarrier = 1 in { @@ -1616,7 +1616,7 @@ let hasSideEffects = 1, isBarrier = 1 in { def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), "#EH_SJLJ_LONGJMP32", [(PPCeh_sjlj_longjmp addr:$buf)]>, - Requires<[In32BitMode]>; + Requires<[IsPPC32]>; } // This pseudo is never removed from the function, as it serves as @@ -3438,8 +3438,6 @@ def Msk2Imm : ImmLeaf(Imm); }]>; def Msk4Imm : ImmLeaf(Imm); }]>; def Msk8Imm : ImmLeaf(Imm); }]>; -def MMA : Predicate<"Subtarget->hasMMA()">; - // Prefixed instructions may require access to the above defs at a later // time so we include this after the def. include "PPCInstrP10.td" @@ -5144,9 +5142,9 @@ def RotateInsertByte1 { } // Clear the upper half of the register when in 64-bit mode -let Predicates = [In64BitMode] in +let Predicates = [IsPPC64] in def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; -let Predicates = [In32BitMode] in +let Predicates = [IsPPC32] in def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>; // Fast 64-bit reverse bits algorithm: diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td index 8ee9cc952dec6..0a87656b9f8aa 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrP10.td +++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td @@ -51,10 +51,6 @@ // Moreover, the order of operands reflects the order of operands // in the encoding. -//-------------------------- Predicate definitions ---------------------------// -def IsPPC32 : Predicate<"!Subtarget->isPPC64()">; - - //===----------------------------------------------------------------------===// // PowerPC ISA 3.1 specific type constraints. // @@ -634,9 +630,6 @@ multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p opcode, dag OOL, dag IOL, } } -def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; -def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; -def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">; def RCCp { dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC); dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC); diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 4e5165bfcda55..979ba31b0431b 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -116,20 +116,6 @@ def PPCSToV : SDNode<"PPCISD::SCALAR_TO_VECTOR_PERMUTED", SDTypeProfile<1, 1, []>, []>; def PPCxxperm : SDNode<"PPCISD::XXPERM", SDT_PPCxxperm, []>; -//-------------------------- Predicate definitions ---------------------------// -def HasVSX : Predicate<"Subtarget->hasVSX()">; -def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">; -def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">; -def IsPPC64 : Predicate<"Subtarget->isPPC64()">; -def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">; -def NoP8Vector : Predicate<"!Subtarget->hasP8Vector()">; -def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">; -def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">; -def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">; -def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">; -def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">; -def NoP10Vector: Predicate<"!Subtarget->hasP10Vector()">; -def HasP10Vector: Predicate<"Subtarget->hasP10Vector()">; def PPCldsplatAlign16 : PatFrag<(ops node:$ptr), (PPCldsplat node:$ptr), [{ return cast(N)->getAlign() >= Align(16) && @@ -1293,13 +1279,13 @@ let Predicates = [HasVSX, HasP8Vector] in { def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$RA), (ins vsfrc:$XT), "mfvsrd $RA, $XT", IIC_VecGeneral, [(set i64:$RA, (PPCmfvsr f64:$XT))]>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; // FIXME: Setting the hasSideEffects flag here to match current behaviour. let isCodeGenOnly = 1, hasSideEffects = 1 in def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$RA), (ins vsrc:$XT), "mfvsrd $RA, $XT", IIC_VecGeneral, []>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$RA), (ins vsfrc:$XT), "mfvsrwz $RA, $XT", IIC_VecGeneral, [(set i32:$RA, (PPCmfvsr f64:$XT))]>, ZExt32To64; @@ -1311,13 +1297,13 @@ let Predicates = [HasVSX, HasP8Vector] in { def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$RA), "mtvsrd $XT, $RA", IIC_VecGeneral, [(set f64:$XT, (PPCmtvsra i64:$RA))]>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; // FIXME: Setting the hasSideEffects flag here to match current behaviour. let isCodeGenOnly = 1, hasSideEffects = 1 in def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$RA), "mtvsrd $XT, $RA", IIC_VecGeneral, []>, - Requires<[In64BitMode]>; + Requires<[IsPPC64]>; def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$RA), "mtvsrwa $XT, $RA", IIC_VecGeneral, [(set f64:$XT, (PPCmtvsra i32:$RA))]>; @@ -1344,11 +1330,11 @@ def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$RA), def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$RA, g8rc:$RB), "mtvsrdd $XT, $RA, $RB", IIC_VecGeneral, - []>, Requires<[In64BitMode]>; + []>, Requires<[IsPPC64]>; def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$RA), (ins vsrc:$XT), "mfvsrld $RA, $XT", IIC_VecGeneral, - []>, Requires<[In64BitMode]>; + []>, Requires<[IsPPC64]>; } // HasVSX, IsISA3_0, HasDirectMove