From 2d95d27a3777cf913dda0876e1eefd8f1fd2bbec Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Thu, 25 Sep 2025 17:23:15 +0800 Subject: [PATCH] [RISCV][GISel] Support ret fp16 vector for zvfhmin --- llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp | 2 +- llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret.ll | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp index 34026ed5d47a4..2f48c7aaae1e7 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp @@ -334,7 +334,7 @@ static bool isLegalElementTypeForRVV(Type *EltTy, if (EltTy->isIntegerTy(64)) return Subtarget.hasVInstructionsI64(); if (EltTy->isHalfTy()) - return Subtarget.hasVInstructionsF16(); + return Subtarget.hasVInstructionsF16Minimal(); if (EltTy->isBFloatTy()) return Subtarget.hasVInstructionsBF16Minimal(); if (EltTy->isFloatTy()) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret.ll index 4b1359e85bc59..73b0d3a173b72 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfbfmin,+zvfh -global-isel -stop-after=irtranslator \ +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfbfmin,+zvfhmin -global-isel -stop-after=irtranslator \ ; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s -; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfbfmin,+zvfh -global-isel -stop-after=irtranslator \ +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfbfmin,+zvfhmin -global-isel -stop-after=irtranslator \ ; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s ; ==========================================================================