From b030027eecc2a73602814e3f84bdfd7206a59081 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Thu, 25 Sep 2025 19:44:38 +0000 Subject: [PATCH] [NFC][PowerPC] Fix err in instruction class name for stxvp --- llvm/lib/Target/PowerPC/PPCInstrFuture.td | 8 ++++---- llvm/lib/Target/PowerPC/PPCInstrP10.td | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index 08d633f962d93..c3ab9651ff695 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -201,10 +201,10 @@ let Predicates = [HasVSX, IsISAFuture] in { def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB), "lxvrll $XT, $addr, $RB", IIC_LdStLoad, []>; - def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp), + def LXVPRL : XForm_XTp5_RAB5<31, 589, (outs vsrprc:$XTp), (ins (memr $RA):$addr, g8rc:$RB), "lxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>; - def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp), + def LXVPRLL : XForm_XTp5_RAB5<31, 621, (outs vsrprc:$XTp), (ins (memr $RA):$addr, g8rc:$RB), "lxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>; } @@ -216,11 +216,11 @@ let Predicates = [HasVSX, IsISAFuture] in { def STXVRLL : XX1Form_memOp<31, 685, (outs), (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB), "stxvrll $XT, $addr, $RB", IIC_LdStLoad, []>; - def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs), + def STXVPRL : XForm_XTp5_RAB5<31, 717, (outs), (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB), "stxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>; def STXVPRLL - : XForm_XTp5_XAB5<31, 749, (outs), + : XForm_XTp5_RAB5<31, 749, (outs), (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB), "stxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>; } diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td index 8ee9cc952dec6..ba70398daf2c0 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrP10.td +++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td @@ -870,7 +870,7 @@ class DQForm_XTp5_RA17_MEM opcode, bits<4> xo, dag OOL, dag IOL, let Inst{28...31} = xo; } -class XForm_XTp5_XAB5 opcode, bits<10> xo, dag OOL, dag IOL, +class XForm_XTp5_RAB5 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I, XFormMemOp { bits<5> XTp; @@ -1159,7 +1159,7 @@ let Predicates = [PairedVectorMemops] in { def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp), (ins (memrix16 $DQ, $RA):$addr), "lxvp $XTp, $addr", IIC_LdStLFD, []>; - def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins (memrr $RA, $RB):$addr), + def LXVPX : XForm_XTp5_RAB5<31, 333, (outs vsrprc:$XTp), (ins (memrr $RA, $RB):$addr), "lxvpx $XTp, $addr", IIC_LdStLFD, []>; } @@ -1168,7 +1168,7 @@ let Predicates = [PairedVectorMemops] in { def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp, (memrix16 $DQ, $RA):$addr), "stxvp $XTp, $addr", IIC_LdStLFD, []>; - def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, (memrr $RA, $RB):$addr), + def STXVPX : XForm_XTp5_RAB5<31, 461, (outs), (ins vsrprc:$XTp, (memrr $RA, $RB):$addr), "stxvpx $XTp, $addr", IIC_LdStLFD, []>; }