From b8b9219f9ab284e59c90b086af295c706ecb7ba0 Mon Sep 17 00:00:00 2001
From: JP Lehr <JanPatrick.Lehr@amd.com>
Date: Thu, 25 Sep 2025 15:25:08 -0500
Subject: [PATCH] [AMDGPU] Enable overwrite ALU bit in sched.barrier mask

The sched.barrier takes a bit mask that determines which instruction
categories are allowed to cross the inserted sched.barrier during the
igrouplp scheduling pass.

Currently, a set ALU bit results in allowing all ALU instructions to
move across the barrier, independent of whether more specific bits
have been specified.
The documentation is silent about the semantics in that case.

This PR changes the current handling: When a mask contains both a set
ALU bit and a set more-specific bit, the more specific bit is respected
and the ALU bit does *not imply* all other bits.

Current:
0x00000005 -- 0101 set ALU and SALU bit. Currently the ALU bit implies
                   SALU and VALU and MFMA to be set.

New:
0x00000005 -- 0101 set ALU and SALU bit. SALU bit set, therefore ALU bit
                   is ignored and only SALU bit is considered.
---
 llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index dbe74b1b08f8c..edb43627dd51e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -2615,8 +2615,14 @@ IGroupLPDAGMutation::invertSchedBarrierMask(SchedGroupMask Mask) const {
   // allowed past the SCHED_BARRIER.
   SchedGroupMask InvertedMask = ~Mask;
 
+  // When given, specific bits overrule the more general ALU type.
+  bool HasConcreteClassSpecified =
+      (Mask & (SchedGroupMask::SALU | SchedGroupMask::VALU |
+               SchedGroupMask::MFMA)) != SchedGroupMask::NONE;
+
   // ALU implies VALU, SALU, MFMA, TRANS.
-  if ((InvertedMask & SchedGroupMask::ALU) == SchedGroupMask::NONE)
+  if (!HasConcreteClassSpecified &&
+      (InvertedMask & SchedGroupMask::ALU) == SchedGroupMask::NONE)
     InvertedMask &= ~SchedGroupMask::VALU & ~SchedGroupMask::SALU &
                     ~SchedGroupMask::MFMA & ~SchedGroupMask::TRANS;
   // VALU, SALU, MFMA, TRANS implies ALU.