From a34887414ee815911dc53c9b9e041af896a3ceeb Mon Sep 17 00:00:00 2001 From: Liao Chunyu Date: Sun, 28 Sep 2025 03:04:33 -0400 Subject: [PATCH 1/3] [Docs][RISCV]Remove experimental from Smctr, Ssctr,Sdext and Sdtrig --- llvm/docs/RISCVUsage.rst | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 7b1a6ce834919..d3c62c1b0d821 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -120,6 +120,8 @@ on support follow. ``H`` Assembly Support ``M`` Supported ``Q`` Assembly Support + ``Sdext`` Assembly Support + ``Sdtrig`` Assembly Support ``Sha`` Supported ``Shcounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Shgatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) @@ -132,6 +134,7 @@ on support follow. ``Smcdeleg`` Supported ``Smcntrpmf`` Supported ``Smcsrind`` Supported + ``Smctr`` Assembly Support ``Smdbltrp`` Supported ``Smepmp`` Supported ``Smmpm`` Supported @@ -144,6 +147,7 @@ on support follow. ``Sscofpmf`` Assembly Support ``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Sscsrind`` Supported + ``Ssctr`` Assembly Support ``Ssdbltrp`` Supported ``Ssnpm`` Supported ``Sspm`` Supported @@ -337,12 +341,6 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zvbc32e``, ``experimental-zvkgs`` LLVM implements the `0.7 release specification `__. -``experimental-sdext``, ``experimental-sdtrig`` - LLVM implements the `1.0-rc4 specification `__. - -``experimental-smctr``, ``experimental-ssctr`` - LLVM implements the `1.0-rc3 specification `__. - ``experimental-svukte`` LLVM implements the `0.3 draft specification `__. From 351f73e17c039235d7c676516561c05f83d2e184 Mon Sep 17 00:00:00 2001 From: Liao Chunyu Date: Mon, 29 Sep 2025 22:30:53 -0400 Subject: [PATCH 2/3] add spec docs --- llvm/docs/RISCVUsage.rst | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index d3c62c1b0d821..41440c31242d7 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -120,8 +120,8 @@ on support follow. ``H`` Assembly Support ``M`` Supported ``Q`` Assembly Support - ``Sdext`` Assembly Support - ``Sdtrig`` Assembly Support + ``Sdext`` Assembly Support (`See note <#riscv-extensions-specifications-note>`__) + ``Sdtrig`` Assembly Support (`See note <#riscv-extensions-specifications-note>`__) ``Sha`` Supported ``Shcounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Shgatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) @@ -134,7 +134,7 @@ on support follow. ``Smcdeleg`` Supported ``Smcntrpmf`` Supported ``Smcsrind`` Supported - ``Smctr`` Assembly Support + ``Smctr`` Assembly Support (`See note <#riscv-extensions-specifications-note>`__) ``Smdbltrp`` Supported ``Smepmp`` Supported ``Smmpm`` Supported @@ -147,7 +147,7 @@ on support follow. ``Sscofpmf`` Assembly Support ``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Sscsrind`` Supported - ``Ssctr`` Assembly Support + ``Ssctr`` Assembly Support (`See note <#riscv-extensions-specifications-note>`__) ``Ssdbltrp`` Supported ``Ssnpm`` Supported ``Sspm`` Supported @@ -310,6 +310,11 @@ Supported ``Za128rs``, ``Za64rs``, ``Zama16b``, ``Zic64b``, ``Ziccamoa``, ``Ziccamoc``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare`` These extensions are defined as part of the `RISC-V Profiles specification `__. They do not introduce any new features themselves, but instead describe existing hardware features. +.. _riscv-extensions-specifications-note: + +``Sdext``, ``Sdtrig`` `The RISC-V Debug Specification `__. +``Smctr``, ``Ssctr`` `RISC-V Control Transfer Records `__. + .. _riscv-zacas-note: ``Zacas`` From 796373e3594620f01d828dbe90ddfcf675b1883e Mon Sep 17 00:00:00 2001 From: Liao Chunyu Date: Tue, 30 Sep 2025 01:15:32 -0400 Subject: [PATCH 3/3] delete Smctr Ssctr spec --- llvm/docs/RISCVUsage.rst | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 41440c31242d7..f9e2e4a5f02c3 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -120,8 +120,8 @@ on support follow. ``H`` Assembly Support ``M`` Supported ``Q`` Assembly Support - ``Sdext`` Assembly Support (`See note <#riscv-extensions-specifications-note>`__) - ``Sdtrig`` Assembly Support (`See note <#riscv-extensions-specifications-note>`__) + ``Sdext`` Assembly Support (`See note <#riscv-debug-specification-note>`__) + ``Sdtrig`` Assembly Support (`See note <#riscv-debug-specification-note>`__) ``Sha`` Supported ``Shcounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Shgatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) @@ -134,7 +134,7 @@ on support follow. ``Smcdeleg`` Supported ``Smcntrpmf`` Supported ``Smcsrind`` Supported - ``Smctr`` Assembly Support (`See note <#riscv-extensions-specifications-note>`__) + ``Smctr`` Assembly Support ``Smdbltrp`` Supported ``Smepmp`` Supported ``Smmpm`` Supported @@ -147,7 +147,7 @@ on support follow. ``Sscofpmf`` Assembly Support ``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Sscsrind`` Supported - ``Ssctr`` Assembly Support (`See note <#riscv-extensions-specifications-note>`__) + ``Ssctr`` Assembly Support ``Ssdbltrp`` Supported ``Ssnpm`` Supported ``Sspm`` Supported @@ -310,10 +310,9 @@ Supported ``Za128rs``, ``Za64rs``, ``Zama16b``, ``Zic64b``, ``Ziccamoa``, ``Ziccamoc``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare`` These extensions are defined as part of the `RISC-V Profiles specification `__. They do not introduce any new features themselves, but instead describe existing hardware features. -.. _riscv-extensions-specifications-note: +.. _riscv-debug-specification-note: ``Sdext``, ``Sdtrig`` `The RISC-V Debug Specification `__. -``Smctr``, ``Ssctr`` `RISC-V Control Transfer Records `__. .. _riscv-zacas-note: