From ecd7d12310757203abe9d3b83d86ffa31bdc1126 Mon Sep 17 00:00:00 2001 From: Aaditya Date: Fri, 26 Sep 2025 17:57:37 +0530 Subject: [PATCH] [AMDGPU] Add wave reduce intrinsics for float types - 1 Supported Ops: `fmin`, `fmax` --- llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 2 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 49 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 5 +- .../CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll | 881 ++++++++++++++++++ .../CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll | 881 ++++++++++++++++++ 5 files changed, 1812 insertions(+), 6 deletions(-) diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index 030d01d7a5f3f..2f6e2dc964e81 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -2470,7 +2470,7 @@ def int_amdgcn_s_quadmask : def int_amdgcn_s_wqm : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem, IntrConvergent]>; -class AMDGPUWaveReduce : Intrinsic< +class AMDGPUWaveReduce : Intrinsic< [data_ty], [ LLVMMatchType<0>, // llvm value to reduce (SGPR/VGPR) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 2a977247bc2cb..4d3c3de879bb6 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5338,6 +5338,15 @@ static uint32_t getIdentityValueFor32BitWaveReduction(unsigned Opc) { return std::numeric_limits::min(); case AMDGPU::S_AND_B32: return std::numeric_limits::max(); + case AMDGPU::V_MIN_F32_e64: + case AMDGPU::V_MAX_F32_e64: { + // Modeled similar to llvm.maxnum/minnum intrinsics + float QNaN = std::numeric_limits::quiet_NaN(); + uint32_t bits; + assert(sizeof(bits) == sizeof(QNaN) && "Huh?"); + std::memcpy(&bits, &QNaN, sizeof(bits)); + return bits; + } default: llvm_unreachable( "Unexpected opcode in getIdentityValueFor32BitWaveReduction"); @@ -5372,7 +5381,12 @@ static bool is32bitWaveReduceOperation(unsigned Opc) { Opc == AMDGPU::S_MAX_U32 || Opc == AMDGPU::S_MAX_I32 || Opc == AMDGPU::S_ADD_I32 || Opc == AMDGPU::S_SUB_I32 || Opc == AMDGPU::S_AND_B32 || Opc == AMDGPU::S_OR_B32 || - Opc == AMDGPU::S_XOR_B32; + Opc == AMDGPU::S_XOR_B32 || Opc == AMDGPU::V_MIN_F32_e64 || + Opc == AMDGPU::V_MAX_F32_e64; +} + +static bool isFloatingPointWaveReduceOperation(unsigned Opc) { + return Opc == AMDGPU::V_MIN_F32_e64 || Opc == AMDGPU::V_MAX_F32_e64; } static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI, @@ -5393,8 +5407,10 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI, switch (Opc) { case AMDGPU::S_MIN_U32: case AMDGPU::S_MIN_I32: + case AMDGPU::V_MIN_F32_e64: case AMDGPU::S_MAX_U32: case AMDGPU::S_MAX_I32: + case AMDGPU::V_MAX_F32_e64: case AMDGPU::S_AND_B32: case AMDGPU::S_OR_B32: { // Idempotent operations. @@ -5590,6 +5606,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI, MachineBasicBlock::iterator I = BB.end(); Register SrcReg = MI.getOperand(1).getReg(); bool is32BitOpc = is32bitWaveReduceOperation(Opc); + bool isFPOp = isFloatingPointWaveReduceOperation(Opc); // Create Control flow for loop // Split MI's Machine Basic block into For loop @@ -5649,9 +5666,29 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI, LaneValueReg) .addReg(SrcReg) .addReg(FF1Reg); - NewAccumulator = BuildMI(*ComputeLoop, I, DL, TII->get(Opc), DstReg) - .addReg(Accumulator->getOperand(0).getReg()) - .addReg(LaneValueReg); + if (isFPOp) { + Register LaneValVreg = + MRI.createVirtualRegister(MRI.getRegClass(SrcReg)); + Register DstVreg = MRI.createVirtualRegister(MRI.getRegClass(SrcReg)); + // Get the Lane Value in VGPR to avoid the Constant Bus Restriction + BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), + LaneValVreg) + .addReg(LaneValueReg); + BuildMI(*ComputeLoop, I, DL, TII->get(Opc), DstVreg) + .addImm(0) // src0 modifier + .addReg(Accumulator->getOperand(0).getReg()) + .addImm(0) // src1 modifier + .addReg(LaneValVreg) + .addImm(0) // clamp + .addImm(0); // omod + NewAccumulator = BuildMI(*ComputeLoop, I, DL, + TII->get(AMDGPU::V_READFIRSTLANE_B32), DstReg) + .addReg(DstVreg); + } else { + NewAccumulator = BuildMI(*ComputeLoop, I, DL, TII->get(Opc), DstReg) + .addReg(Accumulator->getOperand(0).getReg()) + .addReg(LaneValueReg); + } } else { Register LaneValueLoReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); @@ -5780,6 +5817,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_MIN_I32); case AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I64: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_CMP_LT_I64_e64); + case AMDGPU::WAVE_REDUCE_MIN_PSEUDO_F32: + return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_MIN_F32_e64); case AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U32: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_MAX_U32); case AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U64: @@ -5788,6 +5827,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_MAX_I32); case AMDGPU::WAVE_REDUCE_MAX_PSEUDO_I64: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_CMP_GT_I64_e64); + case AMDGPU::WAVE_REDUCE_MAX_PSEUDO_F32: + return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_MAX_F32_e64); case AMDGPU::WAVE_REDUCE_ADD_PSEUDO_I32: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_ADD_I32); case AMDGPU::WAVE_REDUCE_ADD_PSEUDO_U64: diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 1f7951258c219..b0ecf2b56aaef 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -349,7 +349,7 @@ class WaveReduceOp, WaveReduceOp<"or", "B64", i64, SGPR_64, VSrc_b64>, WaveReduceOp<"xor", "B64", i64, SGPR_64, VSrc_b64>, + + WaveReduceOp<"min", "F32", f32, SGPR_32, VSrc_b32>, + WaveReduceOp<"max", "F32", f32, SGPR_32, VSrc_b32>, ]; foreach Op = Operations in { diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll index 6f299ab8bb9cf..919360a1bbb7f 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll @@ -1534,6 +1534,887 @@ endif: store i64 %combine, ptr addrspace(1) %out ret void } + +define amdgpu_kernel void @uniform_value_float(ptr addrspace(1) %out, float %in) { +; GFX8DAGISEL-LABEL: uniform_value_float: +; GFX8DAGISEL: ; %bb.0: ; %entry +; GFX8DAGISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX8DAGISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX8DAGISEL-NEXT: flat_store_dword v[0:1], v2 +; GFX8DAGISEL-NEXT: s_endpgm +; +; GFX8GISEL-LABEL: uniform_value_float: +; GFX8GISEL: ; %bb.0: ; %entry +; GFX8GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2 +; GFX8GISEL-NEXT: s_endpgm +; +; GFX9DAGISEL-LABEL: uniform_value_float: +; GFX9DAGISEL: ; %bb.0: ; %entry +; GFX9DAGISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; GFX9DAGISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9DAGISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v1, s2 +; GFX9DAGISEL-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9DAGISEL-NEXT: s_endpgm +; +; GFX9GISEL-LABEL: uniform_value_float: +; GFX9GISEL: ; %bb.0: ; %entry +; GFX9GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; GFX9GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX9GISEL-NEXT: global_store_dword v1, v0, s[0:1] +; GFX9GISEL-NEXT: s_endpgm +; +; GFX10DAGISEL-LABEL: uniform_value_float: +; GFX10DAGISEL: ; %bb.0: ; %entry +; GFX10DAGISEL-NEXT: s_clause 0x1 +; GFX10DAGISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; GFX10DAGISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10DAGISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX10DAGISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10DAGISEL-NEXT: v_mov_b32_e32 v1, s2 +; GFX10DAGISEL-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10DAGISEL-NEXT: s_endpgm +; +; GFX10GISEL-LABEL: uniform_value_float: +; GFX10GISEL: ; %bb.0: ; %entry +; GFX10GISEL-NEXT: s_clause 0x1 +; GFX10GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; GFX10GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX10GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX10GISEL-NEXT: global_store_dword v1, v0, s[0:1] +; GFX10GISEL-NEXT: s_endpgm +; +; GFX1164DAGISEL-LABEL: uniform_value_float: +; GFX1164DAGISEL: ; %bb.0: ; %entry +; GFX1164DAGISEL-NEXT: s_clause 0x1 +; GFX1164DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v1, s2 +; GFX1164DAGISEL-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX1164DAGISEL-NEXT: s_endpgm +; +; GFX1164GISEL-LABEL: uniform_value_float: +; GFX1164GISEL: ; %bb.0: ; %entry +; GFX1164GISEL-NEXT: s_clause 0x1 +; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX1164GISEL-NEXT: s_endpgm +; +; GFX1132DAGISEL-LABEL: uniform_value_float: +; GFX1132DAGISEL: ; %bb.0: ; %entry +; GFX1132DAGISEL-NEXT: s_clause 0x1 +; GFX1132DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX1132DAGISEL-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX1132DAGISEL-NEXT: s_endpgm +; +; GFX1132GISEL-LABEL: uniform_value_float: +; GFX1132GISEL: ; %bb.0: ; %entry +; GFX1132GISEL-NEXT: s_clause 0x1 +; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2 +; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX1132GISEL-NEXT: s_endpgm +entry: + %result = call float @llvm.amdgcn.wave.reduce.max.float(float %in, i32 1) + store float %result, ptr addrspace(1) %out + ret void +} + +define void @divergent_value_float(ptr addrspace(1) %out, float %in) { +; GFX8DAGISEL-LABEL: divergent_value_float: +; GFX8DAGISEL: ; %bb.0: ; %entry +; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8DAGISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX8DAGISEL-NEXT: s_mov_b32 s6, 0x7fc00000 +; GFX8DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s8 +; GFX8DAGISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX8DAGISEL-NEXT: v_max_f32_e32 v3, s6, v3 +; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s6, v3 +; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX8DAGISEL-NEXT: ; %bb.2: +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX8DAGISEL-NEXT: flat_store_dword v[0:1], v2 +; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) +; GFX8DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX8GISEL-LABEL: divergent_value_float: +; GFX8GISEL: ; %bb.0: ; %entry +; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX8GISEL-NEXT: s_brev_b32 s6, 1 +; GFX8GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX8GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX8GISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX8GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX8GISEL-NEXT: s_max_i32 s6, s6, s8 +; GFX8GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX8GISEL-NEXT: ; %bb.2: +; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2 +; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX8GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9DAGISEL-LABEL: divergent_value_float: +; GFX9DAGISEL: ; %bb.0: ; %entry +; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9DAGISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9DAGISEL-NEXT: s_mov_b32 s6, 0x7fc00000 +; GFX9DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v3, s8 +; GFX9DAGISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9DAGISEL-NEXT: v_max_f32_e32 v3, s6, v3 +; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s6, v3 +; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX9DAGISEL-NEXT: ; %bb.2: +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX9DAGISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GISEL-LABEL: divergent_value_float: +; GFX9GISEL: ; %bb.0: ; %entry +; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9GISEL-NEXT: s_brev_b32 s6, 1 +; GFX9GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX9GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9GISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX9GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9GISEL-NEXT: s_max_i32 s6, s6, s8 +; GFX9GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX9GISEL-NEXT: ; %bb.2: +; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX9GISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1064DAGISEL-LABEL: divergent_value_float: +; GFX1064DAGISEL: ; %bb.0: ; %entry +; GFX1064DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1064DAGISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX1064DAGISEL-NEXT: s_mov_b32 s6, 0x7fc00000 +; GFX1064DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX1064DAGISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX1064DAGISEL-NEXT: v_max_f32_e64 v3, s6, s8 +; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s6, v3 +; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1064DAGISEL-NEXT: ; %bb.2: +; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX1064DAGISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX1064DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1064GISEL-LABEL: divergent_value_float: +; GFX1064GISEL: ; %bb.0: ; %entry +; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX1064GISEL-NEXT: s_brev_b32 s6, 1 +; GFX1064GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1064GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX1064GISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX1064GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX1064GISEL-NEXT: s_max_i32 s6, s6, s8 +; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1064GISEL-NEXT: ; %bb.2: +; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX1064GISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX1064GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1032DAGISEL-LABEL: divergent_value_float: +; GFX1032DAGISEL: ; %bb.0: ; %entry +; GFX1032DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1032DAGISEL-NEXT: s_mov_b32 s4, exec_lo +; GFX1032DAGISEL-NEXT: s_mov_b32 s5, 0x7fc00000 +; GFX1032DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s6, s4 +; GFX1032DAGISEL-NEXT: v_readlane_b32 s7, v2, s6 +; GFX1032DAGISEL-NEXT: s_bitset0_b32 s4, s6 +; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX1032DAGISEL-NEXT: v_max_f32_e64 v3, s5, s7 +; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v3 +; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1032DAGISEL-NEXT: ; %bb.2: +; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v2, s5 +; GFX1032DAGISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX1032DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1032GISEL-LABEL: divergent_value_float: +; GFX1032GISEL: ; %bb.0: ; %entry +; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1032GISEL-NEXT: s_mov_b32 s5, exec_lo +; GFX1032GISEL-NEXT: s_brev_b32 s4, 1 +; GFX1032GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1032GISEL-NEXT: s_ff1_i32_b32 s6, s5 +; GFX1032GISEL-NEXT: v_readlane_b32 s7, v2, s6 +; GFX1032GISEL-NEXT: s_bitset0_b32 s5, s6 +; GFX1032GISEL-NEXT: s_max_i32 s4, s4, s7 +; GFX1032GISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1032GISEL-NEXT: ; %bb.2: +; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX1032GISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-LABEL: divergent_value_float: +; GFX1164DAGISEL: ; %bb.0: ; %entry +; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0x7fc00000 +; GFX1164DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-NEXT: v_max_f32_e64 v3, s2, s4 +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s2, v3 +; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1164DAGISEL-NEXT: ; %bb.2: +; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-NEXT: global_store_b32 v[0:1], v2, off +; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-LABEL: divergent_value_float: +; GFX1164GISEL: ; %bb.0: ; %entry +; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-NEXT: s_brev_b32 s2, 1 +; GFX1164GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164GISEL-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164GISEL-NEXT: s_max_i32 s2, s2, s4 +; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1164GISEL-NEXT: ; %bb.2: +; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-LABEL: divergent_value_float: +; GFX1132DAGISEL: ; %bb.0: ; %entry +; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-NEXT: s_mov_b32 s0, exec_lo +; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7fc00000 +; GFX1132DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s0 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-NEXT: s_bitset0_b32 s0, s2 +; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s0, 0 +; GFX1132DAGISEL-NEXT: v_max_f32_e64 v3, s1, s3 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v3 +; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1132DAGISEL-NEXT: ; %bb.2: +; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s1 +; GFX1132DAGISEL-NEXT: global_store_b32 v[0:1], v2, off +; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-LABEL: divergent_value_float: +; GFX1132GISEL: ; %bb.0: ; %entry +; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX1132GISEL-NEXT: s_brev_b32 s0, 1 +; GFX1132GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX1132GISEL-NEXT: s_max_i32 s0, s0, s3 +; GFX1132GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1132GISEL-NEXT: ; %bb.2: +; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + %result = call float @llvm.amdgcn.wave.reduce.max.float(float %in, i32 1) + store float %result, ptr addrspace(1) %out + ret void +} + +define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) { +; GFX8DAGISEL-LABEL: divergent_cfg_float: +; GFX8DAGISEL: ; %bb.0: ; %entry +; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX8DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v4 +; GFX8DAGISEL-NEXT: ; implicit-def: $vgpr4 +; GFX8DAGISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8DAGISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX8DAGISEL-NEXT: s_cbranch_execz .LBB8_4 +; GFX8DAGISEL-NEXT: ; %bb.1: ; %else +; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX8DAGISEL-NEXT: s_mov_b32 s8, 0x7fc00000 +; GFX8DAGISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v2, s9 +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s10 +; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX8DAGISEL-NEXT: v_max_f32_e32 v3, s8, v3 +; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s8, v3 +; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX8DAGISEL-NEXT: ; %bb.3: +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s8 +; GFX8DAGISEL-NEXT: ; implicit-def: $vgpr3 +; GFX8DAGISEL-NEXT: .LBB8_4: ; %Flow +; GFX8DAGISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX8DAGISEL-NEXT: s_cbranch_execz .LBB8_8 +; GFX8DAGISEL-NEXT: ; %bb.5: ; %if +; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX8DAGISEL-NEXT: s_mov_b32 s8, 0x7fc00000 +; GFX8DAGISEL-NEXT: .LBB8_6: ; =>This Inner Loop Header: Depth=1 +; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v3, s9 +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s10 +; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX8DAGISEL-NEXT: v_max_f32_e32 v2, s8, v2 +; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s8, v2 +; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB8_6 +; GFX8DAGISEL-NEXT: ; %bb.7: +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s8 +; GFX8DAGISEL-NEXT: .LBB8_8: ; %endif +; GFX8DAGISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8DAGISEL-NEXT: flat_store_dword v[0:1], v4 +; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) +; GFX8DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX8GISEL-LABEL: divergent_cfg_float: +; GFX8GISEL: ; %bb.0: ; %entry +; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4 +; GFX8GISEL-NEXT: ; implicit-def: $sgpr8 +; GFX8GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX8GISEL-NEXT: s_cbranch_execz .LBB8_3 +; GFX8GISEL-NEXT: ; %bb.1: ; %else +; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX8GISEL-NEXT: s_brev_b32 s8, 1 +; GFX8GISEL-NEXT: ; implicit-def: $vgpr3 +; GFX8GISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX8GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX8GISEL-NEXT: v_readlane_b32 s10, v2, s9 +; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX8GISEL-NEXT: s_max_i32 s8, s8, s10 +; GFX8GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX8GISEL-NEXT: .LBB8_3: ; %Flow +; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX8GISEL-NEXT: s_cbranch_execz .LBB8_6 +; GFX8GISEL-NEXT: ; %bb.4: ; %if +; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX8GISEL-NEXT: s_brev_b32 s8, 1 +; GFX8GISEL-NEXT: .LBB8_5: ; =>This Inner Loop Header: Depth=1 +; GFX8GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX8GISEL-NEXT: v_readlane_b32 s10, v3, s9 +; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX8GISEL-NEXT: s_max_i32 s8, s8, s10 +; GFX8GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB8_5 +; GFX8GISEL-NEXT: .LBB8_6: ; %endif +; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s8 +; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2 +; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX8GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9DAGISEL-LABEL: divergent_cfg_float: +; GFX9DAGISEL: ; %bb.0: ; %entry +; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX9DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v4 +; GFX9DAGISEL-NEXT: ; implicit-def: $vgpr4 +; GFX9DAGISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9DAGISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9DAGISEL-NEXT: s_cbranch_execz .LBB8_4 +; GFX9DAGISEL-NEXT: ; %bb.1: ; %else +; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9DAGISEL-NEXT: s_mov_b32 s8, 0x7fc00000 +; GFX9DAGISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v2, s9 +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v3, s10 +; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9DAGISEL-NEXT: v_max_f32_e32 v3, s8, v3 +; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s8, v3 +; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX9DAGISEL-NEXT: ; %bb.3: +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s8 +; GFX9DAGISEL-NEXT: ; implicit-def: $vgpr3 +; GFX9DAGISEL-NEXT: .LBB8_4: ; %Flow +; GFX9DAGISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9DAGISEL-NEXT: s_cbranch_execz .LBB8_8 +; GFX9DAGISEL-NEXT: ; %bb.5: ; %if +; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9DAGISEL-NEXT: s_mov_b32 s8, 0x7fc00000 +; GFX9DAGISEL-NEXT: .LBB8_6: ; =>This Inner Loop Header: Depth=1 +; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v3, s9 +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s10 +; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9DAGISEL-NEXT: v_max_f32_e32 v2, s8, v2 +; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s8, v2 +; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB8_6 +; GFX9DAGISEL-NEXT: ; %bb.7: +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s8 +; GFX9DAGISEL-NEXT: .LBB8_8: ; %endif +; GFX9DAGISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9DAGISEL-NEXT: global_store_dword v[0:1], v4, off +; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GISEL-LABEL: divergent_cfg_float: +; GFX9GISEL: ; %bb.0: ; %entry +; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4 +; GFX9GISEL-NEXT: ; implicit-def: $sgpr8 +; GFX9GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9GISEL-NEXT: s_cbranch_execz .LBB8_3 +; GFX9GISEL-NEXT: ; %bb.1: ; %else +; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9GISEL-NEXT: s_brev_b32 s8, 1 +; GFX9GISEL-NEXT: ; implicit-def: $vgpr3 +; GFX9GISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX9GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9GISEL-NEXT: v_readlane_b32 s10, v2, s9 +; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9GISEL-NEXT: s_max_i32 s8, s8, s10 +; GFX9GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX9GISEL-NEXT: .LBB8_3: ; %Flow +; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9GISEL-NEXT: s_cbranch_execz .LBB8_6 +; GFX9GISEL-NEXT: ; %bb.4: ; %if +; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9GISEL-NEXT: s_brev_b32 s8, 1 +; GFX9GISEL-NEXT: .LBB8_5: ; =>This Inner Loop Header: Depth=1 +; GFX9GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9GISEL-NEXT: v_readlane_b32 s10, v3, s9 +; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9GISEL-NEXT: s_max_i32 s8, s8, s10 +; GFX9GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB8_5 +; GFX9GISEL-NEXT: .LBB8_6: ; %endif +; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s8 +; GFX9GISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1064DAGISEL-LABEL: divergent_cfg_float: +; GFX1064DAGISEL: ; %bb.0: ; %entry +; GFX1064DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1064DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1064DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v4 +; GFX1064DAGISEL-NEXT: ; implicit-def: $vgpr4 +; GFX1064DAGISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064DAGISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX1064DAGISEL-NEXT: s_cbranch_execz .LBB8_4 +; GFX1064DAGISEL-NEXT: ; %bb.1: ; %else +; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX1064DAGISEL-NEXT: s_mov_b32 s8, 0x7fc00000 +; GFX1064DAGISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX1064DAGISEL-NEXT: v_readlane_b32 s10, v2, s9 +; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX1064DAGISEL-NEXT: v_max_f32_e64 v3, s8, s10 +; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s8, v3 +; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1064DAGISEL-NEXT: ; %bb.3: +; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v4, s8 +; GFX1064DAGISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1064DAGISEL-NEXT: .LBB8_4: ; %Flow +; GFX1064DAGISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX1064DAGISEL-NEXT: s_cbranch_execz .LBB8_8 +; GFX1064DAGISEL-NEXT: ; %bb.5: ; %if +; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX1064DAGISEL-NEXT: s_mov_b32 s8, 0x7fc00000 +; GFX1064DAGISEL-NEXT: .LBB8_6: ; =>This Inner Loop Header: Depth=1 +; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX1064DAGISEL-NEXT: v_readlane_b32 s10, v3, s9 +; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX1064DAGISEL-NEXT: v_max_f32_e64 v2, s8, s10 +; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s8, v2 +; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB8_6 +; GFX1064DAGISEL-NEXT: ; %bb.7: +; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v4, s8 +; GFX1064DAGISEL-NEXT: .LBB8_8: ; %endif +; GFX1064DAGISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064DAGISEL-NEXT: global_store_dword v[0:1], v4, off +; GFX1064DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1064GISEL-LABEL: divergent_cfg_float: +; GFX1064GISEL: ; %bb.0: ; %entry +; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1064GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1064GISEL-NEXT: ; implicit-def: $sgpr8 +; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4 +; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX1064GISEL-NEXT: s_cbranch_execz .LBB8_3 +; GFX1064GISEL-NEXT: ; %bb.1: ; %else +; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX1064GISEL-NEXT: s_brev_b32 s8, 1 +; GFX1064GISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1064GISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1064GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX1064GISEL-NEXT: v_readlane_b32 s10, v2, s9 +; GFX1064GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX1064GISEL-NEXT: s_max_i32 s8, s8, s10 +; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1064GISEL-NEXT: .LBB8_3: ; %Flow +; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX1064GISEL-NEXT: s_cbranch_execz .LBB8_6 +; GFX1064GISEL-NEXT: ; %bb.4: ; %if +; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX1064GISEL-NEXT: s_brev_b32 s8, 1 +; GFX1064GISEL-NEXT: .LBB8_5: ; =>This Inner Loop Header: Depth=1 +; GFX1064GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX1064GISEL-NEXT: v_readlane_b32 s10, v3, s9 +; GFX1064GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX1064GISEL-NEXT: s_max_i32 s8, s8, s10 +; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB8_5 +; GFX1064GISEL-NEXT: .LBB8_6: ; %endif +; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, s8 +; GFX1064GISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX1064GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1032DAGISEL-LABEL: divergent_cfg_float: +; GFX1032DAGISEL: ; %bb.0: ; %entry +; GFX1032DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1032DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1032DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, 15, v4 +; GFX1032DAGISEL-NEXT: ; implicit-def: $vgpr4 +; GFX1032DAGISEL-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032DAGISEL-NEXT: s_xor_b32 s4, exec_lo, s4 +; GFX1032DAGISEL-NEXT: s_cbranch_execz .LBB8_4 +; GFX1032DAGISEL-NEXT: ; %bb.1: ; %else +; GFX1032DAGISEL-NEXT: s_mov_b32 s5, exec_lo +; GFX1032DAGISEL-NEXT: s_mov_b32 s6, 0x7fc00000 +; GFX1032DAGISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s7, s5 +; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX1032DAGISEL-NEXT: s_bitset0_b32 s5, s7 +; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GFX1032DAGISEL-NEXT: v_max_f32_e64 v3, s6, s8 +; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s6, v3 +; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1032DAGISEL-NEXT: ; %bb.3: +; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v4, s6 +; GFX1032DAGISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1032DAGISEL-NEXT: .LBB8_4: ; %Flow +; GFX1032DAGISEL-NEXT: s_andn2_saveexec_b32 s4, s4 +; GFX1032DAGISEL-NEXT: s_cbranch_execz .LBB8_8 +; GFX1032DAGISEL-NEXT: ; %bb.5: ; %if +; GFX1032DAGISEL-NEXT: s_mov_b32 s5, exec_lo +; GFX1032DAGISEL-NEXT: s_mov_b32 s6, 0x7fc00000 +; GFX1032DAGISEL-NEXT: .LBB8_6: ; =>This Inner Loop Header: Depth=1 +; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s7, s5 +; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v3, s7 +; GFX1032DAGISEL-NEXT: s_bitset0_b32 s5, s7 +; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GFX1032DAGISEL-NEXT: v_max_f32_e64 v2, s6, s8 +; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB8_6 +; GFX1032DAGISEL-NEXT: ; %bb.7: +; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v4, s6 +; GFX1032DAGISEL-NEXT: .LBB8_8: ; %endif +; GFX1032DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032DAGISEL-NEXT: global_store_dword v[0:1], v4, off +; GFX1032DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1032GISEL-LABEL: divergent_cfg_float: +; GFX1032GISEL: ; %bb.0: ; %entry +; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1032GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1032GISEL-NEXT: ; implicit-def: $sgpr4 +; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v4 +; GFX1032GISEL-NEXT: s_and_saveexec_b32 s5, vcc_lo +; GFX1032GISEL-NEXT: s_xor_b32 s5, exec_lo, s5 +; GFX1032GISEL-NEXT: s_cbranch_execz .LBB8_3 +; GFX1032GISEL-NEXT: ; %bb.1: ; %else +; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo +; GFX1032GISEL-NEXT: s_brev_b32 s4, 1 +; GFX1032GISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1032GISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6 +; GFX1032GISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX1032GISEL-NEXT: s_bitset0_b32 s6, s7 +; GFX1032GISEL-NEXT: s_max_i32 s4, s4, s8 +; GFX1032GISEL-NEXT: s_cmp_lg_u32 s6, 0 +; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1032GISEL-NEXT: .LBB8_3: ; %Flow +; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s5, s5 +; GFX1032GISEL-NEXT: s_cbranch_execz .LBB8_6 +; GFX1032GISEL-NEXT: ; %bb.4: ; %if +; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo +; GFX1032GISEL-NEXT: s_brev_b32 s4, 1 +; GFX1032GISEL-NEXT: .LBB8_5: ; =>This Inner Loop Header: Depth=1 +; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6 +; GFX1032GISEL-NEXT: v_readlane_b32 s8, v3, s7 +; GFX1032GISEL-NEXT: s_bitset0_b32 s6, s7 +; GFX1032GISEL-NEXT: s_max_i32 s4, s4, s8 +; GFX1032GISEL-NEXT: s_cmp_lg_u32 s6, 0 +; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB8_5 +; GFX1032GISEL-NEXT: .LBB8_6: ; %endif +; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s5 +; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX1032GISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-LABEL: divergent_cfg_float: +; GFX1164DAGISEL: ; %bb.0: ; %entry +; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v4 +; GFX1164DAGISEL-NEXT: ; implicit-def: $vgpr4 +; GFX1164DAGISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc +; GFX1164DAGISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] +; GFX1164DAGISEL-NEXT: s_cbranch_execz .LBB8_4 +; GFX1164DAGISEL-NEXT: ; %bb.1: ; %else +; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec +; GFX1164DAGISEL-NEXT: s_mov_b32 s4, 0x7fc00000 +; GFX1164DAGISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s5, s[2:3] +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-NEXT: v_readlane_b32 s6, v2, s5 +; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s5 +; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX1164DAGISEL-NEXT: v_max_f32_e64 v3, s4, s6 +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s4, v3 +; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1164DAGISEL-NEXT: ; %bb.3: +; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v4, s4 +; GFX1164DAGISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1164DAGISEL-NEXT: .LBB8_4: ; %Flow +; GFX1164DAGISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1] +; GFX1164DAGISEL-NEXT: s_cbranch_execz .LBB8_8 +; GFX1164DAGISEL-NEXT: ; %bb.5: ; %if +; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec +; GFX1164DAGISEL-NEXT: s_mov_b32 s4, 0x7fc00000 +; GFX1164DAGISEL-NEXT: .LBB8_6: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s5, s[2:3] +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-NEXT: v_readlane_b32 s6, v3, s5 +; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s5 +; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX1164DAGISEL-NEXT: v_max_f32_e64 v2, s4, s6 +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s4, v2 +; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB8_6 +; GFX1164DAGISEL-NEXT: ; %bb.7: +; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v4, s4 +; GFX1164DAGISEL-NEXT: .LBB8_8: ; %endif +; GFX1164DAGISEL-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX1164DAGISEL-NEXT: global_store_b32 v[0:1], v4, off +; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-LABEL: divergent_cfg_float: +; GFX1164GISEL: ; %bb.0: ; %entry +; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-NEXT: ; implicit-def: $sgpr4 +; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v4 +; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] +; GFX1164GISEL-NEXT: s_cbranch_execz .LBB8_3 +; GFX1164GISEL-NEXT: ; %bb.1: ; %else +; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec +; GFX1164GISEL-NEXT: s_brev_b32 s4, 1 +; GFX1164GISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1164GISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-NEXT: s_ctz_i32_b64 s5, s[2:3] +; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-NEXT: v_readlane_b32 s6, v2, s5 +; GFX1164GISEL-NEXT: s_bitset0_b64 s[2:3], s5 +; GFX1164GISEL-NEXT: s_max_i32 s4, s4, s6 +; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1164GISEL-NEXT: .LBB8_3: ; %Flow +; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1] +; GFX1164GISEL-NEXT: s_cbranch_execz .LBB8_6 +; GFX1164GISEL-NEXT: ; %bb.4: ; %if +; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec +; GFX1164GISEL-NEXT: s_brev_b32 s4, 1 +; GFX1164GISEL-NEXT: .LBB8_5: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-NEXT: s_ctz_i32_b64 s5, s[2:3] +; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-NEXT: v_readlane_b32 s6, v3, s5 +; GFX1164GISEL-NEXT: s_bitset0_b64 s[2:3], s5 +; GFX1164GISEL-NEXT: s_max_i32 s4, s4, s6 +; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB8_5 +; GFX1164GISEL-NEXT: .LBB8_6: ; %endif +; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX1164GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-LABEL: divergent_cfg_float: +; GFX1132DAGISEL: ; %bb.0: ; %entry +; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, 15, v4 +; GFX1132DAGISEL-NEXT: ; implicit-def: $vgpr4 +; GFX1132DAGISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX1132DAGISEL-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX1132DAGISEL-NEXT: s_cbranch_execz .LBB8_4 +; GFX1132DAGISEL-NEXT: ; %bb.1: ; %else +; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-NEXT: s_mov_b32 s2, 0x7fc00000 +; GFX1132DAGISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s3, s1 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s3 +; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-NEXT: v_max_f32_e64 v3, s2, s4 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s2, v3 +; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1132DAGISEL-NEXT: ; %bb.3: +; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v4, s2 +; GFX1132DAGISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1132DAGISEL-NEXT: .LBB8_4: ; %Flow +; GFX1132DAGISEL-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX1132DAGISEL-NEXT: s_cbranch_execz .LBB8_8 +; GFX1132DAGISEL-NEXT: ; %bb.5: ; %if +; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-NEXT: s_mov_b32 s2, 0x7fc00000 +; GFX1132DAGISEL-NEXT: .LBB8_6: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s3, s1 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v3, s3 +; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s3 +; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-NEXT: v_max_f32_e64 v2, s2, s4 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s2, v2 +; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB8_6 +; GFX1132DAGISEL-NEXT: ; %bb.7: +; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v4, s2 +; GFX1132DAGISEL-NEXT: .LBB8_8: ; %endif +; GFX1132DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX1132DAGISEL-NEXT: global_store_b32 v[0:1], v4, off +; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-LABEL: divergent_cfg_float: +; GFX1132GISEL: ; %bb.0: ; %entry +; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0 +; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v4 +; GFX1132GISEL-NEXT: s_xor_b32 s1, exec_lo, s1 +; GFX1132GISEL-NEXT: s_cbranch_execz .LBB8_3 +; GFX1132GISEL-NEXT: ; %bb.1: ; %else +; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo +; GFX1132GISEL-NEXT: s_brev_b32 s0, 1 +; GFX1132GISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1132GISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2 +; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3 +; GFX1132GISEL-NEXT: s_max_i32 s0, s0, s4 +; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0 +; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1132GISEL-NEXT: .LBB8_3: ; %Flow +; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s1, s1 +; GFX1132GISEL-NEXT: s_cbranch_execz .LBB8_6 +; GFX1132GISEL-NEXT: ; %bb.4: ; %if +; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo +; GFX1132GISEL-NEXT: s_brev_b32 s0, 1 +; GFX1132GISEL-NEXT: .LBB8_5: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2 +; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-NEXT: v_readlane_b32 s4, v3, s3 +; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3 +; GFX1132GISEL-NEXT: s_max_i32 s0, s0, s4 +; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0 +; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB8_5 +; GFX1132GISEL-NEXT: .LBB8_6: ; %endif +; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %d_cmp = icmp ult i32 %tid, 16 + br i1 %d_cmp, label %if, label %else + +if: + %reducedValTid = call float @llvm.amdgcn.wave.reduce.max.float(float %in2, i32 1) + br label %endif + +else: + %reducedValIn = call float @llvm.amdgcn.wave.reduce.max.float(float %in, i32 1) + br label %endif + +endif: + %combine = phi float [%reducedValTid, %if], [%reducedValIn, %else] + store float %combine, ptr addrspace(1) %out + ret void +} ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GFX11DAGISEL: {{.*}} ; GFX11GISEL: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll index 3c4cbc74aedc1..9bacdf2309efa 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll @@ -1534,6 +1534,887 @@ endif: store i64 %combine, ptr addrspace(1) %out ret void } + +define amdgpu_kernel void @uniform_value_float(ptr addrspace(1) %out, float %in) { +; GFX8DAGISEL-LABEL: uniform_value_float: +; GFX8DAGISEL: ; %bb.0: ; %entry +; GFX8DAGISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX8DAGISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX8DAGISEL-NEXT: flat_store_dword v[0:1], v2 +; GFX8DAGISEL-NEXT: s_endpgm +; +; GFX8GISEL-LABEL: uniform_value_float: +; GFX8GISEL: ; %bb.0: ; %entry +; GFX8GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2 +; GFX8GISEL-NEXT: s_endpgm +; +; GFX9DAGISEL-LABEL: uniform_value_float: +; GFX9DAGISEL: ; %bb.0: ; %entry +; GFX9DAGISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; GFX9DAGISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9DAGISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v1, s2 +; GFX9DAGISEL-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9DAGISEL-NEXT: s_endpgm +; +; GFX9GISEL-LABEL: uniform_value_float: +; GFX9GISEL: ; %bb.0: ; %entry +; GFX9GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; GFX9GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX9GISEL-NEXT: global_store_dword v1, v0, s[0:1] +; GFX9GISEL-NEXT: s_endpgm +; +; GFX10DAGISEL-LABEL: uniform_value_float: +; GFX10DAGISEL: ; %bb.0: ; %entry +; GFX10DAGISEL-NEXT: s_clause 0x1 +; GFX10DAGISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; GFX10DAGISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10DAGISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX10DAGISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10DAGISEL-NEXT: v_mov_b32_e32 v1, s2 +; GFX10DAGISEL-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10DAGISEL-NEXT: s_endpgm +; +; GFX10GISEL-LABEL: uniform_value_float: +; GFX10GISEL: ; %bb.0: ; %entry +; GFX10GISEL-NEXT: s_clause 0x1 +; GFX10GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; GFX10GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX10GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX10GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX10GISEL-NEXT: global_store_dword v1, v0, s[0:1] +; GFX10GISEL-NEXT: s_endpgm +; +; GFX1164DAGISEL-LABEL: uniform_value_float: +; GFX1164DAGISEL: ; %bb.0: ; %entry +; GFX1164DAGISEL-NEXT: s_clause 0x1 +; GFX1164DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v1, s2 +; GFX1164DAGISEL-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX1164DAGISEL-NEXT: s_endpgm +; +; GFX1164GISEL-LABEL: uniform_value_float: +; GFX1164GISEL: ; %bb.0: ; %entry +; GFX1164GISEL-NEXT: s_clause 0x1 +; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX1164GISEL-NEXT: s_endpgm +; +; GFX1132DAGISEL-LABEL: uniform_value_float: +; GFX1132DAGISEL: ; %bb.0: ; %entry +; GFX1132DAGISEL-NEXT: s_clause 0x1 +; GFX1132DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX1132DAGISEL-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX1132DAGISEL-NEXT: s_endpgm +; +; GFX1132GISEL-LABEL: uniform_value_float: +; GFX1132GISEL: ; %bb.0: ; %entry +; GFX1132GISEL-NEXT: s_clause 0x1 +; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2 +; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX1132GISEL-NEXT: s_endpgm +entry: + %result = call float @llvm.amdgcn.wave.reduce.min.float(float %in, i32 1) + store float %result, ptr addrspace(1) %out + ret void +} + +define void @divergent_value_float(ptr addrspace(1) %out, float %in) { +; GFX8DAGISEL-LABEL: divergent_value_float: +; GFX8DAGISEL: ; %bb.0: ; %entry +; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8DAGISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX8DAGISEL-NEXT: s_mov_b32 s6, 0x7fc00000 +; GFX8DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s8 +; GFX8DAGISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX8DAGISEL-NEXT: v_min_f32_e32 v3, s6, v3 +; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s6, v3 +; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX8DAGISEL-NEXT: ; %bb.2: +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX8DAGISEL-NEXT: flat_store_dword v[0:1], v2 +; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) +; GFX8DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX8GISEL-LABEL: divergent_value_float: +; GFX8GISEL: ; %bb.0: ; %entry +; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX8GISEL-NEXT: s_brev_b32 s6, -2 +; GFX8GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX8GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX8GISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX8GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX8GISEL-NEXT: s_min_i32 s6, s6, s8 +; GFX8GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX8GISEL-NEXT: ; %bb.2: +; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2 +; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX8GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9DAGISEL-LABEL: divergent_value_float: +; GFX9DAGISEL: ; %bb.0: ; %entry +; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9DAGISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9DAGISEL-NEXT: s_mov_b32 s6, 0x7fc00000 +; GFX9DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v3, s8 +; GFX9DAGISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9DAGISEL-NEXT: v_min_f32_e32 v3, s6, v3 +; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s6, v3 +; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX9DAGISEL-NEXT: ; %bb.2: +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX9DAGISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GISEL-LABEL: divergent_value_float: +; GFX9GISEL: ; %bb.0: ; %entry +; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9GISEL-NEXT: s_brev_b32 s6, -2 +; GFX9GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX9GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9GISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX9GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9GISEL-NEXT: s_min_i32 s6, s6, s8 +; GFX9GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX9GISEL-NEXT: ; %bb.2: +; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX9GISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1064DAGISEL-LABEL: divergent_value_float: +; GFX1064DAGISEL: ; %bb.0: ; %entry +; GFX1064DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1064DAGISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX1064DAGISEL-NEXT: s_mov_b32 s6, 0x7fc00000 +; GFX1064DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX1064DAGISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX1064DAGISEL-NEXT: v_min_f32_e64 v3, s6, s8 +; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s6, v3 +; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1064DAGISEL-NEXT: ; %bb.2: +; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX1064DAGISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX1064DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1064GISEL-LABEL: divergent_value_float: +; GFX1064GISEL: ; %bb.0: ; %entry +; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX1064GISEL-NEXT: s_brev_b32 s6, -2 +; GFX1064GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1064GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX1064GISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX1064GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX1064GISEL-NEXT: s_min_i32 s6, s6, s8 +; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1064GISEL-NEXT: ; %bb.2: +; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX1064GISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX1064GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1032DAGISEL-LABEL: divergent_value_float: +; GFX1032DAGISEL: ; %bb.0: ; %entry +; GFX1032DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1032DAGISEL-NEXT: s_mov_b32 s4, exec_lo +; GFX1032DAGISEL-NEXT: s_mov_b32 s5, 0x7fc00000 +; GFX1032DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s6, s4 +; GFX1032DAGISEL-NEXT: v_readlane_b32 s7, v2, s6 +; GFX1032DAGISEL-NEXT: s_bitset0_b32 s4, s6 +; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX1032DAGISEL-NEXT: v_min_f32_e64 v3, s5, s7 +; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v3 +; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1032DAGISEL-NEXT: ; %bb.2: +; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v2, s5 +; GFX1032DAGISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX1032DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1032GISEL-LABEL: divergent_value_float: +; GFX1032GISEL: ; %bb.0: ; %entry +; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1032GISEL-NEXT: s_mov_b32 s5, exec_lo +; GFX1032GISEL-NEXT: s_brev_b32 s4, -2 +; GFX1032GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1032GISEL-NEXT: s_ff1_i32_b32 s6, s5 +; GFX1032GISEL-NEXT: v_readlane_b32 s7, v2, s6 +; GFX1032GISEL-NEXT: s_bitset0_b32 s5, s6 +; GFX1032GISEL-NEXT: s_min_i32 s4, s4, s7 +; GFX1032GISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1032GISEL-NEXT: ; %bb.2: +; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX1032GISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-LABEL: divergent_value_float: +; GFX1164DAGISEL: ; %bb.0: ; %entry +; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0x7fc00000 +; GFX1164DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-NEXT: v_min_f32_e64 v3, s2, s4 +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s2, v3 +; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1164DAGISEL-NEXT: ; %bb.2: +; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-NEXT: global_store_b32 v[0:1], v2, off +; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-LABEL: divergent_value_float: +; GFX1164GISEL: ; %bb.0: ; %entry +; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-NEXT: s_brev_b32 s2, -2 +; GFX1164GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164GISEL-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164GISEL-NEXT: s_min_i32 s2, s2, s4 +; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1164GISEL-NEXT: ; %bb.2: +; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-LABEL: divergent_value_float: +; GFX1132DAGISEL: ; %bb.0: ; %entry +; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-NEXT: s_mov_b32 s0, exec_lo +; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7fc00000 +; GFX1132DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s0 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-NEXT: s_bitset0_b32 s0, s2 +; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s0, 0 +; GFX1132DAGISEL-NEXT: v_min_f32_e64 v3, s1, s3 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v3 +; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1132DAGISEL-NEXT: ; %bb.2: +; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s1 +; GFX1132DAGISEL-NEXT: global_store_b32 v[0:1], v2, off +; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-LABEL: divergent_value_float: +; GFX1132GISEL: ; %bb.0: ; %entry +; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX1132GISEL-NEXT: s_brev_b32 s0, -2 +; GFX1132GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX1132GISEL-NEXT: s_min_i32 s0, s0, s3 +; GFX1132GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB7_1 +; GFX1132GISEL-NEXT: ; %bb.2: +; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + %result = call float @llvm.amdgcn.wave.reduce.min.float(float %in, i32 1) + store float %result, ptr addrspace(1) %out + ret void +} + +define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) { +; GFX8DAGISEL-LABEL: divergent_cfg_float: +; GFX8DAGISEL: ; %bb.0: ; %entry +; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX8DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v4 +; GFX8DAGISEL-NEXT: ; implicit-def: $vgpr4 +; GFX8DAGISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8DAGISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX8DAGISEL-NEXT: s_cbranch_execz .LBB8_4 +; GFX8DAGISEL-NEXT: ; %bb.1: ; %else +; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX8DAGISEL-NEXT: s_mov_b32 s8, 0x7fc00000 +; GFX8DAGISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v2, s9 +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s10 +; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX8DAGISEL-NEXT: v_min_f32_e32 v3, s8, v3 +; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s8, v3 +; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX8DAGISEL-NEXT: ; %bb.3: +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s8 +; GFX8DAGISEL-NEXT: ; implicit-def: $vgpr3 +; GFX8DAGISEL-NEXT: .LBB8_4: ; %Flow +; GFX8DAGISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX8DAGISEL-NEXT: s_cbranch_execz .LBB8_8 +; GFX8DAGISEL-NEXT: ; %bb.5: ; %if +; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX8DAGISEL-NEXT: s_mov_b32 s8, 0x7fc00000 +; GFX8DAGISEL-NEXT: .LBB8_6: ; =>This Inner Loop Header: Depth=1 +; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v3, s9 +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s10 +; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX8DAGISEL-NEXT: v_min_f32_e32 v2, s8, v2 +; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s8, v2 +; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB8_6 +; GFX8DAGISEL-NEXT: ; %bb.7: +; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s8 +; GFX8DAGISEL-NEXT: .LBB8_8: ; %endif +; GFX8DAGISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8DAGISEL-NEXT: flat_store_dword v[0:1], v4 +; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) +; GFX8DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX8GISEL-LABEL: divergent_cfg_float: +; GFX8GISEL: ; %bb.0: ; %entry +; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4 +; GFX8GISEL-NEXT: ; implicit-def: $sgpr8 +; GFX8GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX8GISEL-NEXT: s_cbranch_execz .LBB8_3 +; GFX8GISEL-NEXT: ; %bb.1: ; %else +; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX8GISEL-NEXT: s_brev_b32 s8, -2 +; GFX8GISEL-NEXT: ; implicit-def: $vgpr3 +; GFX8GISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX8GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX8GISEL-NEXT: v_readlane_b32 s10, v2, s9 +; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX8GISEL-NEXT: s_min_i32 s8, s8, s10 +; GFX8GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX8GISEL-NEXT: .LBB8_3: ; %Flow +; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX8GISEL-NEXT: s_cbranch_execz .LBB8_6 +; GFX8GISEL-NEXT: ; %bb.4: ; %if +; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX8GISEL-NEXT: s_brev_b32 s8, -2 +; GFX8GISEL-NEXT: .LBB8_5: ; =>This Inner Loop Header: Depth=1 +; GFX8GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX8GISEL-NEXT: v_readlane_b32 s10, v3, s9 +; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX8GISEL-NEXT: s_min_i32 s8, s8, s10 +; GFX8GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB8_5 +; GFX8GISEL-NEXT: .LBB8_6: ; %endif +; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s8 +; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2 +; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX8GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9DAGISEL-LABEL: divergent_cfg_float: +; GFX9DAGISEL: ; %bb.0: ; %entry +; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX9DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v4 +; GFX9DAGISEL-NEXT: ; implicit-def: $vgpr4 +; GFX9DAGISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9DAGISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9DAGISEL-NEXT: s_cbranch_execz .LBB8_4 +; GFX9DAGISEL-NEXT: ; %bb.1: ; %else +; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9DAGISEL-NEXT: s_mov_b32 s8, 0x7fc00000 +; GFX9DAGISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v2, s9 +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v3, s10 +; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9DAGISEL-NEXT: v_min_f32_e32 v3, s8, v3 +; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s8, v3 +; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX9DAGISEL-NEXT: ; %bb.3: +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s8 +; GFX9DAGISEL-NEXT: ; implicit-def: $vgpr3 +; GFX9DAGISEL-NEXT: .LBB8_4: ; %Flow +; GFX9DAGISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9DAGISEL-NEXT: s_cbranch_execz .LBB8_8 +; GFX9DAGISEL-NEXT: ; %bb.5: ; %if +; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9DAGISEL-NEXT: s_mov_b32 s8, 0x7fc00000 +; GFX9DAGISEL-NEXT: .LBB8_6: ; =>This Inner Loop Header: Depth=1 +; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v3, s9 +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s10 +; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9DAGISEL-NEXT: v_min_f32_e32 v2, s8, v2 +; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s8, v2 +; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB8_6 +; GFX9DAGISEL-NEXT: ; %bb.7: +; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s8 +; GFX9DAGISEL-NEXT: .LBB8_8: ; %endif +; GFX9DAGISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9DAGISEL-NEXT: global_store_dword v[0:1], v4, off +; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GISEL-LABEL: divergent_cfg_float: +; GFX9GISEL: ; %bb.0: ; %entry +; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4 +; GFX9GISEL-NEXT: ; implicit-def: $sgpr8 +; GFX9GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9GISEL-NEXT: s_cbranch_execz .LBB8_3 +; GFX9GISEL-NEXT: ; %bb.1: ; %else +; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9GISEL-NEXT: s_brev_b32 s8, -2 +; GFX9GISEL-NEXT: ; implicit-def: $vgpr3 +; GFX9GISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX9GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9GISEL-NEXT: v_readlane_b32 s10, v2, s9 +; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9GISEL-NEXT: s_min_i32 s8, s8, s10 +; GFX9GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX9GISEL-NEXT: .LBB8_3: ; %Flow +; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9GISEL-NEXT: s_cbranch_execz .LBB8_6 +; GFX9GISEL-NEXT: ; %bb.4: ; %if +; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9GISEL-NEXT: s_brev_b32 s8, -2 +; GFX9GISEL-NEXT: .LBB8_5: ; =>This Inner Loop Header: Depth=1 +; GFX9GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9GISEL-NEXT: v_readlane_b32 s10, v3, s9 +; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9GISEL-NEXT: s_min_i32 s8, s8, s10 +; GFX9GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB8_5 +; GFX9GISEL-NEXT: .LBB8_6: ; %endif +; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s8 +; GFX9GISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1064DAGISEL-LABEL: divergent_cfg_float: +; GFX1064DAGISEL: ; %bb.0: ; %entry +; GFX1064DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1064DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1064DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v4 +; GFX1064DAGISEL-NEXT: ; implicit-def: $vgpr4 +; GFX1064DAGISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064DAGISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX1064DAGISEL-NEXT: s_cbranch_execz .LBB8_4 +; GFX1064DAGISEL-NEXT: ; %bb.1: ; %else +; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX1064DAGISEL-NEXT: s_mov_b32 s8, 0x7fc00000 +; GFX1064DAGISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX1064DAGISEL-NEXT: v_readlane_b32 s10, v2, s9 +; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX1064DAGISEL-NEXT: v_min_f32_e64 v3, s8, s10 +; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s8, v3 +; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1064DAGISEL-NEXT: ; %bb.3: +; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v4, s8 +; GFX1064DAGISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1064DAGISEL-NEXT: .LBB8_4: ; %Flow +; GFX1064DAGISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX1064DAGISEL-NEXT: s_cbranch_execz .LBB8_8 +; GFX1064DAGISEL-NEXT: ; %bb.5: ; %if +; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX1064DAGISEL-NEXT: s_mov_b32 s8, 0x7fc00000 +; GFX1064DAGISEL-NEXT: .LBB8_6: ; =>This Inner Loop Header: Depth=1 +; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX1064DAGISEL-NEXT: v_readlane_b32 s10, v3, s9 +; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX1064DAGISEL-NEXT: v_min_f32_e64 v2, s8, s10 +; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s8, v2 +; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB8_6 +; GFX1064DAGISEL-NEXT: ; %bb.7: +; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v4, s8 +; GFX1064DAGISEL-NEXT: .LBB8_8: ; %endif +; GFX1064DAGISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064DAGISEL-NEXT: global_store_dword v[0:1], v4, off +; GFX1064DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1064GISEL-LABEL: divergent_cfg_float: +; GFX1064GISEL: ; %bb.0: ; %entry +; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1064GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1064GISEL-NEXT: ; implicit-def: $sgpr8 +; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4 +; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX1064GISEL-NEXT: s_cbranch_execz .LBB8_3 +; GFX1064GISEL-NEXT: ; %bb.1: ; %else +; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX1064GISEL-NEXT: s_brev_b32 s8, -2 +; GFX1064GISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1064GISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1064GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX1064GISEL-NEXT: v_readlane_b32 s10, v2, s9 +; GFX1064GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX1064GISEL-NEXT: s_min_i32 s8, s8, s10 +; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1064GISEL-NEXT: .LBB8_3: ; %Flow +; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX1064GISEL-NEXT: s_cbranch_execz .LBB8_6 +; GFX1064GISEL-NEXT: ; %bb.4: ; %if +; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX1064GISEL-NEXT: s_brev_b32 s8, -2 +; GFX1064GISEL-NEXT: .LBB8_5: ; =>This Inner Loop Header: Depth=1 +; GFX1064GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX1064GISEL-NEXT: v_readlane_b32 s10, v3, s9 +; GFX1064GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX1064GISEL-NEXT: s_min_i32 s8, s8, s10 +; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB8_5 +; GFX1064GISEL-NEXT: .LBB8_6: ; %endif +; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, s8 +; GFX1064GISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX1064GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1032DAGISEL-LABEL: divergent_cfg_float: +; GFX1032DAGISEL: ; %bb.0: ; %entry +; GFX1032DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1032DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1032DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, 15, v4 +; GFX1032DAGISEL-NEXT: ; implicit-def: $vgpr4 +; GFX1032DAGISEL-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032DAGISEL-NEXT: s_xor_b32 s4, exec_lo, s4 +; GFX1032DAGISEL-NEXT: s_cbranch_execz .LBB8_4 +; GFX1032DAGISEL-NEXT: ; %bb.1: ; %else +; GFX1032DAGISEL-NEXT: s_mov_b32 s5, exec_lo +; GFX1032DAGISEL-NEXT: s_mov_b32 s6, 0x7fc00000 +; GFX1032DAGISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s7, s5 +; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX1032DAGISEL-NEXT: s_bitset0_b32 s5, s7 +; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GFX1032DAGISEL-NEXT: v_min_f32_e64 v3, s6, s8 +; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s6, v3 +; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1032DAGISEL-NEXT: ; %bb.3: +; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v4, s6 +; GFX1032DAGISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1032DAGISEL-NEXT: .LBB8_4: ; %Flow +; GFX1032DAGISEL-NEXT: s_andn2_saveexec_b32 s4, s4 +; GFX1032DAGISEL-NEXT: s_cbranch_execz .LBB8_8 +; GFX1032DAGISEL-NEXT: ; %bb.5: ; %if +; GFX1032DAGISEL-NEXT: s_mov_b32 s5, exec_lo +; GFX1032DAGISEL-NEXT: s_mov_b32 s6, 0x7fc00000 +; GFX1032DAGISEL-NEXT: .LBB8_6: ; =>This Inner Loop Header: Depth=1 +; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s7, s5 +; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v3, s7 +; GFX1032DAGISEL-NEXT: s_bitset0_b32 s5, s7 +; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GFX1032DAGISEL-NEXT: v_min_f32_e64 v2, s6, s8 +; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB8_6 +; GFX1032DAGISEL-NEXT: ; %bb.7: +; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v4, s6 +; GFX1032DAGISEL-NEXT: .LBB8_8: ; %endif +; GFX1032DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032DAGISEL-NEXT: global_store_dword v[0:1], v4, off +; GFX1032DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1032GISEL-LABEL: divergent_cfg_float: +; GFX1032GISEL: ; %bb.0: ; %entry +; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1032GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1032GISEL-NEXT: ; implicit-def: $sgpr4 +; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v4 +; GFX1032GISEL-NEXT: s_and_saveexec_b32 s5, vcc_lo +; GFX1032GISEL-NEXT: s_xor_b32 s5, exec_lo, s5 +; GFX1032GISEL-NEXT: s_cbranch_execz .LBB8_3 +; GFX1032GISEL-NEXT: ; %bb.1: ; %else +; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo +; GFX1032GISEL-NEXT: s_brev_b32 s4, -2 +; GFX1032GISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1032GISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6 +; GFX1032GISEL-NEXT: v_readlane_b32 s8, v2, s7 +; GFX1032GISEL-NEXT: s_bitset0_b32 s6, s7 +; GFX1032GISEL-NEXT: s_min_i32 s4, s4, s8 +; GFX1032GISEL-NEXT: s_cmp_lg_u32 s6, 0 +; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1032GISEL-NEXT: .LBB8_3: ; %Flow +; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s5, s5 +; GFX1032GISEL-NEXT: s_cbranch_execz .LBB8_6 +; GFX1032GISEL-NEXT: ; %bb.4: ; %if +; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo +; GFX1032GISEL-NEXT: s_brev_b32 s4, -2 +; GFX1032GISEL-NEXT: .LBB8_5: ; =>This Inner Loop Header: Depth=1 +; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6 +; GFX1032GISEL-NEXT: v_readlane_b32 s8, v3, s7 +; GFX1032GISEL-NEXT: s_bitset0_b32 s6, s7 +; GFX1032GISEL-NEXT: s_min_i32 s4, s4, s8 +; GFX1032GISEL-NEXT: s_cmp_lg_u32 s6, 0 +; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB8_5 +; GFX1032GISEL-NEXT: .LBB8_6: ; %endif +; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s5 +; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX1032GISEL-NEXT: global_store_dword v[0:1], v2, off +; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-LABEL: divergent_cfg_float: +; GFX1164DAGISEL: ; %bb.0: ; %entry +; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v4 +; GFX1164DAGISEL-NEXT: ; implicit-def: $vgpr4 +; GFX1164DAGISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc +; GFX1164DAGISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] +; GFX1164DAGISEL-NEXT: s_cbranch_execz .LBB8_4 +; GFX1164DAGISEL-NEXT: ; %bb.1: ; %else +; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec +; GFX1164DAGISEL-NEXT: s_mov_b32 s4, 0x7fc00000 +; GFX1164DAGISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s5, s[2:3] +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-NEXT: v_readlane_b32 s6, v2, s5 +; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s5 +; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX1164DAGISEL-NEXT: v_min_f32_e64 v3, s4, s6 +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s4, v3 +; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1164DAGISEL-NEXT: ; %bb.3: +; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v4, s4 +; GFX1164DAGISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1164DAGISEL-NEXT: .LBB8_4: ; %Flow +; GFX1164DAGISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1] +; GFX1164DAGISEL-NEXT: s_cbranch_execz .LBB8_8 +; GFX1164DAGISEL-NEXT: ; %bb.5: ; %if +; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec +; GFX1164DAGISEL-NEXT: s_mov_b32 s4, 0x7fc00000 +; GFX1164DAGISEL-NEXT: .LBB8_6: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s5, s[2:3] +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-NEXT: v_readlane_b32 s6, v3, s5 +; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s5 +; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX1164DAGISEL-NEXT: v_min_f32_e64 v2, s4, s6 +; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s4, v2 +; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB8_6 +; GFX1164DAGISEL-NEXT: ; %bb.7: +; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v4, s4 +; GFX1164DAGISEL-NEXT: .LBB8_8: ; %endif +; GFX1164DAGISEL-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX1164DAGISEL-NEXT: global_store_b32 v[0:1], v4, off +; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-LABEL: divergent_cfg_float: +; GFX1164GISEL: ; %bb.0: ; %entry +; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-NEXT: ; implicit-def: $sgpr4 +; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v4 +; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] +; GFX1164GISEL-NEXT: s_cbranch_execz .LBB8_3 +; GFX1164GISEL-NEXT: ; %bb.1: ; %else +; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec +; GFX1164GISEL-NEXT: s_brev_b32 s4, -2 +; GFX1164GISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1164GISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-NEXT: s_ctz_i32_b64 s5, s[2:3] +; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-NEXT: v_readlane_b32 s6, v2, s5 +; GFX1164GISEL-NEXT: s_bitset0_b64 s[2:3], s5 +; GFX1164GISEL-NEXT: s_min_i32 s4, s4, s6 +; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1164GISEL-NEXT: .LBB8_3: ; %Flow +; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1] +; GFX1164GISEL-NEXT: s_cbranch_execz .LBB8_6 +; GFX1164GISEL-NEXT: ; %bb.4: ; %if +; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec +; GFX1164GISEL-NEXT: s_brev_b32 s4, -2 +; GFX1164GISEL-NEXT: .LBB8_5: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-NEXT: s_ctz_i32_b64 s5, s[2:3] +; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-NEXT: v_readlane_b32 s6, v3, s5 +; GFX1164GISEL-NEXT: s_bitset0_b64 s[2:3], s5 +; GFX1164GISEL-NEXT: s_min_i32 s4, s4, s6 +; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB8_5 +; GFX1164GISEL-NEXT: .LBB8_6: ; %endif +; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX1164GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-LABEL: divergent_cfg_float: +; GFX1132DAGISEL: ; %bb.0: ; %entry +; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, 15, v4 +; GFX1132DAGISEL-NEXT: ; implicit-def: $vgpr4 +; GFX1132DAGISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX1132DAGISEL-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX1132DAGISEL-NEXT: s_cbranch_execz .LBB8_4 +; GFX1132DAGISEL-NEXT: ; %bb.1: ; %else +; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-NEXT: s_mov_b32 s2, 0x7fc00000 +; GFX1132DAGISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s3, s1 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s3 +; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-NEXT: v_min_f32_e64 v3, s2, s4 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s2, v3 +; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1132DAGISEL-NEXT: ; %bb.3: +; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v4, s2 +; GFX1132DAGISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1132DAGISEL-NEXT: .LBB8_4: ; %Flow +; GFX1132DAGISEL-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX1132DAGISEL-NEXT: s_cbranch_execz .LBB8_8 +; GFX1132DAGISEL-NEXT: ; %bb.5: ; %if +; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-NEXT: s_mov_b32 s2, 0x7fc00000 +; GFX1132DAGISEL-NEXT: .LBB8_6: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s3, s1 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v3, s3 +; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s3 +; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-NEXT: v_min_f32_e64 v2, s2, s4 +; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s2, v2 +; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB8_6 +; GFX1132DAGISEL-NEXT: ; %bb.7: +; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v4, s2 +; GFX1132DAGISEL-NEXT: .LBB8_8: ; %endif +; GFX1132DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX1132DAGISEL-NEXT: global_store_b32 v[0:1], v4, off +; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-LABEL: divergent_cfg_float: +; GFX1132GISEL: ; %bb.0: ; %entry +; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31 +; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0 +; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v4 +; GFX1132GISEL-NEXT: s_xor_b32 s1, exec_lo, s1 +; GFX1132GISEL-NEXT: s_cbranch_execz .LBB8_3 +; GFX1132GISEL-NEXT: ; %bb.1: ; %else +; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo +; GFX1132GISEL-NEXT: s_brev_b32 s0, -2 +; GFX1132GISEL-NEXT: ; implicit-def: $vgpr3 +; GFX1132GISEL-NEXT: .LBB8_2: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2 +; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3 +; GFX1132GISEL-NEXT: s_min_i32 s0, s0, s4 +; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0 +; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB8_2 +; GFX1132GISEL-NEXT: .LBB8_3: ; %Flow +; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s1, s1 +; GFX1132GISEL-NEXT: s_cbranch_execz .LBB8_6 +; GFX1132GISEL-NEXT: ; %bb.4: ; %if +; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo +; GFX1132GISEL-NEXT: s_brev_b32 s0, -2 +; GFX1132GISEL-NEXT: .LBB8_5: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2 +; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-NEXT: v_readlane_b32 s4, v3, s3 +; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3 +; GFX1132GISEL-NEXT: s_min_i32 s0, s0, s4 +; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0 +; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB8_5 +; GFX1132GISEL-NEXT: .LBB8_6: ; %endif +; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132GISEL-NEXT: global_store_b32 v[0:1], v2, off +; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %d_cmp = icmp ult i32 %tid, 16 + br i1 %d_cmp, label %if, label %else + +if: + %reducedValTid = call float @llvm.amdgcn.wave.reduce.min.float(float %in2, i32 1) + br label %endif + +else: + %reducedValIn = call float @llvm.amdgcn.wave.reduce.min.float(float %in, i32 1) + br label %endif + +endif: + %combine = phi float [%reducedValTid, %if], [%reducedValIn, %else] + store float %combine, ptr addrspace(1) %out + ret void +} ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GFX11DAGISEL: {{.*}} ; GFX11GISEL: {{.*}}