From 28a2c5da5c68b795867429262793aab516d01876 Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Sat, 4 Oct 2025 15:10:10 -0400 Subject: [PATCH] [mlir][vector] Simplify rewrite pattern inheriting constructors. NFC. Use the `Base` type alias from https://github.com/llvm/llvm-project/pull/158433. --- .../Conversion/VectorToAMX/VectorToAMX.cpp | 2 +- .../VectorToArmSME/VectorToArmSME.cpp | 26 +++++++++---------- .../Conversion/VectorToGPU/VectorToGPU.cpp | 4 +-- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 4 +-- .../VectorToSPIRV/VectorToSPIRV.cpp | 2 +- .../VectorToXeGPU/VectorToXeGPU.cpp | 14 +++++----- 6 files changed, 26 insertions(+), 26 deletions(-) diff --git a/mlir/lib/Conversion/VectorToAMX/VectorToAMX.cpp b/mlir/lib/Conversion/VectorToAMX/VectorToAMX.cpp index 7b9ed1d8cd21a..79c2f23c8e7f3 100644 --- a/mlir/lib/Conversion/VectorToAMX/VectorToAMX.cpp +++ b/mlir/lib/Conversion/VectorToAMX/VectorToAMX.cpp @@ -363,7 +363,7 @@ static TypedValue storeTile(PatternRewriter &rewriter, } struct ContractionToAMX : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::ContractionOp contractOp, PatternRewriter &rewriter) const override { diff --git a/mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp b/mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp index 4e1da39c29260..363685a691180 100644 --- a/mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp +++ b/mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp @@ -44,7 +44,7 @@ namespace { /// arm_sme.tile_load ... layout struct TransferReadToArmSMELowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::TransferReadOp transferReadOp, PatternRewriter &rewriter) const final { @@ -120,7 +120,7 @@ struct TransferReadToArmSMELowering /// : memref, vector<[16]x[16]xi8> struct TransferWriteToArmSMELowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::TransferWriteOp writeOp, PatternRewriter &rewriter) const final { @@ -157,7 +157,7 @@ struct TransferWriteToArmSMELowering /// Conversion pattern for vector.load. struct VectorLoadToArmSMELowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::LoadOp load, PatternRewriter &rewriter) const override { @@ -173,7 +173,7 @@ struct VectorLoadToArmSMELowering : public OpRewritePattern { /// Conversion pattern for vector.store. struct VectorStoreToArmSMELowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::StoreOp store, PatternRewriter &rewriter) const override { @@ -208,7 +208,7 @@ struct VectorStoreToArmSMELowering : public OpRewritePattern { /// Supports scalar, 0-d vector, and 1-d vector broadcasts. struct BroadcastOpToArmSMELowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::BroadcastOp broadcastOp, PatternRewriter &rewriter) const final { @@ -279,7 +279,7 @@ struct BroadcastOpToArmSMELowering /// implementation, perhaps with tile <-> vector (MOVA) ops. struct TransposeOpToArmSMELowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::TransposeOp transposeOp, PatternRewriter &rewriter) const final { @@ -372,7 +372,7 @@ struct TransposeOpToArmSMELowering struct VectorOuterProductToArmSMELowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::OuterProductOp outerProductOp, PatternRewriter &rewriter) const override { @@ -451,7 +451,7 @@ struct VectorOuterProductToArmSMELowering /// ``` struct VectorExtractToArmSMELowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::ExtractOp extractOp, PatternRewriter &rewriter) const override { @@ -507,7 +507,7 @@ struct VectorExtractToArmSMELowering /// ``` struct VectorInsertToArmSMELowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::InsertOp insertOp, PatternRewriter &rewriter) const override { @@ -568,7 +568,7 @@ struct VectorInsertToArmSMELowering /// } /// ``` struct VectorPrintToArmSMELowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::PrintOp printOp, PatternRewriter &rewriter) const override { @@ -623,7 +623,7 @@ struct VectorPrintToArmSMELowering : public OpRewritePattern { /// ``` struct FoldTransferWriteOfExtractTileSlice : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::TransferWriteOp writeOp, PatternRewriter &rewriter) const final { @@ -679,7 +679,7 @@ struct FoldTransferWriteOfExtractTileSlice /// ``` struct ExtractFromCreateMaskToPselLowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::ExtractOp extractOp, PatternRewriter &rewriter) const override { @@ -734,7 +734,7 @@ struct ExtractFromCreateMaskToPselLowering // Convert all `vector.splat` to `vector.broadcast`. There is a path from // `vector.broadcast` to ArmSME via another pattern. struct ConvertSplatToBroadcast : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::SplatOp splatOp, PatternRewriter &rewriter) const final { diff --git a/mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp b/mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp index d6a262275be3d..98434357f826f 100644 --- a/mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp +++ b/mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp @@ -386,7 +386,7 @@ namespace { // to MMA matmul. struct PrepareContractToGPUMMA : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::ContractionOp op, PatternRewriter &rewriter) const override { @@ -450,7 +450,7 @@ struct PrepareContractToGPUMMA // Shared Memory to registers. struct CombineTransferReadOpTranspose final : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::TransposeOp op, PatternRewriter &rewriter) const override { diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp index e0b1a88d01cdc..546164628b795 100644 --- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp +++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp @@ -1342,7 +1342,7 @@ struct VectorScalableExtractOpLowering /// ``` class VectorFMAOpNDRewritePattern : public OpRewritePattern { public: - using OpRewritePattern::OpRewritePattern; + using Base::Base; void initialize() { // This pattern recursively unpacks one dimension at a time. The recursion @@ -2127,7 +2127,7 @@ FailureOr ContractionOpToMatmulOpLowering::matchAndRewriteMaskableOp( class TransposeOpToMatrixTransposeOpLowering : public OpRewritePattern { public: - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::TransposeOp op, PatternRewriter &rewriter) const override { diff --git a/mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp b/mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp index 5061a4454a7fd..311ff6f5fbeee 100644 --- a/mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp +++ b/mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp @@ -838,7 +838,7 @@ struct VectorStoreOpConverter final struct VectorReductionToIntDotProd final : OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::ReductionOp op, PatternRewriter &rewriter) const override { diff --git a/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp b/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp index 9f5585a701438..e2c7d803e5a5e 100644 --- a/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp +++ b/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp @@ -475,7 +475,7 @@ static LogicalResult lowerToScatteredStoreOp(vector::TransferWriteOp writeOp, } struct TransferReadLowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::TransferReadOp readOp, PatternRewriter &rewriter) const override { @@ -546,7 +546,7 @@ struct TransferReadLowering : public OpRewritePattern { struct TransferWriteLowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::TransferWriteOp writeOp, PatternRewriter &rewriter) const override { @@ -597,7 +597,7 @@ struct TransferWriteLowering }; struct GatherLowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::GatherOp gatherOp, PatternRewriter &rewriter) const override { @@ -632,7 +632,7 @@ struct GatherLowering : public OpRewritePattern { }; struct ScatterLowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::ScatterOp scatterOp, PatternRewriter &rewriter) const override { @@ -662,7 +662,7 @@ struct ScatterLowering : public OpRewritePattern { }; struct LoadLowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::LoadOp loadOp, PatternRewriter &rewriter) const override { @@ -694,7 +694,7 @@ struct LoadLowering : public OpRewritePattern { }; struct StoreLowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::StoreOp storeOp, PatternRewriter &rewriter) const override { @@ -727,7 +727,7 @@ struct StoreLowering : public OpRewritePattern { }; struct ContractionLowering : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; + using Base::Base; LogicalResult matchAndRewrite(vector::ContractionOp contractOp, PatternRewriter &rewriter) const override {