From ad7940baf1c9b20b1932ace12629ffdcc66101ba Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Mon, 6 Oct 2025 17:51:06 -0700 Subject: [PATCH 1/2] [RISCV] Add a new subtarget feature for throttled vector FP64 --- llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++++ llvm/test/CodeGen/RISCV/features-info.ll | 1 + 2 files changed, 5 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 27cf057112869..0d3df0e188505 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1823,6 +1823,10 @@ def TuneConditionalCompressedMoveFusion def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">; def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">; +def TuneHasThrottledVecFP64 + : SubtargetFeature<"throttled-vec-fp64", "HasThrottledVectorFP64", "true", + "Certain vector FP64 operations have limited performance">; + def TuneMIPSP8700 : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700", "MIPS p8700 processor">; diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 1a7a72d3e072b..40a976e871988 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -179,6 +179,7 @@ ; CHECK-NEXT: svpbmt - 'Svpbmt' (Page-Based Memory Types). ; CHECK-NEXT: svvptc - 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid). ; CHECK-NEXT: tagged-globals - Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits. +; CHECK-NEXT: throttled-vec-fp64 - Certain vector FP64 operations have limited performance. ; CHECK-NEXT: unaligned-scalar-mem - Has reasonably performant unaligned scalar loads and stores. ; CHECK-NEXT: unaligned-vector-mem - Has reasonably performant unaligned vector loads and stores. ; CHECK-NEXT: use-postra-scheduler - Schedule again after register allocation. From da837f3dc34f2c3af938ba05564e53888035ee87 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Wed, 8 Oct 2025 09:58:28 -0700 Subject: [PATCH 2/2] fixup! Rename to `TuneHasSingleElementVecFP64` --- llvm/lib/Target/RISCV/RISCVFeatures.td | 7 ++++--- llvm/test/CodeGen/RISCV/features-info.ll | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 0d3df0e188505..ac7125a05d262 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1823,9 +1823,10 @@ def TuneConditionalCompressedMoveFusion def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">; def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">; -def TuneHasThrottledVecFP64 - : SubtargetFeature<"throttled-vec-fp64", "HasThrottledVectorFP64", "true", - "Certain vector FP64 operations have limited performance">; +def TuneHasSingleElementVecFP64 + : SubtargetFeature<"single-element-vec-fp64", "HasSingleElementVectorFP64", "true", + "Certain vector FP64 operations produce a single result " + "element per cycle">; def TuneMIPSP8700 : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700", diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 40a976e871988..693a40d3f39e6 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -142,6 +142,7 @@ ; CHECK-NEXT: shvstvecd - 'Shvstvecd' (vstvec supports Direct mode). ; CHECK-NEXT: shxadd-load-fusion - Enable SH(1|2|3)ADD(.UW) + load macrofusion. ; CHECK-NEXT: sifive7 - SiFive 7-Series processors. +; CHECK-NEXT: single-element-vec-fp64 - Certain vector FP64 operations produce a single result element per cycle. ; CHECK-NEXT: smaia - 'Smaia' (Advanced Interrupt Architecture Machine Level). ; CHECK-NEXT: smcdeleg - 'Smcdeleg' (Counter Delegation Machine Level). ; CHECK-NEXT: smcntrpmf - 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering). @@ -179,7 +180,6 @@ ; CHECK-NEXT: svpbmt - 'Svpbmt' (Page-Based Memory Types). ; CHECK-NEXT: svvptc - 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid). ; CHECK-NEXT: tagged-globals - Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits. -; CHECK-NEXT: throttled-vec-fp64 - Certain vector FP64 operations have limited performance. ; CHECK-NEXT: unaligned-scalar-mem - Has reasonably performant unaligned scalar loads and stores. ; CHECK-NEXT: unaligned-vector-mem - Has reasonably performant unaligned vector loads and stores. ; CHECK-NEXT: use-postra-scheduler - Schedule again after register allocation.