From b785cb5e3215d146fe98df357e1b53f11e48e046 Mon Sep 17 00:00:00 2001 From: Harsh Chandel Date: Fri, 3 Oct 2025 15:52:35 +0530 Subject: [PATCH 1/2] Prioritize Xqcics over Xqcicli Change-Id: I87702585a78545470b9cfd0325a7d7efb0750396 --- llvm/lib/Target/RISCV/RISCVFeatures.td | 2 ++ llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 23 ++++++++++++++------- 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index a02de31d1cc4d..d80cb2f4aa18c 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1520,6 +1520,8 @@ def HasVendorXqcics : Predicate<"Subtarget->hasVendorXqcics()">, AssemblerPredicate<(all_of FeatureVendorXqcics), "'Xqcics' (Qualcomm uC Conditional Select Extension)">; +def NoVendorXqcics + : Predicate<"!Subtarget->hasVendorXqcics()">; def FeatureVendorXqcicsr : RISCVExperimentalExtension<0, 4, "Qualcomm uC CSR Extension">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index efdbd1298aec6..c1e1c5d8fa683 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -1571,35 +1571,42 @@ def : QCIMVCCIPat; } let Predicates = [HasVendorXqcicli, IsRV32] in { -def : QCILICCPat; -def : QCILICCPat; def : QCILICCPat; def : QCILICCPat; def : QCILICCPat; def : QCILICCPat; -def : QCILICCIPat; -def : QCILICCIPat; def : QCILICCIPat; def : QCILICCIPat; def : QCILICCIPat; def : QCILICCIPat; -def : QCILICCPatInv; -def : QCILICCPatInv; def : QCILICCPatInv; def : QCILICCPatInv; def : QCILICCPatInv; def : QCILICCPatInv; -def : QCILICCIPatInv; -def : QCILICCIPatInv; def : QCILICCIPatInv; def : QCILICCIPatInv; def : QCILICCIPatInv; def : QCILICCIPatInv; } // Predicates = [HasVendorXqcicli, IsRV32] +// Prioritize Xqcics over these patterns. +let Predicates = [HasVendorXqcicli, NoVendorXqcics, IsRV32] in { +def : QCILICCPat; +def : QCILICCPat; + +def : QCILICCIPat; +def : QCILICCIPat; + +def : QCILICCPatInv; +def : QCILICCPatInv; + +def : QCILICCIPatInv; +def : QCILICCIPatInv; +} // Predicates = [HasVendorXqcicli, NoVendorXqcics, IsRV32] + let Predicates = [HasVendorXqcics, IsRV32] in { // (SELECT X, Y, Z) is canonicalised to `(riscv_selectcc x, 0, NE, y, z)`. // These exist to prioritise over the `Select_GPR_Using_CC_GPR` pattern. From d2671ac3b02767ab93a29b1d164b62eb7258191f Mon Sep 17 00:00:00 2001 From: Harsh Chandel Date: Tue, 7 Oct 2025 10:29:40 +0530 Subject: [PATCH 2/2] Update tests Change-Id: I819f038f8434f713d42943a23e1f8b8853d690cb --- llvm/test/CodeGen/RISCV/cmov-branch-opt.ll | 5 +-- llvm/test/CodeGen/RISCV/xqcicli.ll | 36 ++++++++++++------- llvm/test/CodeGen/RISCV/xqcics.ll | 42 ++++++++-------------- 3 files changed, 41 insertions(+), 42 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll b/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll index edec1d0b649ce..1957019f055a2 100644 --- a/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll +++ b/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll @@ -201,8 +201,9 @@ define signext i32 @test4(i32 signext %x, i32 signext %y, i32 signext %z) { ; ; RV32IXQCI-LABEL: test4: ; RV32IXQCI: # %bb.0: -; RV32IXQCI-NEXT: li a0, 0 -; RV32IXQCI-NEXT: qc.lieqi a0, a2, 0, 3 +; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: li a1, 3 +; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 0 ; RV32IXQCI-NEXT: ret %c = icmp eq i32 %z, 0 %a = select i1 %c, i32 3, i32 0 diff --git a/llvm/test/CodeGen/RISCV/xqcicli.ll b/llvm/test/CodeGen/RISCV/xqcicli.ll index 8d4caa177513b..cdb1947339736 100644 --- a/llvm/test/CodeGen/RISCV/xqcicli.ll +++ b/llvm/test/CodeGen/RISCV/xqcicli.ll @@ -23,7 +23,8 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_eq: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieq a0, a1, a2, 11 +; RV32IXQCI-NEXT: qc.selectine a1, a2, a0, 11 +; RV32IXQCI-NEXT: mv a0, a1 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 %b, %x @@ -47,7 +48,8 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_ne: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.line a0, a1, a2, 11 +; RV32IXQCI-NEXT: qc.selectieq a1, a2, a0, 11 +; RV32IXQCI-NEXT: mv a0, a1 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 %b, %x @@ -167,7 +169,8 @@ define i32 @select_cc_example_eq_c(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_eq_c: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.line a0, a1, a2, 11 +; RV32IXQCI-NEXT: qc.selectieq a1, a2, a0, 11 +; RV32IXQCI-NEXT: mv a0, a1 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 %b, %x @@ -191,7 +194,8 @@ define i32 @select_cc_example_ne_c(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_ne_c: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieq a0, a1, a2, 11 +; RV32IXQCI-NEXT: qc.selectine a1, a2, a0, 11 +; RV32IXQCI-NEXT: mv a0, a1 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 %b, %x @@ -312,7 +316,8 @@ define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_eqi: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11 +; RV32IXQCI-NEXT: qc.selectinei a1, 12, a0, 11 +; RV32IXQCI-NEXT: mv a0, a1 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 %b, 12 @@ -337,7 +342,8 @@ define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_nei: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11 +; RV32IXQCI-NEXT: qc.selectieqi a1, 12, a0, 11 +; RV32IXQCI-NEXT: mv a0, a1 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 %b, 12 @@ -462,7 +468,8 @@ define i32 @select_cc_example_eqi_c1(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_eqi_c1: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11 +; RV32IXQCI-NEXT: qc.selectinei a1, 12, a0, 11 +; RV32IXQCI-NEXT: mv a0, a1 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 12, %b @@ -487,7 +494,8 @@ define i32 @select_cc_example_nei_c1(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_nei_c1: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11 +; RV32IXQCI-NEXT: qc.selectieqi a1, 12, a0, 11 +; RV32IXQCI-NEXT: mv a0, a1 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 12, %b @@ -612,7 +620,8 @@ define i32 @select_cc_example_eqi_c2(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_eqi_c2: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11 +; RV32IXQCI-NEXT: qc.selectieqi a1, 12, a0, 11 +; RV32IXQCI-NEXT: mv a0, a1 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 12, %b @@ -637,7 +646,8 @@ define i32 @select_cc_example_nei_c2(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_nei_c2: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11 +; RV32IXQCI-NEXT: qc.selectinei a1, 12, a0, 11 +; RV32IXQCI-NEXT: mv a0, a1 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 12, %b @@ -762,7 +772,8 @@ define i32 @select_cc_example_eqi_c3(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_eqi_c3: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11 +; RV32IXQCI-NEXT: qc.selectieqi a1, 12, a0, 11 +; RV32IXQCI-NEXT: mv a0, a1 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 %b, 12 @@ -787,7 +798,8 @@ define i32 @select_cc_example_nei_c3(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_nei_c3: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11 +; RV32IXQCI-NEXT: qc.selectinei a1, 12, a0, 11 +; RV32IXQCI-NEXT: mv a0, a1 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 %b, 12 diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll index c0839c98c1348..7656a0c0e78e0 100644 --- a/llvm/test/CodeGen/RISCV/xqcics.ll +++ b/llvm/test/CodeGen/RISCV/xqcics.ll @@ -270,8 +270,7 @@ define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_eqi: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.line a2, a0, a1, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectieq a0, a1, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 %a, %b @@ -301,8 +300,7 @@ define i32 @select_cc_example_eqi_c(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_eqi_c: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieq a2, a0, a1, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectine a0, a1, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 %a, %b @@ -332,8 +330,7 @@ define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_nei: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieq a2, a0, a1, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectine a0, a1, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 %a, %b @@ -363,8 +360,7 @@ define i32 @select_cc_example_nei_c(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_nei_c: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.line a2, a0, a1, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectieq a0, a1, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 %a, %b @@ -395,8 +391,7 @@ define i32 @select_cc_example_ieqi(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_ieqi: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectieqi a0, 12, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 %a, 12 @@ -427,8 +422,7 @@ define i32 @select_cc_example_ieqi_c1(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_ieqi_c1: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectieqi a0, 12, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 12, %a @@ -459,8 +453,7 @@ define i32 @select_cc_example_ieqi_c2(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_ieqi_c2: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectinei a0, 12, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 %a, 12 @@ -491,8 +484,7 @@ define i32 @select_cc_example_ieqi_c3(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_ieqi_c3: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectinei a0, 12, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 12, %a @@ -523,8 +515,7 @@ define i32 @select_cc_example_inei(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_inei: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectinei a0, 12, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 %a, 12 @@ -555,8 +546,7 @@ define i32 @select_cc_example_inei_c1(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_inei_c1: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectinei a0, 12, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 12, %a @@ -587,8 +577,7 @@ define i32 @select_cc_example_inei_c2(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_inei_c2: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectieqi a0, 12, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 %a, 12 @@ -619,8 +608,7 @@ define i32 @select_cc_example_inei_c3(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_inei_c3: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectieqi a0, 12, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 12, %a @@ -712,8 +700,7 @@ define i32 @select_cc_example_eq1(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_eq1: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.line a2, a1, a0, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectieq a0, a1, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp eq i32 %b, %a @@ -743,8 +730,7 @@ define i32 @select_cc_example_ne1(i32 %a, i32 %b, i32 %x, i32 %y) { ; ; RV32IXQCI-LABEL: select_cc_example_ne1: ; RV32IXQCI: # %bb.0: # %entry -; RV32IXQCI-NEXT: qc.lieq a2, a1, a0, 11 -; RV32IXQCI-NEXT: mv a0, a2 +; RV32IXQCI-NEXT: qc.selectine a0, a1, a2, 11 ; RV32IXQCI-NEXT: ret entry: %cmp = icmp ne i32 %b, %a