From 0a1f745c40d8a32f4dc43658bd571782b17d3ffc Mon Sep 17 00:00:00 2001 From: Carlo Bertolli Date: Mon, 13 Oct 2025 13:24:22 -0500 Subject: [PATCH 1/2] Enable saving SHARED_BASE to VCC. This is observed when exhausting scalar registers in kernels with high register usage. --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 3 ++- llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir | 9 +++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index ec5c5bb349ac4..86a60e5a6242b 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -899,7 +899,8 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } if (DestReg == AMDGPU::VCC) { - if (AMDGPU::SReg_64RegClass.contains(SrcReg)) { + if (AMDGPU::SReg_64RegClass.contains(SrcReg) || + AMDGPU::SReg_64_EncodableRegClass.contains(SrcReg)) { BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC) .addReg(SrcReg, getKillRegState(KillSrc)); } else { diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir b/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir index 9553fcc1c51c8..f11fe4aa6e00e 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir @@ -58,6 +58,15 @@ body: | $sgpr0_sgpr1 = COPY $src_shared_base ... +--- +name: src_shared_base_to_vcc +body: | + bb.0: + ; GFX9-LABEL: name: src_shared_base_to_vcc + ; GFX9: $vcc = S_MOV_B64 $src_shared_base + $vcc = COPY $src_shared_base +... + --- name: sgpr96_aligned_src_dst body: | From 06ca6797be5b08ad3739ec0f2b191113091eea2a Mon Sep 17 00:00:00 2001 From: carlobertolli Date: Mon, 13 Oct 2025 14:16:20 -0500 Subject: [PATCH 2/2] Update llvm/lib/Target/AMDGPU/SIInstrInfo.cpp SReg_64 is part of SReg_64_EncodableRegClass. Co-authored-by: Stanislav Mekhanoshin --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 86a60e5a6242b..a44a247184ea5 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -899,8 +899,7 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } if (DestReg == AMDGPU::VCC) { - if (AMDGPU::SReg_64RegClass.contains(SrcReg) || - AMDGPU::SReg_64_EncodableRegClass.contains(SrcReg)) { + if (AMDGPU::SReg_64_EncodableRegClass.contains(SrcReg)) { BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC) .addReg(SrcReg, getKillRegState(KillSrc)); } else {