From 00d3cb8466aef10b48b4cc8a3f88da5f262d4057 Mon Sep 17 00:00:00 2001 From: Antoni Zwolski Date: Tue, 14 Oct 2025 11:24:27 +0200 Subject: [PATCH 1/3] [X86] Add and_cond function with conditional logic for masked store --- llvm/test/CodeGen/X86/apx/cf.ll | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/llvm/test/CodeGen/X86/apx/cf.ll b/llvm/test/CodeGen/X86/apx/cf.ll index b2651e91134ee..4cce2226a91fb 100644 --- a/llvm/test/CodeGen/X86/apx/cf.ll +++ b/llvm/test/CodeGen/X86/apx/cf.ll @@ -230,6 +230,24 @@ entry: ret void } +define void @and_cond(i32 %a, i1 %b) { +; CHECK-LABEL: and_cond: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: testl %edi, %edi +; CHECK-NEXT: setg %al +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: testb %al, %sil +; CHECK-NEXT: cfcmovel %ecx, 0 +; CHECK-NEXT: retq +entry: + %0 = icmp sgt i32 %a, 0 + %1 = xor i1 %b, true + %3 = and i1 %1, %0 + %4 = insertelement <1 x i1> zeroinitializer, i1 %3, i64 0 + call void @llvm.masked.store.v1i32.p0(<1 x i32> zeroinitializer, ptr null, i32 1, <1 x i1> %4) + ret void +} + define i64 @redundant_test(i64 %num, ptr %p1, i64 %in) { ; CHECK-LABEL: redundant_test: ; CHECK: # %bb.0: From 42a27c7b8efec990d2e0f04afc2322c4a8076f53 Mon Sep 17 00:00:00 2001 From: Antoni Zwolski Date: Tue, 14 Oct 2025 11:46:15 +0200 Subject: [PATCH 2/3] [X86] Update conditional logic in cload/cstore and update cf.ll tests --- llvm/lib/Target/X86/X86ISelLowering.cpp | 7 ++++--- llvm/test/CodeGen/X86/apx/cf.ll | 3 ++- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index eea84a2841764..dabd898819e26 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -58332,11 +58332,12 @@ static SDValue combineX86CloadCstore(SDNode *N, SelectionDAG &DAG) { } else if (Op1.getOpcode() == ISD::AND && Sub.getValue(0).use_empty()) { SDValue Src = Op1; SDValue Op10 = Op1.getOperand(0); - if (Op10.getOpcode() == ISD::XOR && isAllOnesConstant(Op10.getOperand(1))) { - // res, flags2 = sub 0, (and (xor X, -1), Y) + if (Op10.getOpcode() == ISD::XOR && isAllOnesConstant(Op10.getOperand(1)) && + llvm::isOneConstant(Op1.getOperand(1))) { + // res, flags2 = sub 0, (and (xor X, -1), 1) // cload/cstore ..., cond_ne, flag2 // -> - // res, flags2 = sub 0, (and X, Y) + // res, flags2 = sub 0, (and X, 1) // cload/cstore ..., cond_e, flag2 Src = DAG.getNode(ISD::AND, DL, Op1.getValueType(), Op10.getOperand(0), Op1.getOperand(1)); diff --git a/llvm/test/CodeGen/X86/apx/cf.ll b/llvm/test/CodeGen/X86/apx/cf.ll index 4cce2226a91fb..4c689d9d0a7a9 100644 --- a/llvm/test/CodeGen/X86/apx/cf.ll +++ b/llvm/test/CodeGen/X86/apx/cf.ll @@ -235,9 +235,10 @@ define void @and_cond(i32 %a, i1 %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testl %edi, %edi ; CHECK-NEXT: setg %al +; CHECK-NEXT: notb %sil ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: testb %al, %sil -; CHECK-NEXT: cfcmovel %ecx, 0 +; CHECK-NEXT: cfcmovnel %ecx, 0 ; CHECK-NEXT: retq entry: %0 = icmp sgt i32 %a, 0 From 756216076e92d663124978c6c03895e447648b31 Mon Sep 17 00:00:00 2001 From: Antoni Zwolski Date: Tue, 14 Oct 2025 23:32:56 +0200 Subject: [PATCH 3/3] [X86] Improve naming in and_cond test --- llvm/test/CodeGen/X86/apx/cf.ll | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/llvm/test/CodeGen/X86/apx/cf.ll b/llvm/test/CodeGen/X86/apx/cf.ll index 4c689d9d0a7a9..de9caa5b6d989 100644 --- a/llvm/test/CodeGen/X86/apx/cf.ll +++ b/llvm/test/CodeGen/X86/apx/cf.ll @@ -232,7 +232,7 @@ entry: define void @and_cond(i32 %a, i1 %b) { ; CHECK-LABEL: and_cond: -; CHECK: # %bb.0: # %entry +; CHECK: # %bb.0: ; CHECK-NEXT: testl %edi, %edi ; CHECK-NEXT: setg %al ; CHECK-NEXT: notb %sil @@ -240,12 +240,11 @@ define void @and_cond(i32 %a, i1 %b) { ; CHECK-NEXT: testb %al, %sil ; CHECK-NEXT: cfcmovnel %ecx, 0 ; CHECK-NEXT: retq -entry: - %0 = icmp sgt i32 %a, 0 - %1 = xor i1 %b, true - %3 = and i1 %1, %0 - %4 = insertelement <1 x i1> zeroinitializer, i1 %3, i64 0 - call void @llvm.masked.store.v1i32.p0(<1 x i32> zeroinitializer, ptr null, i32 1, <1 x i1> %4) + %is_pos = icmp sgt i32 %a, 0 + %not_b = xor i1 %b, true + %cond = and i1 %not_b, %is_pos + %mask = insertelement <1 x i1> zeroinitializer, i1 %cond, i64 0 + call void @llvm.masked.store.v1i32.p0(<1 x i32> zeroinitializer, ptr null, i32 1, <1 x i1> %mask) ret void }