From e14684fc90ec5ef5ea1f8b362a6bdb83a43607bc Mon Sep 17 00:00:00 2001 From: quic-areg Date: Wed, 15 Oct 2025 14:25:34 -0700 Subject: [PATCH 1/2] [Hexagon] Define V91 ISA and Processor versions in ELF flags These versions are not supported by upstream LLVM but are needed to add support in the eld linker. --- llvm/include/llvm/BinaryFormat/ELF.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/include/llvm/BinaryFormat/ELF.h b/llvm/include/llvm/BinaryFormat/ELF.h index e619b186dfe3d..8d0dc64199ebf 100644 --- a/llvm/include/llvm/BinaryFormat/ELF.h +++ b/llvm/include/llvm/BinaryFormat/ELF.h @@ -647,6 +647,7 @@ enum { EF_HEXAGON_ISA_V85 = 0x00000085, // Hexagon V85 ISA EF_HEXAGON_ISA_V87 = 0x00000087, // Hexagon V87 ISA EF_HEXAGON_ISA_V89 = 0x00000089, // Hexagon V89 ISA + EF_HEXAGON_ISA_V91 = 0x00000091, // Hexagon V91 ISA EF_HEXAGON_ISA = 0x000003ff, // Hexagon V.. ISA // Tiny core flag, bit[15] @@ -680,6 +681,7 @@ enum { EF_HEXAGON_MACH_V85 = EF_HEXAGON_ISA_V85, // Hexagon V85 EF_HEXAGON_MACH_V87 = EF_HEXAGON_ISA_V87, // Hexagon V87 EF_HEXAGON_MACH_V89 = EF_HEXAGON_ISA_V89, // Hexagon V89 + EF_HEXAGON_MACH_V91 = EF_HEXAGON_ISA_V91, // Hexagon V91 EF_HEXAGON_MACH = 0x0000ffff, // Hexagon V.. }; From cd773355299b77493eede3c7acd82886152c4c38 Mon Sep 17 00:00:00 2001 From: quic-areg Date: Thu, 16 Oct 2025 11:19:36 -0700 Subject: [PATCH 2/2] update ELFYaml for V91 --- llvm/lib/ObjectYAML/ELFYAML.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/ObjectYAML/ELFYAML.cpp b/llvm/lib/ObjectYAML/ELFYAML.cpp index 68c8ff5b4eb87..c3a27c9326790 100644 --- a/llvm/lib/ObjectYAML/ELFYAML.cpp +++ b/llvm/lib/ObjectYAML/ELFYAML.cpp @@ -507,6 +507,7 @@ void ScalarBitSetTraits::bitset(IO &IO, BCaseMask(EF_HEXAGON_MACH_V85, EF_HEXAGON_MACH); BCaseMask(EF_HEXAGON_MACH_V87, EF_HEXAGON_MACH); BCaseMask(EF_HEXAGON_MACH_V89, EF_HEXAGON_MACH); + BCaseMask(EF_HEXAGON_MACH_V91, EF_HEXAGON_MACH); BCaseMask(EF_HEXAGON_ISA_V2, EF_HEXAGON_ISA); BCaseMask(EF_HEXAGON_ISA_V3, EF_HEXAGON_ISA); BCaseMask(EF_HEXAGON_ISA_V4, EF_HEXAGON_ISA); @@ -530,6 +531,7 @@ void ScalarBitSetTraits::bitset(IO &IO, BCaseMask(EF_HEXAGON_ISA_V85, EF_HEXAGON_ISA); BCaseMask(EF_HEXAGON_ISA_V87, EF_HEXAGON_ISA); BCaseMask(EF_HEXAGON_ISA_V89, EF_HEXAGON_ISA); + BCaseMask(EF_HEXAGON_ISA_V91, EF_HEXAGON_ISA); break; case ELF::EM_AVR: BCaseMask(EF_AVR_ARCH_AVR1, EF_AVR_ARCH_MASK);