From 05357a7bfdfc6542484ec781252731e83d34733a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 18 Oct 2025 10:51:35 -0700 Subject: [PATCH] [RISCV] Remove duplicate Zvfbfmin patterns that use base Zve instructions. These patterns already exist in our other V extension files using AllFloatAndBF16Vectors without Zvfbfmin predicate. Which is good because we need them for Zvfbfa. --- llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td | 54 -------------------- 1 file changed, 54 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td index 9358486c13da2..45e97800ce3ab 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td @@ -439,20 +439,7 @@ let Predicates = [HasStdExtZvfbfmin] in { fvti.AVL, fvti.Log2SEW, TA_MA)>; } - defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllBF16Vectors>; - defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER", - AllBF16Vectors, uimm5>; - defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16", - eew=16, vtilist=AllBF16Vectors>; - defm : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllBF16Vectors, uimm5>; - defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllBF16Vectors, uimm5>; - foreach fvti = AllBF16Vectors in { - defm : VPatBinaryCarryInTAIL<"int_riscv_vmerge", "PseudoVMERGE", "VVM", - fvti.Vector, - fvti.Vector, fvti.Vector, fvti.Mask, - fvti.Log2SEW, fvti.LMul, fvti.RegClass, - fvti.RegClass, fvti.RegClass>; defm : VPatBinaryCarryInTAIL<"int_riscv_vfmerge", "PseudoVFMERGE", "V"#fvti.ScalarSuffix#"M", fvti.Vector, @@ -468,12 +455,6 @@ let Predicates = [HasStdExtZvfbfmin] in { (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW)>; defvar ivti = GetIntVTypeInfo.Vti; - def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm), fvti.RegClass:$rs1, - fvti.RegClass:$rs2)), - (!cast("PseudoVMERGE_VVM_"#fvti.LMul.MX) - (fvti.Vector (IMPLICIT_DEF)), - fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask VMV0:$vm), - fvti.AVL, fvti.Log2SEW)>; def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm), (SplatFPOp (SelectScalarFPAsInt (XLenVT GPR:$imm))), @@ -498,15 +479,6 @@ let Predicates = [HasStdExtZvfbfmin] in { (fvti.Scalar fvti.ScalarRegClass:$rs1), (fvti.Mask VMV0:$vm), fvti.AVL, fvti.Log2SEW)>; - def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm), - fvti.RegClass:$rs1, - fvti.RegClass:$rs2, - fvti.RegClass:$passthru, - VLOpFrag)), - (!cast("PseudoVMERGE_VVM_"#fvti.LMul.MX) - fvti.RegClass:$passthru, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask VMV0:$vm), - GPR:$vl, fvti.Log2SEW)>; - def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm), (SplatFPOp (SelectScalarFPAsInt (XLenVT GPR:$imm))), fvti.RegClass:$rs2, @@ -535,32 +507,6 @@ let Predicates = [HasStdExtZvfbfmin] in { fvti.RegClass:$passthru, fvti.RegClass:$rs2, (fvti.Scalar fvti.ScalarRegClass:$rs1), (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW)>; - - def : Pat<(fvti.Vector - (riscv_vrgather_vv_vl fvti.RegClass:$rs2, - (ivti.Vector fvti.RegClass:$rs1), - fvti.RegClass:$passthru, - (fvti.Mask VMV0:$vm), - VLOpFrag)), - (!cast("PseudoVRGATHER_VV_"# fvti.LMul.MX#"_E"# fvti.SEW#"_MASK") - fvti.RegClass:$passthru, fvti.RegClass:$rs2, fvti.RegClass:$rs1, - (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fvti.Vector (riscv_vrgather_vx_vl fvti.RegClass:$rs2, GPR:$rs1, - fvti.RegClass:$passthru, - (fvti.Mask VMV0:$vm), - VLOpFrag)), - (!cast("PseudoVRGATHER_VX_"# fvti.LMul.MX#"_MASK") - fvti.RegClass:$passthru, fvti.RegClass:$rs2, GPR:$rs1, - (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fvti.Vector - (riscv_vrgather_vx_vl fvti.RegClass:$rs2, - uimm5:$imm, - fvti.RegClass:$passthru, - (fvti.Mask VMV0:$vm), - VLOpFrag)), - (!cast("PseudoVRGATHER_VI_"# fvti.LMul.MX#"_MASK") - fvti.RegClass:$passthru, fvti.RegClass:$rs2, uimm5:$imm, - (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; } }