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8 changes: 8 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -845,6 +845,14 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
}

if (AMDGPU::APERTURE_ClassRegClass.contains(DestReg)) {
if (SrcReg == AMDGPU::VCC) {
BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
}
}

if (RC == &AMDGPU::VGPR_32RegClass) {
assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
AMDGPU::SReg_32RegClass.contains(SrcReg) ||
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9 changes: 9 additions & 0 deletions llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,15 @@ body: |
$vcc = COPY $src_shared_base
...

---
name: vcc_to_src_shared_base
body: |
bb.0:
; GFX9-LABEL: name: vcc_to_src_shared_base
; GFX9: $src_shared_base = S_MOV_B64 $vcc
$src_shared_base = COPY $vcc
...

---
name: sgpr96_aligned_src_dst
body: |
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