From a6dadd0fa94ab1db6cabd3b0f4068d210e42e8c8 Mon Sep 17 00:00:00 2001 From: jiang1997 Date: Tue, 21 Oct 2025 05:38:37 +0800 Subject: [PATCH] [X86] Remove LOW32_ADDR_ACCESS_RBP RegisterClass The FIXME comment appears to be outdated. Deleting the register class has no observable impact on code generation in the current codebase. Fixes #155430 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 3 +-- llvm/lib/Target/X86/X86RegisterInfo.td | 4 ---- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index d49f25a950e3a..4bd26a2216ba1 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -61643,8 +61643,7 @@ static bool isGRClass(const TargetRegisterClass &RC) { return RC.hasSuperClassEq(&X86::GR8RegClass) || RC.hasSuperClassEq(&X86::GR16RegClass) || RC.hasSuperClassEq(&X86::GR32RegClass) || - RC.hasSuperClassEq(&X86::GR64RegClass) || - RC.hasSuperClassEq(&X86::LOW32_ADDR_ACCESS_RBPRegClass); + RC.hasSuperClassEq(&X86::GR64RegClass); } /// Check if \p RC is a vector register class. diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index 99b7910131dc5..1c58b31700b75 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -716,10 +716,6 @@ def GR64_NOREX2_NOSP : RegisterClass<"X86", [i64], 64, // which we do not have right now. def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; -// FIXME: This is unused, but deleting it results in codegen changes -def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32, - (add LOW32_ADDR_ACCESS, RBP)>; - // A class to support the 'A' assembler constraint: [ER]AX then [ER]DX. def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;