From 6397d2ed1394f094c068aba9015b5bcd2bf01e04 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Fri, 24 Oct 2025 14:26:58 +0800 Subject: [PATCH] [VPlan] Explicitly predicate some replicate region sinking tests. NFC --- ...-order-recurrence-sink-replicate-region.ll | 25 +++++++++++++------ .../vplan-sink-scalars-and-merge.ll | 17 ++++++++++--- 2 files changed, 30 insertions(+), 12 deletions(-) diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll index 9deab9063d710..fe230fa6c9090 100644 --- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll +++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll @@ -102,7 +102,7 @@ exit: ret void } -define void @sink_replicate_region_2(i32 %x, i8 %y, ptr %ptr) optsize { +define void @sink_replicate_region_2(i32 %x, i8 %y, ptr %ptr, i32 %z) optsize { ; CHECK-LABEL: sink_replicate_region_2 ; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { ; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF @@ -125,16 +125,18 @@ define void @sink_replicate_region_2(i32 %x, i8 %y, ptr %ptr) optsize { ; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]> ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]> ; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur>, ir<%recur.next> +; CHECK-NEXT: WIDEN ir<%cond> = icmp eq ir<%iv>, ir<%z> +; CHECK-NEXT: EMIT vp<[[AND:%.+]]> = logical-and vp<[[MASK]]>, ir<%cond> ; CHECK-NEXT: Successor(s): pred.store ; CHECK-EMPTY: ; CHECK-NEXT: pred.store: { ; CHECK-NEXT: pred.store.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> +; CHECK-NEXT: BRANCH-ON-MASK vp<[[AND]]> ; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue ; CHECK-EMPTY: ; CHECK-NEXT: pred.store.if: -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> ; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> +; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> ; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEPS]]> ; CHECK-NEXT: REPLICATE ir<%add> = add ir<%rem>, ir<%recur.next> ; CHECK-NEXT: REPLICATE store ir<%add>, ir<%gep> @@ -143,9 +145,9 @@ define void @sink_replicate_region_2(i32 %x, i8 %y, ptr %ptr) optsize { ; CHECK-NEXT: pred.store.continue: ; CHECK-NEXT: No successors ; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): loop.0 +; CHECK-NEXT: Successor(s): if.1 ; CHECK-EMPTY: -; CHECK-NEXT: loop.0: +; CHECK-NEXT: if.1: ; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> ; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]> ; CHECK-NEXT: No successors @@ -162,13 +164,20 @@ entry: br label %loop loop: - %recur = phi i32 [ 0, %entry ], [ %recur.next, %loop ] - %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] - %rem = srem i32 %recur, %x + %recur = phi i32 [ 0, %entry ], [ %recur.next, %latch ] + %iv = phi i32 [ 0, %entry ], [ %iv.next, %latch ] %recur.next = sext i8 %y to i32 + %cond = icmp eq i32 %iv, %z + br i1 %cond, label %if, label %latch + +if: + %rem = srem i32 %recur, %x %add = add i32 %rem, %recur.next %gep = getelementptr i32, ptr %ptr, i32 %iv store i32 %add, ptr %gep + br label %latch + +latch: %iv.next = add nsw i32 %iv, 1 %ec = icmp eq i32 %iv.next, 20001 br i1 %ec, label %exit, label %loop diff --git a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll index 994e9c1ce64fa..2dd6a04ee7d4a 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll @@ -29,11 +29,13 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]> ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]> +; CHECK-NEXT: WIDEN ir<%cond> = icmp eq ir<%iv>, ir<%x> +; CHECK-NEXT: EMIT vp<[[AND:%.+]]> = logical-and vp<[[MASK]]>, ir<%cond> ; CHECK-NEXT: Successor(s): pred.store ; CHECK: pred.store: { ; CHECK-NEXT: pred.store.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> +; CHECK-NEXT: BRANCH-ON-MASK vp<[[AND]]> ; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue ; CHECK: pred.store.if: @@ -50,24 +52,31 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 ; CHECK-NEXT: No successors ; CHECK-NEXT: } -; CHECK: loop.1: +; CHECK: if.1: ; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> ; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]> ; CHECK-NEXT: No successors ; CHECK-NEXT: } ; -define void @sink1(i32 %k) { +define void @sink1(i32 %k, i32 %x) { entry: br label %loop loop: - %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] + %iv = phi i32 [ 0, %entry ], [ %iv.next, %latch ] + %cond = icmp eq i32 %iv, %x + br i1 %cond, label %if, label %latch + +if: %gep.b = getelementptr inbounds [2048 x i32], ptr @b, i32 0, i32 %iv %lv.b = load i32, ptr %gep.b, align 4 %add = add i32 %lv.b, 10 %mul = mul i32 2, %add %gep.a = getelementptr inbounds [2048 x i32], ptr @a, i32 0, i32 %iv store i32 %mul, ptr %gep.a, align 4 + br label %latch + +latch: %iv.next = add i32 %iv, 1 %large = icmp sge i32 %iv, 8 %exitcond = icmp eq i32 %iv, %k