diff --git a/llvm/lib/Target/X86/GISel/X86CallLowering.cpp b/llvm/lib/Target/X86/GISel/X86CallLowering.cpp
index c0b9339e9bc34..b07ce2b958fa0 100644
--- a/llvm/lib/Target/X86/GISel/X86CallLowering.cpp
+++ b/llvm/lib/Target/X86/GISel/X86CallLowering.cpp
@@ -280,8 +280,7 @@ bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
     if (Arg.hasAttribute(Attribute::ByVal) ||
         Arg.hasAttribute(Attribute::InReg) ||
         Arg.hasAttribute(Attribute::SwiftSelf) ||
-        Arg.hasAttribute(Attribute::SwiftError) ||
-        Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1)
+        Arg.hasAttribute(Attribute::SwiftError) || VRegs[Idx].size() > 1)
       return false;
 
     if (Arg.hasAttribute(Attribute::StructRet)) {
diff --git a/llvm/test/CodeGen/X86/isel-arg-attrs.ll b/llvm/test/CodeGen/X86/isel-arg-attrs.ll
new file mode 100644
index 0000000000000..3afee76715d6d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/isel-arg-attrs.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=i686-linux-gnu | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=i686-linux-gnu -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=X64
+
+; The src array should be in R10 or ECX register due to nest attribute
+define i32 @nest_arg(ptr nest %src) {
+; X86-LABEL: nest_arg:
+; X86:       # %bb.0:
+; X86-NEXT:    movl 8(%ecx), %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: nest_arg:
+; X64:       # %bb.0:
+; X64-NEXT:    movl 8(%r10), %eax
+; X64-NEXT:    retq
+  %off = getelementptr [3 x i32], ptr %src, i32 0, i32 2
+  %ret = load i32, ptr %off
+  ret i32 %ret
+}