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[BOLT][BTI] Add MCPlusBuilder::createBTI #167305

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[BOLT][BTI] Add MCPlusBuilder::createBTI #167305

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5 changes: 5 additions & 0 deletions bolt/include/bolt/Core/MCPlusBuilder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1865,6 +1865,11 @@ class MCPlusBuilder {
llvm_unreachable("not implemented");
}

/// Create a BTI landing pad instruction.
virtual void createBTI(MCInst &Inst, bool CouldCall, bool CouldJump) const {
llvm_unreachable("not implemented");
}

/// Store \p Target absolute address to \p RegName
virtual InstructionListType materializeAddress(const MCSymbol *Target,
MCContext *Ctx,
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6 changes: 6 additions & 0 deletions bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
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Expand Up @@ -2706,6 +2706,12 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
return Insts;
}

void createBTI(MCInst &Inst, bool CouldCall, bool CouldJump) const override {
Inst.setOpcode(AArch64::HINT);
unsigned HintNum = getBTIHintNum(CouldCall, CouldJump);
Inst.addOperand(MCOperand::createImm(HintNum));
}

InstructionListType materializeAddress(const MCSymbol *Target, MCContext *Ctx,
MCPhysReg RegName,
int64_t Addend = 0) const override {
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30 changes: 30 additions & 0 deletions bolt/unittests/Core/MCPlusBuilder.cpp
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Expand Up @@ -143,6 +143,36 @@ TEST_P(MCPlusBuilderTester, AArch64_CmpJE) {
ASSERT_EQ(Label, BB->getLabel());
}

TEST_P(MCPlusBuilderTester, AArch64_BTI) {
if (GetParam() != Triple::aarch64)
GTEST_SKIP();
BinaryFunction *BF = BC->createInjectedBinaryFunction("BF", true);
std::unique_ptr<BinaryBasicBlock> BB = BF->createBasicBlock();

MCInst BTIjc;
BC->MIB->createBTI(BTIjc, true, true);
BB->addInstruction(BTIjc);
auto II = BB->begin();
ASSERT_EQ(II->getOpcode(), AArch64::HINT);
ASSERT_EQ(II->getOperand(0).getImm(), 38);

MCInst BTIj;
BC->MIB->createBTI(BTIj, false, true);
II = BB->addInstruction(BTIj);
ASSERT_EQ(II->getOpcode(), AArch64::HINT);
ASSERT_EQ(II->getOperand(0).getImm(), 36);

MCInst BTIc;
BC->MIB->createBTI(BTIc, true, false);
II = BB->addInstruction(BTIc);
ASSERT_EQ(II->getOpcode(), AArch64::HINT);
ASSERT_EQ(II->getOperand(0).getImm(), 34);

MCInst BTIinvalid;
ASSERT_DEATH(BC->MIB->createBTI(BTIinvalid, false, false),
"No target kinds!");
}

TEST_P(MCPlusBuilderTester, AArch64_CmpJNE) {
if (GetParam() != Triple::aarch64)
GTEST_SKIP();
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9 changes: 2 additions & 7 deletions llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
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Expand Up @@ -18,6 +18,7 @@

#include "AArch64MachineFunctionInfo.h"
#include "AArch64Subtarget.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
Expand Down Expand Up @@ -135,13 +136,7 @@ void AArch64BranchTargets::addBTI(MachineBasicBlock &MBB, bool CouldCall,
<< (CouldCall ? "c" : "") << " to " << MBB.getName()
<< "\n");

unsigned HintNum = 32;
if (CouldCall)
HintNum |= 2;
if (CouldJump)
HintNum |= 4;
assert(HintNum != 32 && "No target kinds!");

unsigned HintNum = getBTIHintNum(CouldCall, CouldJump);
auto MBBI = MBB.begin();

// If the block starts with EH_LABEL(s), skip them first.
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10 changes: 10 additions & 0 deletions llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
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Expand Up @@ -987,6 +987,16 @@ AArch64StringToPACKeyID(StringRef Name) {
return std::nullopt;
}

inline static unsigned getBTIHintNum(bool CouldCall, bool CouldJump) {
unsigned HintNum = 32;
if (CouldCall)
HintNum |= 2;
if (CouldJump)
HintNum |= 4;
assert(HintNum != 32 && "No target kinds!");
return HintNum;
}

namespace AArch64 {
// The number of bits in a SVE register is architecturally defined
// to be a multiple of this value. If <M x t> has this number of bits,
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