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[BOLT][BTI] Add MCPlusBuilder::updateBTIVariant #167308

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[BOLT][BTI] Add MCPlusBuilder::updateBTIVariant #167308

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6 changes: 6 additions & 0 deletions bolt/include/bolt/Core/MCPlusBuilder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1884,6 +1884,12 @@ class MCPlusBuilder {
llvm_unreachable("not implemented");
}

/// Update operand of BTI instruction.
virtual void updateBTIVariant(MCInst &Inst, bool CouldCall,
bool CouldJump) const {
llvm_unreachable("not implemented");
}

/// Store \p Target absolute address to \p RegName
virtual InstructionListType materializeAddress(const MCSymbol *Target,
MCContext *Ctx,
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8 changes: 8 additions & 0 deletions bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
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Expand Up @@ -2730,6 +2730,14 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
Inst.addOperand(MCOperand::createImm(HintNum));
}

void updateBTIVariant(MCInst &Inst, bool CouldCall,
bool CouldJump) const override {
assert(Inst.getOpcode() == AArch64::HINT && "Not a BTI instruction.");
unsigned HintNum = getBTIHintNum(CouldCall, CouldJump);
Inst.clear();
Inst.addOperand(MCOperand::createImm(HintNum));
}

InstructionListType materializeAddress(const MCSymbol *Target, MCContext *Ctx,
MCPhysReg RegName,
int64_t Addend = 0) const override {
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6 changes: 6 additions & 0 deletions bolt/unittests/Core/MCPlusBuilder.cpp
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Expand Up @@ -156,20 +156,26 @@ TEST_P(MCPlusBuilderTester, AArch64_BTI) {
ASSERT_EQ(II->getOpcode(), AArch64::HINT);
ASSERT_EQ(II->getOperand(0).getImm(), 38);
ASSERT_TRUE(BC->MIB->isBTILandingPad(*II, true, true));
BC->MIB->updateBTIVariant(*II, true, false);
ASSERT_TRUE(BC->MIB->isBTILandingPad(*II, true, false));

MCInst BTIj;
BC->MIB->createBTI(BTIj, false, true);
II = BB->addInstruction(BTIj);
ASSERT_EQ(II->getOpcode(), AArch64::HINT);
ASSERT_EQ(II->getOperand(0).getImm(), 36);
ASSERT_TRUE(BC->MIB->isBTILandingPad(*II, false, true));
BC->MIB->updateBTIVariant(*II, true, true);
ASSERT_TRUE(BC->MIB->isBTILandingPad(*II, true, true));

MCInst BTIc;
BC->MIB->createBTI(BTIc, true, false);
II = BB->addInstruction(BTIc);
ASSERT_EQ(II->getOpcode(), AArch64::HINT);
ASSERT_EQ(II->getOperand(0).getImm(), 34);
ASSERT_TRUE(BC->MIB->isBTILandingPad(*II, true, false));
BC->MIB->updateBTIVariant(*II, false, true);
ASSERT_TRUE(BC->MIB->isBTILandingPad(*II, false, true));

MCInst BTIinvalid;
ASSERT_DEATH(BC->MIB->createBTI(BTIinvalid, false, false),
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