From 660d6e512ef6b977dad52d3cec65fd065a57bb35 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 11 Nov 2025 21:22:22 -0800 Subject: [PATCH] [Mips] Remove implicit conversions of MCRegister to unsigned. NFC --- .../Target/Mips/AsmParser/MipsAsmParser.cpp | 79 +++---- .../Mips/Disassembler/MipsDisassembler.cpp | 196 +++++++++--------- .../Mips/MCTargetDesc/MipsOptionRecord.cpp | 2 +- .../Mips/MCTargetDesc/MipsTargetStreamer.cpp | 54 ++--- .../Mips/MCTargetDesc/MipsTargetStreamer.h | 34 +-- llvm/lib/Target/Mips/MipsOptionRecord.h | 2 +- 6 files changed, 184 insertions(+), 183 deletions(-) diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index f588e56f2ea18..6b28531764db9 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -151,7 +151,7 @@ class MipsAsmParser : public MCTargetAsmParser { bool IsCpRestoreSet; bool CurForbiddenSlotAttr; int CpRestoreOffset; - unsigned GPReg; + MCRegister GPReg; unsigned CpSaveLocation; /// If true, then CpSaveLocation is a register, otherwise it's an offset. bool CpSaveLocationIsRegister; @@ -823,7 +823,7 @@ class MipsOperand : public MCParsedAsmOperand { }; struct RegListOp { - SmallVector *List; + SmallVector *List; }; union { @@ -1377,15 +1377,15 @@ class MipsOperand : public MCParsedAsmOperand { if (Size < 2 || Size > 5) return false; - unsigned R0 = RegList.List->front(); - unsigned R1 = RegList.List->back(); + MCRegister R0 = RegList.List->front(); + MCRegister R1 = RegList.List->back(); if (!((R0 == Mips::S0 && R1 == Mips::RA) || (R0 == Mips::S0_64 && R1 == Mips::RA_64))) return false; - int PrevReg = *RegList.List->begin(); + MCRegister PrevReg = RegList.List->front(); for (int i = 1; i < Size - 1; i++) { - int Reg = (*(RegList.List))[i]; + MCRegister Reg = (*(RegList.List))[i]; if ( Reg != PrevReg + 1) return false; PrevReg = Reg; @@ -1447,7 +1447,7 @@ class MipsOperand : public MCParsedAsmOperand { return static_cast(getMemOff())->getValue(); } - const SmallVectorImpl &getRegList() const { + const SmallVectorImpl &getRegList() const { assert((Kind == k_RegList) && "Invalid access!"); return *(RegList.List); } @@ -1548,12 +1548,13 @@ class MipsOperand : public MCParsedAsmOperand { } static std::unique_ptr - CreateRegList(SmallVectorImpl &Regs, SMLoc StartLoc, SMLoc EndLoc, + CreateRegList(SmallVectorImpl &Regs, SMLoc StartLoc, SMLoc EndLoc, MipsAsmParser &Parser) { - assert(Regs.size() > 0 && "Empty list not allowed"); + assert(!Regs.empty() && "Empty list not allowed"); auto Op = std::make_unique(k_RegList, Parser); - Op->RegList.List = new SmallVector(Regs.begin(), Regs.end()); + Op->RegList.List = + new SmallVector(Regs.begin(), Regs.end()); Op->StartLoc = StartLoc; Op->EndLoc = EndLoc; return Op; @@ -1684,7 +1685,7 @@ class MipsOperand : public MCParsedAsmOperand { case k_RegList: OS << "RegList< "; for (auto Reg : (*RegList.List)) - OS << Reg << " "; + OS << Reg.id() << " "; OS << ">"; break; } @@ -6848,9 +6849,9 @@ ParseStatus MipsAsmParser::parseInvNum(OperandVector &Operands) { ParseStatus MipsAsmParser::parseRegisterList(OperandVector &Operands) { MCAsmParser &Parser = getParser(); - SmallVector Regs; - unsigned RegNo; - unsigned PrevReg = Mips::NoRegister; + SmallVector Regs; + MCRegister Reg; + MCRegister PrevReg; bool RegRange = false; SmallVector, 8> TmpOperands; @@ -6860,46 +6861,47 @@ ParseStatus MipsAsmParser::parseRegisterList(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); while (parseAnyRegister(TmpOperands).isSuccess()) { SMLoc E = getLexer().getLoc(); - MipsOperand &Reg = static_cast(*TmpOperands.back()); - RegNo = isGP64bit() ? Reg.getGPR64Reg() : Reg.getGPR32Reg(); + MipsOperand &RegOpnd = static_cast(*TmpOperands.back()); + Reg = isGP64bit() ? RegOpnd.getGPR64Reg() : RegOpnd.getGPR32Reg(); if (RegRange) { // Remove last register operand because registers from register range // should be inserted first. - if ((isGP64bit() && RegNo == Mips::RA_64) || - (!isGP64bit() && RegNo == Mips::RA)) { - Regs.push_back(RegNo); + if ((isGP64bit() && Reg == Mips::RA_64) || + (!isGP64bit() && Reg == Mips::RA)) { + Regs.push_back(Reg); } else { - unsigned TmpReg = PrevReg + 1; - while (TmpReg <= RegNo) { + MCRegister TmpReg = PrevReg + 1; + while (TmpReg <= Reg) { if ((((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) && !isGP64bit()) || (((TmpReg < Mips::S0_64) || (TmpReg > Mips::S7_64)) && isGP64bit())) return Error(E, "invalid register operand"); PrevReg = TmpReg; - Regs.push_back(TmpReg++); + Regs.push_back(TmpReg); + TmpReg = TmpReg.id() + 1; } } RegRange = false; } else { - if ((PrevReg == Mips::NoRegister) && - ((isGP64bit() && (RegNo != Mips::S0_64) && (RegNo != Mips::RA_64)) || - (!isGP64bit() && (RegNo != Mips::S0) && (RegNo != Mips::RA)))) + if (!PrevReg.isValid() && + ((isGP64bit() && (Reg != Mips::S0_64) && (Reg != Mips::RA_64)) || + (!isGP64bit() && (Reg != Mips::S0) && (Reg != Mips::RA)))) return Error(E, "$16 or $31 expected"); - if (!(((RegNo == Mips::FP || RegNo == Mips::RA || - (RegNo >= Mips::S0 && RegNo <= Mips::S7)) && + if (!(((Reg == Mips::FP || Reg == Mips::RA || + (Reg >= Mips::S0 && Reg <= Mips::S7)) && !isGP64bit()) || - ((RegNo == Mips::FP_64 || RegNo == Mips::RA_64 || - (RegNo >= Mips::S0_64 && RegNo <= Mips::S7_64)) && + ((Reg == Mips::FP_64 || Reg == Mips::RA_64 || + (Reg >= Mips::S0_64 && Reg <= Mips::S7_64)) && isGP64bit()))) return Error(E, "invalid register operand"); - if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && - ((RegNo != Mips::FP && RegNo != Mips::RA && !isGP64bit()) || - (RegNo != Mips::FP_64 && RegNo != Mips::RA_64 && isGP64bit()))) + if (PrevReg.isValid() && (Reg != PrevReg + 1) && + ((Reg != Mips::FP && Reg != Mips::RA && !isGP64bit()) || + (Reg != Mips::FP_64 && Reg != Mips::RA_64 && isGP64bit()))) return Error(E, "consecutive register numbers expected"); - Regs.push_back(RegNo); + Regs.push_back(Reg); } if (Parser.getTok().is(AsmToken::Minus)) @@ -6913,7 +6915,7 @@ ParseStatus MipsAsmParser::parseRegisterList(OperandVector &Operands) { if (Parser.getTok().isNot(AsmToken::Dollar)) break; - PrevReg = RegNo; + PrevReg = Reg; } SMLoc E = Parser.getTok().getLoc(); @@ -7780,7 +7782,7 @@ bool MipsAsmParser::parseDirectiveCpLocal(SMLoc Loc) { } getParser().Lex(); // Consume the EndOfStatement. - unsigned NewReg = RegOpnd.getGPR32Reg(); + MCRegister NewReg = RegOpnd.getGPR32Reg(); if (IsPicEnabled) GPReg = NewReg; @@ -7835,7 +7837,6 @@ bool MipsAsmParser::parseDirectiveCpRestore(SMLoc Loc) { bool MipsAsmParser::parseDirectiveCPSetup() { MCAsmParser &Parser = getParser(); - unsigned FuncReg; unsigned Save; bool SaveIsReg = true; @@ -7852,7 +7853,7 @@ bool MipsAsmParser::parseDirectiveCPSetup() { return false; } - FuncReg = FuncRegOpnd.getGPR32Reg(); + MCRegister FuncReg = FuncRegOpnd.getGPR32Reg(); TmpReg.clear(); if (!eatComma("unexpected token, expected comma")) @@ -7878,7 +7879,7 @@ bool MipsAsmParser::parseDirectiveCPSetup() { reportParseError(SaveOpnd.getStartLoc(), "invalid register"); return false; } - Save = SaveOpnd.getGPR32Reg(); + Save = SaveOpnd.getGPR32Reg().id(); } if (!eatComma("unexpected token, expected comma")) @@ -8696,7 +8697,7 @@ bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) { "expected general purpose register"); return false; } - unsigned StackReg = StackRegOpnd.getGPR32Reg(); + MCRegister StackReg = StackRegOpnd.getGPR32Reg(); if (Parser.getTok().is(AsmToken::Comma)) Parser.Lex(); diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 12e31c07aa15a..fd9eb9b8fe9a3 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -103,7 +103,7 @@ LLVMInitializeMipsDisassembler() { createMipselDisassembler); } -static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) { +static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) { const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo(); return RegInfo->getRegClass(RC).getRegister(RegNo); } @@ -123,7 +123,7 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo > 30 || RegNo % 2) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo / 2); + MCRegister Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo / 2); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -134,7 +134,7 @@ static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo >= 4) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -145,7 +145,7 @@ static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo >= 4) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -156,7 +156,7 @@ static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo >= 4) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -167,7 +167,7 @@ static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -178,7 +178,7 @@ static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -189,7 +189,7 @@ static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -200,7 +200,7 @@ static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -211,7 +211,7 @@ static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo > 7) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -222,7 +222,7 @@ static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -233,7 +233,7 @@ static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -881,7 +881,7 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -891,7 +891,7 @@ static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, const MCDisassembler *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -901,7 +901,7 @@ DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -911,7 +911,7 @@ DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -948,7 +948,7 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -974,7 +974,7 @@ static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -985,7 +985,7 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -995,7 +995,7 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1005,7 +1005,7 @@ static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, const MCDisassembler *Decoder) { if (RegNo > 7) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1016,7 +1016,7 @@ static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo > 31) return MCDisassembler::Fail; - unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); + MCRegister Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -1024,11 +1024,11 @@ static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + unsigned RegNo = fieldFromInstruction(Insn, 16, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 21, 5); - Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); if (Inst.getOpcode() == Mips::SC || Inst.getOpcode() == Mips::SC64 || Inst.getOpcode() == Mips::SCD) @@ -1044,14 +1044,14 @@ static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<9>(Insn >> 7); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + unsigned RegNo = fieldFromInstruction(Insn, 16, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 21, 5); - Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); - if (Inst.getOpcode() == Mips::SCE) - Inst.addOperand(MCOperand::createReg(Reg)); + if (Inst.getOpcode() == Mips::SCE) + Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Base)); @@ -1064,11 +1064,11 @@ static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); - unsigned Base = fieldFromInstruction(Insn, 16, 5); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 16, 5); + unsigned RegNo = fieldFromInstruction(Insn, 21, 5); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); + MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Base)); @@ -1081,9 +1081,9 @@ static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); unsigned Hint = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 21, 5); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Base)); Inst.addOperand(MCOperand::createImm(Offset)); @@ -1096,10 +1096,10 @@ static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<12>(Insn & 0xfff); - unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 16, 5); unsigned Hint = fieldFromInstruction(Insn, 21, 5); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Base)); Inst.addOperand(MCOperand::createImm(Offset)); @@ -1112,10 +1112,10 @@ static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<9>(Insn & 0x1ff); - unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 16, 5); unsigned Hint = fieldFromInstruction(Insn, 21, 5); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Base)); Inst.addOperand(MCOperand::createImm(Offset)); @@ -1129,9 +1129,9 @@ static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, const MCDisassembler *Decoder) { int Offset = SignExtend32<9>(Insn >> 7); unsigned Hint = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 21, 5); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Base)); Inst.addOperand(MCOperand::createImm(Offset)); @@ -1143,9 +1143,9 @@ static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 21, 5); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Base)); Inst.addOperand(MCOperand::createImm(Offset)); @@ -1157,9 +1157,9 @@ static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); - unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 16, 5); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Base)); Inst.addOperand(MCOperand::createImm(Offset)); @@ -1170,9 +1170,9 @@ static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Immediate = SignExtend32<16>(Insn & 0xffff); - unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 16, 5); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Base)); Inst.addOperand(MCOperand::createImm(Immediate)); @@ -1184,11 +1184,11 @@ static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); - unsigned Reg = fieldFromInstruction(Insn, 6, 5); - unsigned Base = fieldFromInstruction(Insn, 11, 5); + unsigned RegNo = fieldFromInstruction(Insn, 6, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 11, 5); - Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Base)); @@ -1288,9 +1288,9 @@ static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { unsigned Offset = Insn & 0x1F; - unsigned Reg = fieldFromInstruction(Insn, 5, 5); + unsigned RegNo = fieldFromInstruction(Insn, 5, 5); - Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); + MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Mips::SP)); @@ -1303,9 +1303,9 @@ static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { unsigned Offset = Insn & 0x7F; - unsigned Reg = fieldFromInstruction(Insn, 7, 3); + unsigned RegNo = fieldFromInstruction(Insn, 7, 3); - Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); + MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Mips::GP)); @@ -1342,11 +1342,11 @@ static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<9>(Insn & 0x1ff); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); - unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned RegNo = fieldFromInstruction(Insn, 21, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 16, 5); - Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6) Inst.addOperand(MCOperand::createReg(Reg)); @@ -1362,11 +1362,11 @@ static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<12>(Insn & 0x0fff); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); - unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned RegNo = fieldFromInstruction(Insn, 21, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 16, 5); - Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); switch (Inst.getOpcode()) { case Mips::SWM32_MM: @@ -1396,11 +1396,11 @@ static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); - unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned RegNo = fieldFromInstruction(Insn, 21, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 16, 5); - Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Base)); @@ -1412,11 +1412,11 @@ static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + unsigned RegNo = fieldFromInstruction(Insn, 16, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 21, 5); - Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Base)); @@ -1431,11 +1431,11 @@ static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, // This function is the same as DecodeFMem but with the Reg and Base fields // swapped according to microMIPS spec. int Offset = SignExtend32<16>(Insn & 0xffff); - unsigned Base = fieldFromInstruction(Insn, 16, 5); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 16, 5); + unsigned RegNo = fieldFromInstruction(Insn, 21, 5); - Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Base)); @@ -1447,11 +1447,11 @@ static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + unsigned RegNo = fieldFromInstruction(Insn, 16, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 21, 5); - Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Base)); @@ -1463,11 +1463,11 @@ static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<16>(Insn & 0xffff); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + unsigned RegNo = fieldFromInstruction(Insn, 16, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 21, 5); - Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Reg = getReg(Decoder, Mips::COP3RegClassID, RegNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Base)); @@ -1480,11 +1480,11 @@ static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<11>(Insn & 0x07ff); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 11, 5); + unsigned RegNo = fieldFromInstruction(Insn, 16, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 11, 5); - Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Base)); @@ -1497,11 +1497,11 @@ static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int Offset = SignExtend32<11>(Insn & 0x07ff); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); - unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned RegNo = fieldFromInstruction(Insn, 21, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 16, 5); - Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Base)); @@ -1514,11 +1514,11 @@ static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); - unsigned Rt = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + unsigned RtNo = fieldFromInstruction(Insn, 16, 5); + unsigned BaseNo = fieldFromInstruction(Insn, 21, 5); - Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); - Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + MCRegister Rt = getReg(Decoder, Mips::GPR32RegClassID, RtNo); + MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo); if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ Inst.addOperand(MCOperand::createReg(Rt)); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp index 6b013de274772..fd8eb33e20b26 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp @@ -67,7 +67,7 @@ void MipsRegInfoRecord::EmitMipsOptionRecord() { Streamer->popSection(); } -void MipsRegInfoRecord::SetPhysRegUsed(unsigned Reg, +void MipsRegInfoRecord::SetPhysRegUsed(MCRegister Reg, const MCRegisterInfo *MCRegInfo) { unsigned Value = 0; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp index 1e1b9703d8062..01f18acf050d7 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -126,9 +126,9 @@ void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetMips3D() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetNoMips3D() { forbidModuleDirective(); } -void MipsTargetStreamer::emitDirectiveCpAdd(unsigned RegNo) {} -void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {} -void MipsTargetStreamer::emitDirectiveCpLocal(unsigned RegNo) { +void MipsTargetStreamer::emitDirectiveCpAdd(MCRegister Reg) {} +void MipsTargetStreamer::emitDirectiveCpLoad(MCRegister Reg) {} +void MipsTargetStreamer::emitDirectiveCpLocal(MCRegister Reg) { // .cplocal $reg // This directive forces to use the alternate register for context pointer. // For example @@ -141,17 +141,17 @@ void MipsTargetStreamer::emitDirectiveCpLocal(unsigned RegNo) { if (!getABI().IsN32() && !getABI().IsN64()) return; - GPReg = RegNo; + GPReg = Reg; forbidModuleDirective(); } bool MipsTargetStreamer::emitDirectiveCpRestore( - int Offset, function_ref GetATReg, SMLoc IDLoc, + int Offset, function_ref GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) { forbidModuleDirective(); return true; } -void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, +void MipsTargetStreamer::emitDirectiveCpsetup(MCRegister Reg, int RegOrOffset, const MCSymbol &Sym, bool IsReg) { } void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation, @@ -324,7 +324,7 @@ void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc, /// Emit a store instruction with an immediate offset. void MipsTargetStreamer::emitStoreWithImmOffset( unsigned Opcode, MCRegister SrcReg, MCRegister BaseReg, int64_t Offset, - function_ref GetATReg, SMLoc IDLoc, + function_ref GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) { if (isInt<16>(Offset)) { emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI); @@ -729,38 +729,38 @@ void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask, OS << "," << FPUTopSavedRegOff << '\n'; } -void MipsTargetAsmStreamer::emitDirectiveCpAdd(unsigned RegNo) { +void MipsTargetAsmStreamer::emitDirectiveCpAdd(MCRegister Reg) { OS << "\t.cpadd\t$" - << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n"; + << StringRef(MipsInstPrinter::getRegisterName(Reg)).lower() << "\n"; forbidModuleDirective(); } -void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) { +void MipsTargetAsmStreamer::emitDirectiveCpLoad(MCRegister Reg) { OS << "\t.cpload\t$" - << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n"; + << StringRef(MipsInstPrinter::getRegisterName(Reg)).lower() << "\n"; forbidModuleDirective(); } -void MipsTargetAsmStreamer::emitDirectiveCpLocal(unsigned RegNo) { +void MipsTargetAsmStreamer::emitDirectiveCpLocal(MCRegister Reg) { OS << "\t.cplocal\t$" - << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n"; - MipsTargetStreamer::emitDirectiveCpLocal(RegNo); + << StringRef(MipsInstPrinter::getRegisterName(Reg)).lower() << "\n"; + MipsTargetStreamer::emitDirectiveCpLocal(Reg); } bool MipsTargetAsmStreamer::emitDirectiveCpRestore( - int Offset, function_ref GetATReg, SMLoc IDLoc, + int Offset, function_ref GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) { MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI); OS << "\t.cprestore\t" << Offset << "\n"; return true; } -void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo, +void MipsTargetAsmStreamer::emitDirectiveCpsetup(MCRegister Reg, int RegOrOffset, const MCSymbol &Sym, bool IsReg) { OS << "\t.cpsetup\t$" - << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", "; + << StringRef(MipsInstPrinter::getRegisterName(Reg)).lower() << ", "; if (IsReg) OS << "$" @@ -1229,18 +1229,18 @@ void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask, FPROffset = FPUTopSavedRegOff; } -void MipsTargetELFStreamer::emitDirectiveCpAdd(unsigned RegNo) { +void MipsTargetELFStreamer::emitDirectiveCpAdd(MCRegister Reg) { // .cpadd $reg // This directive inserts code to add $gp to the argument's register // when support for position independent code is enabled. if (!Pic) return; - emitAddu(RegNo, RegNo, GPReg, getABI().IsN64(), &STI); + emitAddu(Reg, Reg, GPReg, getABI().IsN64(), &STI); forbidModuleDirective(); } -void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { +void MipsTargetELFStreamer::emitDirectiveCpLoad(MCRegister Reg) { // .cpload $reg // This directive expands to: // lui $gp, %hi(_gp_disp) @@ -1283,19 +1283,19 @@ void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { TmpInst.setOpcode(Mips::ADDu); TmpInst.addOperand(MCOperand::createReg(GPReg)); TmpInst.addOperand(MCOperand::createReg(GPReg)); - TmpInst.addOperand(MCOperand::createReg(RegNo)); + TmpInst.addOperand(MCOperand::createReg(Reg)); getStreamer().emitInstruction(TmpInst, STI); forbidModuleDirective(); } -void MipsTargetELFStreamer::emitDirectiveCpLocal(unsigned RegNo) { +void MipsTargetELFStreamer::emitDirectiveCpLocal(MCRegister Reg) { if (Pic) - MipsTargetStreamer::emitDirectiveCpLocal(RegNo); + MipsTargetStreamer::emitDirectiveCpLocal(Reg); } bool MipsTargetELFStreamer::emitDirectiveCpRestore( - int Offset, function_ref GetATReg, SMLoc IDLoc, + int Offset, function_ref GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) { MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI); // .cprestore offset @@ -1315,7 +1315,7 @@ bool MipsTargetELFStreamer::emitDirectiveCpRestore( return true; } -void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo, +void MipsTargetELFStreamer::emitDirectiveCpsetup(MCRegister Reg, int RegOrOffset, const MCSymbol &Sym, bool IsReg) { @@ -1353,9 +1353,9 @@ void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo, // (d)addu $gp, $gp, $funcreg if (getABI().IsN32()) - emitRRR(Mips::ADDu, GPReg, GPReg, RegNo, SMLoc(), &STI); + emitRRR(Mips::ADDu, GPReg, GPReg, Reg, SMLoc(), &STI); else - emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), &STI); + emitRRR(Mips::DADDu, GPReg, GPReg, Reg, SMLoc(), &STI); } void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation, diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.h index b726a80ce6b72..71b5d165a9cb3 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.h @@ -98,13 +98,13 @@ class MipsTargetStreamer : public MCTargetStreamer { virtual void emitDirectiveSetHardFloat(); // PIC support - virtual void emitDirectiveCpAdd(unsigned RegNo); - virtual void emitDirectiveCpLoad(unsigned RegNo); - virtual void emitDirectiveCpLocal(unsigned RegNo); + virtual void emitDirectiveCpAdd(MCRegister Reg); + virtual void emitDirectiveCpLoad(MCRegister Reg); + virtual void emitDirectiveCpLocal(MCRegister Reg); virtual bool emitDirectiveCpRestore(int Offset, - function_ref GetATReg, + function_ref GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI); - virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, + virtual void emitDirectiveCpsetup(MCRegister Reg, int RegOrOffset, const MCSymbol &Sym, bool IsReg); virtual void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister); @@ -164,7 +164,7 @@ class MipsTargetStreamer : public MCTargetStreamer { /// by reporting an error). void emitStoreWithImmOffset(unsigned Opcode, MCRegister SrcReg, MCRegister BaseReg, int64_t Offset, - function_ref GetATReg, SMLoc IDLoc, + function_ref GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI); void emitLoadWithImmOffset(unsigned Opcode, MCRegister DstReg, MCRegister BaseReg, int64_t Offset, @@ -205,7 +205,7 @@ class MipsTargetStreamer : public MCTargetStreamer { bool FrameInfoSet; int FrameOffset; unsigned FrameReg; - unsigned GPReg; + MCRegister GPReg; unsigned ReturnReg; private: @@ -290,9 +290,9 @@ class MipsTargetAsmStreamer : public MipsTargetStreamer { void emitDirectiveSetHardFloat() override; // PIC support - void emitDirectiveCpAdd(unsigned RegNo) override; - void emitDirectiveCpLoad(unsigned RegNo) override; - void emitDirectiveCpLocal(unsigned RegNo) override; + void emitDirectiveCpAdd(MCRegister Reg) override; + void emitDirectiveCpLoad(MCRegister Reg) override; + void emitDirectiveCpLocal(MCRegister Reg) override; /// Emit a .cprestore directive. If the offset is out of range then it will /// be synthesized using the assembler temporary. @@ -301,9 +301,9 @@ class MipsTargetAsmStreamer : public MipsTargetStreamer { /// temporary and is only called when the assembler temporary is required. It /// must handle the case where no assembler temporary is available (typically /// by reporting an error). - bool emitDirectiveCpRestore(int Offset, function_ref GetATReg, + bool emitDirectiveCpRestore(int Offset, function_ref GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) override; - void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, + void emitDirectiveCpsetup(MCRegister Reg, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override; void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister) override; @@ -370,12 +370,12 @@ class MipsTargetELFStreamer : public MipsTargetStreamer { void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override; // PIC support - void emitDirectiveCpAdd(unsigned RegNo) override; - void emitDirectiveCpLoad(unsigned RegNo) override; - void emitDirectiveCpLocal(unsigned RegNo) override; - bool emitDirectiveCpRestore(int Offset, function_ref GetATReg, + void emitDirectiveCpAdd(MCRegister Reg) override; + void emitDirectiveCpLoad(MCRegister Reg) override; + void emitDirectiveCpLocal(MCRegister Reg) override; + bool emitDirectiveCpRestore(int Offset, function_ref GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) override; - void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, + void emitDirectiveCpsetup(MCRegister Reg, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override; void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister) override; diff --git a/llvm/lib/Target/Mips/MipsOptionRecord.h b/llvm/lib/Target/Mips/MipsOptionRecord.h index 7897095ef8941..2107baf9f14e5 100644 --- a/llvm/lib/Target/Mips/MipsOptionRecord.h +++ b/llvm/lib/Target/Mips/MipsOptionRecord.h @@ -58,7 +58,7 @@ class MipsRegInfoRecord : public MipsOptionRecord { ~MipsRegInfoRecord() override = default; void EmitMipsOptionRecord() override; - void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo); + void SetPhysRegUsed(MCRegister Reg, const MCRegisterInfo *MCRegInfo); private: MipsELFStreamer *Streamer;