From 840041585819c87c4a5dd900c89eecfe9645b720 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 13 Nov 2025 13:28:42 +0300 Subject: [PATCH 1/2] [CodeGen] Use VirtRegOrUnit in MachineTraceMetrics (NFC) --- .../llvm/CodeGen/MachineTraceMetrics.h | 9 ++++---- llvm/lib/CodeGen/MachineTraceMetrics.cpp | 21 +++++++++++-------- 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineTraceMetrics.h b/llvm/include/llvm/CodeGen/MachineTraceMetrics.h index d51de24d64e8d..8994633f9086b 100644 --- a/llvm/include/llvm/CodeGen/MachineTraceMetrics.h +++ b/llvm/include/llvm/CodeGen/MachineTraceMetrics.h @@ -73,14 +73,14 @@ class TargetRegisterInfo; // direction instructions are scanned, it could be the operand that defined the // regunit, or the highest operand to read the regunit. struct LiveRegUnit { - unsigned RegUnit; + MCRegUnit RegUnit; unsigned Cycle = 0; const MachineInstr *MI = nullptr; unsigned Op = 0; unsigned getSparseSetIndex() const { return RegUnit; } - LiveRegUnit(unsigned RU) : RegUnit(RU) {} + explicit LiveRegUnit(MCRegUnit RU) : RegUnit(RU) {} }; /// Strategies for selecting traces. @@ -156,13 +156,14 @@ class MachineTraceMetrics { /// successors. struct LiveInReg { /// The virtual register required, or a register unit. - Register Reg; + VirtRegOrUnit VRegOrUnit; /// For virtual registers: Minimum height of the defining instruction. /// For regunits: Height of the highest user in the trace. unsigned Height; - LiveInReg(Register Reg, unsigned Height = 0) : Reg(Reg), Height(Height) {} + LiveInReg(VirtRegOrUnit VRegOrUnit, unsigned Height = 0) + : VRegOrUnit(VRegOrUnit), Height(Height) {} }; /// Per-basic block information that relates to a specific trace through the diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp index c40bd1c83f34a..3069ee98454d9 100644 --- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp +++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp @@ -800,9 +800,10 @@ computeCrossBlockCriticalPath(const TraceBlockInfo &TBI) { assert(TBI.HasValidInstrHeights && "Missing height info"); unsigned MaxLen = 0; for (const LiveInReg &LIR : TBI.LiveIns) { - if (!LIR.Reg.isVirtual()) + if (!LIR.VRegOrUnit.isVirtualReg()) continue; - const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); + const MachineInstr *DefMI = + MTM.MRI->getVRegDef(LIR.VRegOrUnit.asVirtualReg()); // Ignore dependencies outside the current trace. const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; if (!DefTBI.isUsefulDominator(TBI)) @@ -1020,7 +1021,7 @@ addLiveIns(const MachineInstr *DefMI, unsigned DefOp, return; TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()]; // Just add the register. The height will be updated later. - TBI.LiveIns.push_back(Reg); + TBI.LiveIns.push_back(VirtRegOrUnit(Reg)); } } @@ -1057,15 +1058,16 @@ computeInstrHeights(const MachineBasicBlock *MBB) { if (MBB) { TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()]; for (LiveInReg &LI : TBI.LiveIns) { - if (LI.Reg.isVirtual()) { + if (LI.VRegOrUnit.isVirtualReg()) { // For virtual registers, the def latency is included. - unsigned &Height = Heights[MTM.MRI->getVRegDef(LI.Reg)]; + unsigned &Height = + Heights[MTM.MRI->getVRegDef(LI.VRegOrUnit.asVirtualReg())]; if (Height < LI.Height) Height = LI.Height; } else { // For register units, the def latency is not included because we don't // know the def yet. - RegUnits[LI.Reg.id()].Cycle = LI.Height; + RegUnits[LI.VRegOrUnit.asMCRegUnit()].Cycle = LI.Height; } } } @@ -1160,14 +1162,15 @@ computeInstrHeights(const MachineBasicBlock *MBB) { // height because the final height isn't known until now. LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " Live-ins:"); for (LiveInReg &LIR : TBI.LiveIns) { - const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); + Register Reg = LIR.VRegOrUnit.asVirtualReg(); + const MachineInstr *DefMI = MTM.MRI->getVRegDef(Reg); LIR.Height = Heights.lookup(DefMI); - LLVM_DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height); + LLVM_DEBUG(dbgs() << ' ' << printReg(Reg) << '@' << LIR.Height); } // Transfer the live regunits to the live-in list. for (const LiveRegUnit &RU : RegUnits) { - TBI.LiveIns.push_back(LiveInReg(RU.RegUnit, RU.Cycle)); + TBI.LiveIns.push_back(LiveInReg(VirtRegOrUnit(RU.RegUnit), RU.Cycle)); LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RU.RegUnit, MTM.TRI) << '@' << RU.Cycle); } From 67528602c2ace94f616d1d35e58926c80630cdf4 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 13 Nov 2025 13:39:14 +0300 Subject: [PATCH 2/2] Mark the other constructor explicit, use emplace_back --- llvm/include/llvm/CodeGen/MachineTraceMetrics.h | 2 +- llvm/lib/CodeGen/MachineTraceMetrics.cpp | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineTraceMetrics.h b/llvm/include/llvm/CodeGen/MachineTraceMetrics.h index 8994633f9086b..cf034ff6600ab 100644 --- a/llvm/include/llvm/CodeGen/MachineTraceMetrics.h +++ b/llvm/include/llvm/CodeGen/MachineTraceMetrics.h @@ -162,7 +162,7 @@ class MachineTraceMetrics { /// For regunits: Height of the highest user in the trace. unsigned Height; - LiveInReg(VirtRegOrUnit VRegOrUnit, unsigned Height = 0) + explicit LiveInReg(VirtRegOrUnit VRegOrUnit, unsigned Height = 0) : VRegOrUnit(VRegOrUnit), Height(Height) {} }; diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp index 3069ee98454d9..d8af760a8917e 100644 --- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp +++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp @@ -1021,7 +1021,7 @@ addLiveIns(const MachineInstr *DefMI, unsigned DefOp, return; TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()]; // Just add the register. The height will be updated later. - TBI.LiveIns.push_back(VirtRegOrUnit(Reg)); + TBI.LiveIns.emplace_back(VirtRegOrUnit(Reg)); } } @@ -1170,7 +1170,7 @@ computeInstrHeights(const MachineBasicBlock *MBB) { // Transfer the live regunits to the live-in list. for (const LiveRegUnit &RU : RegUnits) { - TBI.LiveIns.push_back(LiveInReg(VirtRegOrUnit(RU.RegUnit), RU.Cycle)); + TBI.LiveIns.emplace_back(VirtRegOrUnit(RU.RegUnit), RU.Cycle); LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RU.RegUnit, MTM.TRI) << '@' << RU.Cycle); }