AMDGPU: Add baseline test for load-select to load select of pointer combine

[arsenm]

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[arsenm]

• DAG: Allow select ptr combine for non-0 address spaces #167909
• AMDGPU: Add baseline test for load-select to load select of pointer combine #167908 👈 (View in Graphite)
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[llvmbot]

@llvm/pr-subscribers-llvm-selectiondag

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/167908.diff

1 Files Affected:

• (added) llvm/test/CodeGen/AMDGPU/select-load-to-load-select-ptr-combine.ll (+123)

diff --git a/llvm/test/CodeGen/AMDGPU/select-load-to-load-select-ptr-combine.ll b/llvm/test/CodeGen/AMDGPU/select-load-to-load-select-ptr-combine.ll
new file mode 100644
index 0000000000000..423fb7d52d3e3
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/select-load-to-load-select-ptr-combine.ll
@@ -0,0 +1,123 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
+
+define i32 @select_load_i32_p0(i1 %cond, ptr %a, ptr %b) {
+; CHECK-LABEL: select_load_i32_p0:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; CHECK-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
+; CHECK-NEXT:    flat_load_dword v0, v[1:2]
+; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ld0 = load i32, ptr %a
+  %ld1 = load i32, ptr %b
+  %select = select i1 %cond, i32 %ld0, i32 %ld1
+  ret i32 %select
+}
+
+define i32 @select_load_i32_p1(i1 %cond, ptr addrspace(1) %a, ptr addrspace(1) %b) {
+; CHECK-LABEL: select_load_i32_p1:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    global_load_dword v5, v[1:2], off
+; CHECK-NEXT:    global_load_dword v6, v[3:4], off
+; CHECK-NEXT:    v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v6, v5, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ld0 = load i32, ptr addrspace(1) %a
+  %ld1 = load i32, ptr addrspace(1) %b
+  %select = select i1 %cond, i32 %ld0, i32 %ld1
+  ret i32 %select
+}
+
+define i32 @select_load_i32_p3(i1 %cond, ptr addrspace(3) %a, ptr addrspace(3) %b) {
+; CHECK-LABEL: select_load_i32_p3:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    ds_read_b32 v1, v1
+; CHECK-NEXT:    ds_read_b32 v2, v2
+; CHECK-NEXT:    v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ld0 = load i32, ptr addrspace(3) %a
+  %ld1 = load i32, ptr addrspace(3) %b
+  %select = select i1 %cond, i32 %ld0, i32 %ld1
+  ret i32 %select
+}
+
+define i32 @select_load_i32_p0_p1(i1 %cond, ptr %a, ptr addrspace(1) %b) {
+; CHECK-LABEL: select_load_i32_p0_p1:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    flat_load_dword v5, v[1:2]
+; CHECK-NEXT:    global_load_dword v6, v[3:4], off
+; CHECK-NEXT:    v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v6, v5, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ld0 = load i32, ptr %a
+  %ld1 = load i32, ptr addrspace(1) %b
+  %select = select i1 %cond, i32 %ld0, i32 %ld1
+  ret i32 %select
+}
+
+define i32 @select_load_i32_p1_p0(i1 %cond, ptr addrspace(1) %a, ptr %b) {
+; CHECK-LABEL: select_load_i32_p1_p0:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    global_load_dword v5, v[1:2], off
+; CHECK-NEXT:    flat_load_dword v6, v[3:4]
+; CHECK-NEXT:    v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v6, v5, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ld0 = load i32, ptr addrspace(1) %a
+  %ld1 = load i32, ptr %b
+  %select = select i1 %cond, i32 %ld0, i32 %ld1
+  ret i32 %select
+}
+
+define i8 @select_load_i8_p1(i1 %cond, ptr addrspace(1) %a, ptr addrspace(1) %b) {
+; CHECK-LABEL: select_load_i8_p1:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    global_load_ubyte v5, v[1:2], off
+; CHECK-NEXT:    global_load_ubyte v6, v[3:4], off
+; CHECK-NEXT:    v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v6, v5, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ld0 = load i8, ptr addrspace(1) %a
+  %ld1 = load i8, ptr addrspace(1) %b
+  %select = select i1 %cond, i8 %ld0, i8 %ld1
+  ret i8 %select
+}
+
+define i32 @select_load_i32_p1_offset(i1 %cond, ptr addrspace(1) %a, ptr addrspace(1) %b) {
+; CHECK-LABEL: select_load_i32_p1_offset:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    global_load_dword v3, v[1:2], off offset:256
+; CHECK-NEXT:    global_load_dword v4, v[1:2], off offset:512
+; CHECK-NEXT:    v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v4, v3, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %gep.a = getelementptr i8, ptr addrspace(1) %a, i64 256
+  %gep.b = getelementptr i8, ptr addrspace(1) %a, i64 512
+  %ld0 = load i32, ptr addrspace(1) %gep.a
+  %ld1 = load i32, ptr addrspace(1) %gep.b
+  %select = select i1 %cond, i32 %ld0, i32 %ld1
+  ret i32 %select
+}