diff --git a/clang/lib/Basic/Targets/Hexagon.cpp b/clang/lib/Basic/Targets/Hexagon.cpp index d5b413cb58eb2..bd70bfe4fef51 100644 --- a/clang/lib/Basic/Targets/Hexagon.cpp +++ b/clang/lib/Basic/Targets/Hexagon.cpp @@ -155,9 +155,14 @@ bool HexagonTargetInfo::handleTargetFeatures(std::vector &Features, HasFastHalfType = true; HasFloat16 = true; } + if (CPU.compare("hexagonv81") >= 0) + HasBFloat16 = true; + return true; } +bool HexagonTargetInfo::hasBFloat16Type() const { return HasBFloat16; } + const char *const HexagonTargetInfo::GCCRegNames[] = { // Scalar registers: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", diff --git a/clang/lib/Basic/Targets/Hexagon.h b/clang/lib/Basic/Targets/Hexagon.h index a65663ca09eee..53c348a3246f9 100644 --- a/clang/lib/Basic/Targets/Hexagon.h +++ b/clang/lib/Basic/Targets/Hexagon.h @@ -64,6 +64,8 @@ class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo { // for modeling predicate registers in HVX, and the bool -> byte // correspondence matches the HVX architecture. BoolWidth = BoolAlign = 8; + BFloat16Width = BFloat16Align = 16; + BFloat16Format = &llvm::APFloat::BFloat(); } llvm::SmallVector getTargetBuiltins() const override; @@ -95,6 +97,8 @@ class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo { bool hasFeature(StringRef Feature) const override; + bool hasBFloat16Type() const override; + bool initFeatureMap(llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU, diff --git a/llvm/lib/Target/Hexagon/HexagonCallingConv.td b/llvm/lib/Target/Hexagon/HexagonCallingConv.td index dceb70c8abbf2..80adde8246809 100644 --- a/llvm/lib/Target/Hexagon/HexagonCallingConv.td +++ b/llvm/lib/Target/Hexagon/HexagonCallingConv.td @@ -25,6 +25,8 @@ def CC_HexagonStack: CallingConv<[ def CC_Hexagon_Legacy: CallingConv<[ CCIfType<[i1,i8,i16], CCPromoteToType>, + CCIfType<[bf16], + CCBitConvertToType>, CCIfType<[f32], CCBitConvertToType>, CCIfType<[f64], @@ -55,6 +57,8 @@ def CC_Hexagon_Legacy: CallingConv<[ def CC_Hexagon: CallingConv<[ CCIfType<[i1,i8,i16], CCPromoteToType>, + CCIfType<[bf16], + CCBitConvertToType>, CCIfType<[f32], CCBitConvertToType>, CCIfType<[f64], @@ -88,6 +92,8 @@ def CC_Hexagon: CallingConv<[ def RetCC_Hexagon: CallingConv<[ CCIfType<[i1,i8,i16], CCPromoteToType>, + CCIfType<[bf16], + CCBitConvertToType>, CCIfType<[f32], CCBitConvertToType>, CCIfType<[f64], @@ -149,16 +155,16 @@ def CC_Hexagon_HVX: CallingConv<[ CCIfType<[v128i1], CCPromoteToType>>, CCIfHvx128< - CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16], + CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16,v64bf16], CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>, CCIfHvx128< - CCIfType<[v64i32,v128i16,v256i8,v64f32,v128f16], + CCIfType<[v64i32,v128i16,v256i8,v64f32,v128f16,v128bf16], CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>, CCIfHvx128< - CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16], + CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16,v64bf16], CCAssignToStack<128,128>>>, CCIfHvx128< - CCIfType<[v64i32,v128i16,v256i8,v64f32,v128f16], + CCIfType<[v64i32,v128i16,v256i8,v64f32,v128f16,v64bf16], CCAssignToStack<256,128>>>, CCDelegateTo @@ -175,10 +181,10 @@ def RetCC_Hexagon_HVX: CallingConv<[ // HVX 128-byte mode CCIfHvx128< - CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16], + CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16,v64bf16], CCAssignToReg<[V0]>>>, CCIfHvx128< - CCIfType<[v64i32,v128i16,v256i8,v64f32,v128f16], + CCIfType<[v64i32,v128i16,v256i8,v64f32,v128f16,v128bf16], CCAssignToReg<[W0]>>>, CCDelegateTo diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 04a97606cb7f8..372524a6ac88a 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -1677,6 +1677,8 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, } // Turn FP truncstore into trunc + store. setTruncStoreAction(MVT::f64, MVT::f32, Expand); + setTruncStoreAction(MVT::f32, MVT::bf16, Expand); + setTruncStoreAction(MVT::f64, MVT::bf16, Expand); // Turn FP extload into load/fpextend. for (MVT VT : MVT::fp_valuetypes()) setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); @@ -1872,9 +1874,15 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); + setOperationAction(ISD::BF16_TO_FP, MVT::f32, Expand); + setOperationAction(ISD::BF16_TO_FP, MVT::f64, Expand); + setOperationAction(ISD::FP_TO_BF16, MVT::f64, Expand); setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::bf16, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::bf16, Expand); + setTruncStoreAction(MVT::f32, MVT::f16, Expand); setTruncStoreAction(MVT::f64, MVT::f16, Expand); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index 0573f64084d6f..bcc705c3fd99e 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -88,6 +88,10 @@ HexagonTargetLowering::initializeHVXLowering() { addRegisterClass(MVT::v64f32, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v128f16, &Hexagon::HvxWRRegClass); } + if (Subtarget.useHVXV81Ops()) { + addRegisterClass(MVT::v64bf16, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v128bf16, &Hexagon::HvxWRRegClass); + } } // Set up operation actions. @@ -162,6 +166,30 @@ HexagonTargetLowering::initializeHVXLowering() { setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f32, ByteW); setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v32f32, ByteV); + if (Subtarget.useHVXV81Ops()) { + setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v128bf16, ByteW); + setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64bf16, ByteV); + setPromoteTo(ISD::SETCC, MVT::v64bf16, MVT::v64f32); + setPromoteTo(ISD::FADD, MVT::v64bf16, MVT::v64f32); + setPromoteTo(ISD::FSUB, MVT::v64bf16, MVT::v64f32); + setPromoteTo(ISD::FMUL, MVT::v64bf16, MVT::v64f32); + setPromoteTo(ISD::FMINNUM, MVT::v64bf16, MVT::v64f32); + setPromoteTo(ISD::FMAXNUM, MVT::v64bf16, MVT::v64f32); + + setOperationAction(ISD::SPLAT_VECTOR, MVT::v64bf16, Legal); + setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64bf16, Custom); + setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64bf16, Custom); + + setOperationAction(ISD::MLOAD, MVT::v64bf16, Custom); + setOperationAction(ISD::MSTORE, MVT::v64bf16, Custom); + setOperationAction(ISD::BUILD_VECTOR, MVT::v64bf16, Custom); + setOperationAction(ISD::CONCAT_VECTORS, MVT::v64bf16, Custom); + + setOperationAction(ISD::SPLAT_VECTOR, MVT::bf16, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::bf16, Custom); + setOperationAction(ISD::BUILD_VECTOR, MVT::bf16, Custom); + } + for (MVT P : FloatW) { setOperationAction(ISD::LOAD, P, Custom); setOperationAction(ISD::STORE, P, Custom); @@ -1667,14 +1695,15 @@ HexagonTargetLowering::LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) // In case of MVT::f16 BUILD_VECTOR, since MVT::f16 is // not a legal type, just bitcast the node to use i16 // types and bitcast the result back to f16 - if (VecTy.getVectorElementType() == MVT::f16) { - SmallVector NewOps; + if (VecTy.getVectorElementType() == MVT::f16 || + VecTy.getVectorElementType() == MVT::bf16) { + SmallVector NewOps; for (unsigned i = 0; i != Size; i++) NewOps.push_back(DAG.getBitcast(MVT::i16, Ops[i])); - SDValue T0 = DAG.getNode(ISD::BUILD_VECTOR, dl, - tyVector(VecTy, MVT::i16), NewOps); - return DAG.getBitcast(tyVector(VecTy, MVT::f16), T0); + SDValue T0 = + DAG.getNode(ISD::BUILD_VECTOR, dl, tyVector(VecTy, MVT::i16), NewOps); + return DAG.getBitcast(tyVector(VecTy, VecTy.getVectorElementType()), T0); } // First, split the BUILD_VECTOR for vector pairs. We could generate @@ -1698,7 +1727,7 @@ HexagonTargetLowering::LowerHvxSplatVector(SDValue Op, SelectionDAG &DAG) MVT VecTy = ty(Op); MVT ArgTy = ty(Op.getOperand(0)); - if (ArgTy == MVT::f16) { + if (ArgTy == MVT::f16 || ArgTy == MVT::bf16) { MVT SplatTy = MVT::getVectorVT(MVT::i16, VecTy.getVectorNumElements()); SDValue ToInt16 = DAG.getBitcast(MVT::i16, Op.getOperand(0)); SDValue ToInt32 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, ToInt16); @@ -1831,12 +1860,12 @@ HexagonTargetLowering::LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) if (ElemTy == MVT::i1) return insertHvxElementPred(VecV, IdxV, ValV, dl, DAG); - if (ElemTy == MVT::f16) { + if (ElemTy == MVT::f16 || ElemTy == MVT::bf16) { SDValue T0 = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, tyVector(VecTy, MVT::i16), DAG.getBitcast(tyVector(VecTy, MVT::i16), VecV), DAG.getBitcast(MVT::i16, ValV), IdxV); - return DAG.getBitcast(tyVector(VecTy, MVT::f16), T0); + return DAG.getBitcast(tyVector(VecTy, ElemTy), T0); } return insertHvxElementReg(VecV, IdxV, ValV, dl, DAG); @@ -2334,6 +2363,20 @@ SDValue HexagonTargetLowering::LowerHvxFpExtend(SDValue Op, MVT VecTy = ty(Op); MVT ArgTy = ty(Op.getOperand(0)); const SDLoc &dl(Op); + + if (ArgTy == MVT::v64bf16) { + MVT HalfTy = typeSplit(VecTy).first; + SDValue BF16Vec = Op.getOperand(0); + SDValue Zeroes = getInstr(Hexagon::V6_vxor, dl, HalfTy, {BF16Vec, BF16Vec}, DAG); + // Interleave zero vector with the bf16 vector, with zeroes in the lower half + // of each 32 bit lane, effectively extending the bf16 values to fp32 values. + SDValue ShuffVec = getInstr(Hexagon::V6_vshufoeh, dl, VecTy, {BF16Vec, Zeroes}, DAG); + VectorPair VecPair = opSplit(ShuffVec, dl, DAG); + SDValue Result = getInstr(Hexagon::V6_vshuffvdd, dl, VecTy, + {VecPair.second, VecPair.first, DAG.getSignedConstant(-4, dl, MVT::i32)}, DAG); + return Result; + } + assert(VecTy == MVT::v64f32 && ArgTy == MVT::v64f16); SDValue F16Vec = Op.getOperand(0); diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td index e40dbd251b5b7..e84070f1a5468 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -391,7 +391,6 @@ def Fptoui: pf1; def Sitofp: pf1; def Uitofp: pf1; - // --(1) Immediate ------------------------------------------------------- // @@ -474,6 +473,18 @@ def: OpR_R_pat, i32, F64>; def: OpR_R_pat, i64, F32>; def: OpR_R_pat, i64, F64>; +def: Pat<(i32 (fp_to_bf16 F32:$v)), + (C2_mux (F2_sfclass F32:$v, 0x10), (A2_tfrsi(i32 0x7fff)), + (C2_mux + (C2_cmpeq + (A2_and F32:$v, (A2_tfrsi (i32 0x1FFFF))), + (A2_tfrsi (i32 0x08000))), + (A2_and (A2_asrh F32:$v), (A2_tfrsi (i32 65535))), + (A2_and + (A2_asrh + (A2_add F32:$v, (A2_and F32:$v, (A2_tfrsi (i32 0x8000))))), + (A2_tfrsi (i32 65535)))) + )>; // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp]. def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td index d19920cfc9ea0..4cb29e7f00317 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td +++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td @@ -15,12 +15,14 @@ def HVI16: PatLeaf<(VecI16 HvxVR:$R)>; def HVI32: PatLeaf<(VecI32 HvxVR:$R)>; def HVF16: PatLeaf<(VecF16 HvxVR:$R)>; def HVF32: PatLeaf<(VecF32 HvxVR:$R)>; +def HVBF16: PatLeaf<(VecBF16 HvxVR:$R)>; def HWI8: PatLeaf<(VecPI8 HvxWR:$R)>; def HWI16: PatLeaf<(VecPI16 HvxWR:$R)>; def HWI32: PatLeaf<(VecPI32 HvxWR:$R)>; def HWF16: PatLeaf<(VecPF16 HvxWR:$R)>; def HWF32: PatLeaf<(VecPF32 HvxWR:$R)>; +def HWBF16: PatLeaf<(VecBF16 HvxWR:$R)>; def SDTVecUnaryOp: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; @@ -182,12 +184,15 @@ let Predicates = [UseHVX] in { } let Predicates = [UseHVXV68] in { - defm: HvxLda_pat; - defm: HvxLda_pat; - defm: HvxLda_pat; - defm: HvxLda_pat; - defm: HvxLd_pat; - defm: HvxLd_pat; + defm : HvxLda_pat; + defm : HvxLda_pat; + defm : HvxLda_pat; + defm : HvxLda_pat; + defm : HvxLda_pat; + defm : HvxLda_pat; + defm : HvxLd_pat; + defm : HvxLd_pat; + defm : HvxLd_pat; } // HVX stores @@ -233,10 +238,13 @@ let Predicates = [UseHVX] in { } let Predicates = [UseHVXV68] in { + defm: HvxSt_pat; defm: HvxSt_pat; defm: HvxSt_pat; + defm: HvxSt_pat; defm: HvxSt_pat; defm: HvxSt_pat; + defm: HvxSt_pat; defm: HvxSt_pat; defm: HvxSt_pat; } @@ -255,18 +263,24 @@ let Predicates = [UseHVX] in { let Predicates = [UseHVX, UseHVXFloatingPoint] in { defm: NopCast_pat; + defm: NopCast_pat; defm: NopCast_pat; defm: NopCast_pat; + defm: NopCast_pat; defm: NopCast_pat; defm: NopCast_pat; + defm: NopCast_pat; defm: NopCast_pat; defm: NopCast_pat; defm: NopCast_pat; + defm: NopCast_pat; defm: NopCast_pat; defm: NopCast_pat; + defm: NopCast_pat; defm: NopCast_pat; defm: NopCast_pat; + defm: NopCast_pat; defm: NopCast_pat; defm: NopCast_pat; } @@ -315,11 +329,14 @@ let Predicates = [UseHVX] in { let Predicates = [UseHVX, UseHVXFloatingPoint] in { let AddedComplexity = 100 in { def: Pat<(VecF16 vzero), (V6_vd0)>; + def: Pat<(VecBF16 vzero), (V6_vd0)>; def: Pat<(VecF32 vzero), (V6_vd0)>; def: Pat<(VecPF16 vzero), (PS_vdd0)>; + def: Pat<(VecPBF16 vzero), (PS_vdd0)>; def: Pat<(VecPF32 vzero), (PS_vdd0)>; def: Pat<(concat_vectors (VecF16 vzero), (VecF16 vzero)), (PS_vdd0)>; + def : Pat<(concat_vectors (VecBF16 vzero), (VecBF16 vzero)), (PS_vdd0)>; def: Pat<(concat_vectors (VecF32 vzero), (VecF32 vzero)), (PS_vdd0)>; } @@ -355,11 +372,13 @@ let Predicates = [UseHVX] in { let Predicates = [UseHVXV68, UseHVXFloatingPoint] in { let AddedComplexity = 30 in { def: Pat<(VecF16 (splat_vector u16_0ImmPred:$V)), (PS_vsplatih imm:$V)>; + def: Pat<(VecBF16 (splat_vector u16_0ImmPred:$V)), (PS_vsplatih imm:$V)>; def: Pat<(VecF32 (splat_vector anyint:$V)), (PS_vsplatiw imm:$V)>; def: Pat<(VecF32 (splat_vector f32ImmPred:$V)), (PS_vsplatiw (ftoi $V))>; } let AddedComplexity = 20 in { def: Pat<(VecF16 (splat_vector I32:$Rs)), (PS_vsplatrh $Rs)>; + def: Pat<(VecBF16 (splat_vector I32:$Rs)), (PS_vsplatrh $Rs)>; def: Pat<(VecF32 (splat_vector I32:$Rs)), (PS_vsplatrw $Rs)>; def: Pat<(VecF32 (splat_vector F32:$Rs)), (PS_vsplatrw $Rs)>; } @@ -519,6 +538,35 @@ let Predicates = [UseHVXV68, UseHVXIEEEFP] in { def: Pat<(VecPF16 (Uitofp HVI8:$Vu)), (V6_vcvt_hf_ub HvxVR:$Vu)>; } +let Predicates = [UseHVXV81] in { + def : Pat<(VecBF16 (pf1 HWF32:$Vuu)), + (V6_vpackwuh_sat (V6_vmux + (V6_veqsf (HiVec HvxWR:$Vuu), (HiVec HvxWR:$Vuu)), + (V6_vlsrw (V6_vmux (V6_veqw (V6_vand (HiVec HvxWR:$Vuu), + (PS_vsplatiw (i32 0x1FFFF))), + (PS_vsplatiw (i32 0x08000))), + (HiVec HvxWR:$Vuu), + (V6_vaddw (HiVec HvxWR:$Vuu), + (V6_vand (HiVec HvxWR:$Vuu), + (PS_vsplatiw (i32 0x8000))))), + (A2_tfrsi 16)), + (PS_vsplatih (i32 0x7fff))), + (V6_vmux (V6_veqsf (LoVec HvxWR:$Vuu), (LoVec HvxWR:$Vuu)), + (V6_vlsrw (V6_vmux (V6_veqw (V6_vand (LoVec HvxWR:$Vuu), + (PS_vsplatiw (i32 0x1FFFF))), + (PS_vsplatiw (i32 0x08000))), + (LoVec HvxWR:$Vuu), + (V6_vaddw (LoVec HvxWR:$Vuu), + (V6_vand (LoVec HvxWR:$Vuu), + (PS_vsplatiw (i32 0x8000))))), + (A2_tfrsi 16)), + (PS_vsplatih (i32 0x7fff))))>; +} + +let Predicates = [UseHVXV73, UseHVXQFloat] in { + def : Pat<(VecF32 (Sitofp HVI32:$Vu)), (V6_vconv_sf_w HvxVR:$Vu)>; +} + let Predicates = [UseHVXV68, UseHVXFloatingPoint] in { def: Pat<(vselect HQ16:$Qu, HVF16:$Vs, HVF16:$Vt), (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>; @@ -531,6 +579,13 @@ let Predicates = [UseHVXV68, UseHVXFloatingPoint] in { (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>; } +let Predicates = [UseHVXV81, UseHVXFloatingPoint] in { + def : Pat<(vselect HQ16:$Qu, HVBF16:$Vs, HVBF16:$Vt), + (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>; + def : Pat<(vselect (qnot HQ16:$Qu), HVBF16:$Vs, HVBF16:$Vt), + (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>; +} + let Predicates = [UseHVXV68, UseHVX128B, UseHVXQFloat] in { let AddedComplexity = 220 in { defm: MinMax_pats; diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td index 3a77fcd04e35c..1f1aebd0e5ec9 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -15,141 +15,126 @@ let Namespace = "Hexagon" in { class HexagonReg num, string n, list alt = [], list alias = []> : Register { let Aliases = alias; - let HWEncoding{4-0} = num; + let HWEncoding{4 -0} = num; } // These registers are used to preserve a distinction between // vector register pairs of differing order. - class HexagonFakeReg : Register { - let isArtificial = 1; - } + class HexagonFakeReg : Register { let isArtificial = 1; } class HexagonDoubleReg num, string n, list subregs, - list alt = []> : - RegisterWithSubRegs { + list alt = []> + : RegisterWithSubRegs { let AltNames = alt; - let HWEncoding{4-0} = num; + let HWEncoding{4 -0} = num; } class HexagonSys num, string n, list alt = [], list alias = []> : Register { let Aliases = alias; - let HWEncoding{6-0} = num; + let HWEncoding{6 -0} = num; } class HexagonDoubleSys num, string n, list subregs, - list alt = []> : - RegisterWithSubRegs { + list alt = []> + : RegisterWithSubRegs { let AltNames = alt; - let HWEncoding{6-0} = num; + let HWEncoding{6 -0} = num; } // Registers are identified with 5-bit ID numbers. // Ri - 32-bit integer registers. - class Ri num, string n, list alt = []> : - HexagonReg; + class Ri num, string n, list alt = []> + : HexagonReg; // Rp - false/pseudo registers. These registers are used // to provide a distinct set of aliases for both styles of vector // register pairs without encountering subregister indexing constraints. - class R_fake : - HexagonFakeReg; - + class R_fake : HexagonFakeReg; // Rf - 32-bit floating-point registers. class Rf num, string n> : HexagonReg; // Rd - 64-bit registers. - class Rd num, string n, list subregs, - list alt = []> : - HexagonDoubleReg { + class Rd num, string n, list subregs, list alt = []> + : HexagonDoubleReg { let SubRegs = subregs; } // Rp - predicate registers class Rp num, string n> : HexagonReg; - // Rq - vector predicate registers class Rq num, string n> : Register { - let HWEncoding{2-0} = num; + let HWEncoding{2 -0} = num; } // Rc - control registers - class Rc num, string n, - list alt = [], list alias = []> : - HexagonReg; + class Rc num, string n, list alt = [], + list alias = []> : HexagonReg; // Rcc - 64-bit control registers. class Rcc num, string n, list subregs, - list alt = []> : - HexagonDoubleReg { + list alt = []> : HexagonDoubleReg { let SubRegs = subregs; } // Rs - system registers - class Rs num, string n, - list alt = [], list alias = []> : - HexagonSys; + class Rs num, string n, list alt = [], + list alias = []> : HexagonSys; // Rss - 64-bit system registers. class Rss num, string n, list subregs, - list alt = []> : - HexagonDoubleSys { + list alt = []> : HexagonDoubleSys { let SubRegs = subregs; } // Mx - address modifier registers - class Mx num, string n> : Register { - let HWEncoding{0} = num; - } + class Mx num, string n> : Register { let HWEncoding{0} = num; } // Rg - Guest/Hypervisor registers - class Rg num, string n, - list alt = [], list alias = []> : - HexagonReg; + class Rg num, string n, list alt = [], + list alias = []> : HexagonReg; // Rgg - 64-bit Guest/Hypervisor registers - class Rgg num, string n, list subregs> : - HexagonDoubleReg { + class Rgg num, string n, list subregs> + : HexagonDoubleReg { let SubRegs = subregs; } - def isub_lo : SubRegIndex<32>; - def isub_hi : SubRegIndex<32, 32>; - def vsub_lo : SubRegIndex<-1, -1>; - def vsub_hi : SubRegIndex<-1, -1>; - def vsub_fake: SubRegIndex<-1, -1>; - def wsub_lo : SubRegIndex<-1, -1>; - def wsub_hi : SubRegIndex<-1, -1>; + def isub_lo : SubRegIndex<32>; + def isub_hi : SubRegIndex<32, 32>; + def vsub_lo : SubRegIndex<-1, -1>; + def vsub_hi : SubRegIndex<-1, -1>; + def vsub_fake : SubRegIndex<-1, -1>; + def wsub_lo : SubRegIndex<-1, -1>; + def wsub_hi : SubRegIndex<-1, -1>; def subreg_overflow : SubRegIndex<1, 0>; // Integer registers. - foreach i = 0-28 in { - def R#i : Ri, DwarfRegNum<[i]>; - } + foreach i = 0 -28 in { def R#i : Ri, DwarfRegNum<[i]>; } def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>; def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>; def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>; // Aliases of the R* registers used to hold 64-bit int values (doubles). let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { - def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; - def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; - def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; - def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>; - def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>; - def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>; - def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>; - def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>; - def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>; - def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>; - def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>; - def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>; - def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>; - def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>; - def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>; - def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>; + def D0 : Rd<0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; + def D1 : Rd<2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; + def D2 : Rd<4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; + def D3 : Rd<6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>; + def D4 : Rd<8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>; + def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>; + def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>; + def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>; + def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>; + def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>; + def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>; + def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>; + def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>; + def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>; + def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>; + def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>; } // Predicate registers. @@ -164,119 +149,118 @@ let Namespace = "Hexagon" in { // on the entire USR. def USR_OVF : Rc; - def USR : Rc<8, "usr", ["c8"]>, DwarfRegNum<[75]> { + def USR : Rc<8, "usr", ["c8"]>, DwarfRegNum<[75]> { let SubRegIndices = [subreg_overflow]; let SubRegs = [USR_OVF]; } // Control registers. - def SA0: Rc<0, "sa0", ["c0"]>, DwarfRegNum<[67]>; - def LC0: Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>; - def SA1: Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>; - def LC1: Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>; - def P3_0: Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>, - DwarfRegNum<[71]>; + def SA0 : Rc<0, "sa0", ["c0"]>, DwarfRegNum<[67]>; + def LC0 : Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>; + def SA1 : Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>; + def LC1 : Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>; + def P3_0 : Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>, DwarfRegNum<[71]>; // When defining more Cn registers, make sure to explicitly mark them // as reserved in HexagonRegisterInfo.cpp. - def C5: Rc<5, "c5", ["c5"]>, DwarfRegNum<[72]>; - def M0: Rc<6, "m0", ["c6"]>, DwarfRegNum<[73]>; - def M1: Rc<7, "m1", ["c7"]>, DwarfRegNum<[74]>; + def C5 : Rc<5, "c5", ["c5"]>, DwarfRegNum<[72]>; + def M0 : Rc<6, "m0", ["c6"]>, DwarfRegNum<[73]>; + def M1 : Rc<7, "m1", ["c7"]>, DwarfRegNum<[74]>; // Define C8 separately and make it aliased with USR. // The problem is that USR has subregisters (e.g. overflow). If USR was // specified as a subregister of C9_8, it would imply that subreg_overflow // and isub_lo can be composed, which leads to all kinds of issues // with lane masks. - def C8: Rc<8, "c8", [], [USR]>, DwarfRegNum<[75]>; - def PC: Rc<9, "pc", ["c9"]>, DwarfRegNum<[76]>; - def UGP: Rc<10, "ugp", ["c10"]>, DwarfRegNum<[77]>; - def GP: Rc<11, "gp", ["c11"]>, DwarfRegNum<[78]>; - def CS0: Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>; - def CS1: Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>; - def UPCYCLELO: Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>; - def UPCYCLEHI: Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>; - def FRAMELIMIT: Rc<16, "framelimit", ["c16"]>, DwarfRegNum<[83]>; - def FRAMEKEY: Rc<17, "framekey", ["c17"]>, DwarfRegNum<[84]>; - def PKTCOUNTLO: Rc<18, "pktcountlo", ["c18"]>, DwarfRegNum<[85]>; - def PKTCOUNTHI: Rc<19, "pktcounthi", ["c19"]>, DwarfRegNum<[86]>; - def UTIMERLO: Rc<30, "utimerlo", ["c30"]>, DwarfRegNum<[97]>; - def UTIMERHI: Rc<31, "utimerhi", ["c31"]>, DwarfRegNum<[98]>; + def C8 : Rc<8, "c8", [], [USR]>, DwarfRegNum<[75]>; + def PC : Rc<9, "pc", ["c9"]>, DwarfRegNum<[76]>; + def UGP : Rc<10, "ugp", ["c10"]>, DwarfRegNum<[77]>; + def GP : Rc<11, "gp", ["c11"]>, DwarfRegNum<[78]>; + def CS0 : Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>; + def CS1 : Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>; + def UPCYCLELO : Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>; + def UPCYCLEHI : Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>; + def FRAMELIMIT : Rc<16, "framelimit", ["c16"]>, DwarfRegNum<[83]>; + def FRAMEKEY : Rc<17, "framekey", ["c17"]>, DwarfRegNum<[84]>; + def PKTCOUNTLO : Rc<18, "pktcountlo", ["c18"]>, DwarfRegNum<[85]>; + def PKTCOUNTHI : Rc<19, "pktcounthi", ["c19"]>, DwarfRegNum<[86]>; + def UTIMERLO : Rc<30, "utimerlo", ["c30"]>, DwarfRegNum<[97]>; + def UTIMERHI : Rc<31, "utimerhi", ["c31"]>, DwarfRegNum<[98]>; // Control registers pairs. let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { - def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>; - def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>; - def C5_4 : Rcc<4, "c5:4", [P3_0, C5]>, DwarfRegNum<[71]>; - def C7_6 : Rcc<6, "c7:6", [M0, M1], ["m1:0"]>, DwarfRegNum<[72]>; + def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>; + def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>; + def C5_4 : Rcc<4, "c5:4", [P3_0, C5]>, DwarfRegNum<[71]>; + def C7_6 : Rcc<6, "c7:6", [M0, M1], ["m1:0"]>, DwarfRegNum<[72]>; // Use C8 instead of USR as a subregister of C9_8. - def C9_8 : Rcc<8, "c9:8", [C8, PC]>, DwarfRegNum<[74]>; - def C11_10 : Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>; - def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>; - def UPCYCLE: Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI], ["upcycle"]>, - DwarfRegNum<[80]>; - def C17_16 : Rcc<16, "c17:16", [FRAMELIMIT, FRAMEKEY]>, DwarfRegNum<[83]>; + def C9_8 : Rcc<8, "c9:8", [C8, PC]>, DwarfRegNum<[74]>; + def C11_10 : Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>; + def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>; + def UPCYCLE : Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI], ["upcycle"]>, + DwarfRegNum<[80]>; + def C17_16 : Rcc<16, "c17:16", [FRAMELIMIT, FRAMEKEY]>, DwarfRegNum<[83]>; def PKTCOUNT : Rcc<18, "c19:18", [PKTCOUNTLO, PKTCOUNTHI], ["pktcount"]>, - DwarfRegNum<[85]>; - def UTIMER : Rcc<30, "c31:30", [UTIMERLO, UTIMERHI], ["utimer"]>, - DwarfRegNum<[97]>; + DwarfRegNum<[85]>; + def UTIMER : Rcc<30, "c31:30", [UTIMERLO, UTIMERHI], ["utimer"]>, + DwarfRegNum<[97]>; } - foreach i = 0-31 in { - def V#i : Ri, DwarfRegNum<[!add(i, 99)]>; - def VF#i : R_fake<"__"#!add(i,999999)>, DwarfRegNum<[!add(i, 999999)]>; - def VFR#i : R_fake<"__"#!add(i,9999999)>, DwarfRegNum<[!add(i, 9999999)]>; + foreach i = 0 -31 in { + def V#i : Ri, DwarfRegNum<[!add(i, 99)]>; + def VF#i : R_fake<"__"#!add(i, 999999)>, DwarfRegNum<[!add(i, 999999)]>; + def VFR#i : R_fake<"__"#!add(i, 9999999)>, DwarfRegNum<[!add(i, 9999999)]>; } def VTMP : Ri<0, "vtmp">, DwarfRegNum<[131]>; // Aliases of the V* registers used to hold double vec values. let SubRegIndices = [vsub_lo, vsub_hi, vsub_fake], CoveredBySubRegs = 1 in { - def W0 : Rd< 0, "v1:0", [V0, V1, VF0]>, DwarfRegNum<[99]>; - def W1 : Rd< 2, "v3:2", [V2, V3, VF1]>, DwarfRegNum<[101]>; - def W2 : Rd< 4, "v5:4", [V4, V5, VF2]>, DwarfRegNum<[103]>; - def W3 : Rd< 6, "v7:6", [V6, V7, VF3]>, DwarfRegNum<[105]>; - def W4 : Rd< 8, "v9:8", [V8, V9, VF4]>, DwarfRegNum<[107]>; - def W5 : Rd<10, "v11:10", [V10, V11, VF5]>, DwarfRegNum<[109]>; - def W6 : Rd<12, "v13:12", [V12, V13, VF6]>, DwarfRegNum<[111]>; - def W7 : Rd<14, "v15:14", [V14, V15, VF7]>, DwarfRegNum<[113]>; - def W8 : Rd<16, "v17:16", [V16, V17, VF8]>, DwarfRegNum<[115]>; - def W9 : Rd<18, "v19:18", [V18, V19, VF9]>, DwarfRegNum<[117]>; - def W10 : Rd<20, "v21:20", [V20, V21, VF10]>, DwarfRegNum<[119]>; - def W11 : Rd<22, "v23:22", [V22, V23, VF11]>, DwarfRegNum<[121]>; - def W12 : Rd<24, "v25:24", [V24, V25, VF12]>, DwarfRegNum<[123]>; - def W13 : Rd<26, "v27:26", [V26, V27, VF13]>, DwarfRegNum<[125]>; - def W14 : Rd<28, "v29:28", [V28, V29, VF14]>, DwarfRegNum<[127]>; - def W15 : Rd<30, "v31:30", [V30, V31, VF15]>, DwarfRegNum<[129]>; + def W0 : Rd<0, "v1:0", [V0, V1, VF0]>, DwarfRegNum<[99]>; + def W1 : Rd<2, "v3:2", [V2, V3, VF1]>, DwarfRegNum<[101]>; + def W2 : Rd<4, "v5:4", [V4, V5, VF2]>, DwarfRegNum<[103]>; + def W3 : Rd<6, "v7:6", [V6, V7, VF3]>, DwarfRegNum<[105]>; + def W4 : Rd<8, "v9:8", [V8, V9, VF4]>, DwarfRegNum<[107]>; + def W5 : Rd<10, "v11:10", [V10, V11, VF5]>, DwarfRegNum<[109]>; + def W6 : Rd<12, "v13:12", [V12, V13, VF6]>, DwarfRegNum<[111]>; + def W7 : Rd<14, "v15:14", [V14, V15, VF7]>, DwarfRegNum<[113]>; + def W8 : Rd<16, "v17:16", [V16, V17, VF8]>, DwarfRegNum<[115]>; + def W9 : Rd<18, "v19:18", [V18, V19, VF9]>, DwarfRegNum<[117]>; + def W10 : Rd<20, "v21:20", [V20, V21, VF10]>, DwarfRegNum<[119]>; + def W11 : Rd<22, "v23:22", [V22, V23, VF11]>, DwarfRegNum<[121]>; + def W12 : Rd<24, "v25:24", [V24, V25, VF12]>, DwarfRegNum<[123]>; + def W13 : Rd<26, "v27:26", [V26, V27, VF13]>, DwarfRegNum<[125]>; + def W14 : Rd<28, "v29:28", [V28, V29, VF14]>, DwarfRegNum<[127]>; + def W15 : Rd<30, "v31:30", [V30, V31, VF15]>, DwarfRegNum<[129]>; } // Reverse Aliases of the V* registers used to hold double vec values. let SubRegIndices = [vsub_lo, vsub_hi, vsub_fake], CoveredBySubRegs = 1 in { - def WR0 : Rd< 1, "v0:1", [V0, V1, VFR0]>, DwarfRegNum<[161]>; - def WR1 : Rd< 3, "v2:3", [V2, V3, VFR1]>, DwarfRegNum<[162]>; - def WR2 : Rd< 5, "v4:5", [V4, V5, VFR2]>, DwarfRegNum<[163]>; - def WR3 : Rd< 7, "v6:7", [V6, V7, VFR3]>, DwarfRegNum<[164]>; - def WR4 : Rd< 9, "v8:9", [V8, V9, VFR4]>, DwarfRegNum<[165]>; - def WR5 : Rd<11, "v10:11", [V10, V11, VFR5]>, DwarfRegNum<[166]>; - def WR6 : Rd<13, "v12:13", [V12, V13, VFR6]>, DwarfRegNum<[167]>; - def WR7 : Rd<15, "v14:15", [V14, V15, VFR7]>, DwarfRegNum<[168]>; - def WR8 : Rd<17, "v16:17", [V16, V17, VFR8]>, DwarfRegNum<[169]>; - def WR9 : Rd<19, "v18:19", [V18, V19, VFR9]>, DwarfRegNum<[170]>; - def WR10: Rd<21, "v20:21", [V20, V21, VFR10]>, DwarfRegNum<[171]>; - def WR11: Rd<23, "v22:23", [V22, V23, VFR11]>, DwarfRegNum<[172]>; - def WR12: Rd<25, "v24:25", [V24, V25, VFR12]>, DwarfRegNum<[173]>; - def WR13: Rd<27, "v26:27", [V26, V27, VFR13]>, DwarfRegNum<[174]>; - def WR14: Rd<29, "v28:29", [V28, V29, VFR14]>, DwarfRegNum<[175]>; - def WR15: Rd<31, "v30:31", [V30, V31, VFR15]>, DwarfRegNum<[176]>; + def WR0 : Rd<1, "v0:1", [V0, V1, VFR0]>, DwarfRegNum<[161]>; + def WR1 : Rd<3, "v2:3", [V2, V3, VFR1]>, DwarfRegNum<[162]>; + def WR2 : Rd<5, "v4:5", [V4, V5, VFR2]>, DwarfRegNum<[163]>; + def WR3 : Rd<7, "v6:7", [V6, V7, VFR3]>, DwarfRegNum<[164]>; + def WR4 : Rd<9, "v8:9", [V8, V9, VFR4]>, DwarfRegNum<[165]>; + def WR5 : Rd<11, "v10:11", [V10, V11, VFR5]>, DwarfRegNum<[166]>; + def WR6 : Rd<13, "v12:13", [V12, V13, VFR6]>, DwarfRegNum<[167]>; + def WR7 : Rd<15, "v14:15", [V14, V15, VFR7]>, DwarfRegNum<[168]>; + def WR8 : Rd<17, "v16:17", [V16, V17, VFR8]>, DwarfRegNum<[169]>; + def WR9 : Rd<19, "v18:19", [V18, V19, VFR9]>, DwarfRegNum<[170]>; + def WR10 : Rd<21, "v20:21", [V20, V21, VFR10]>, DwarfRegNum<[171]>; + def WR11 : Rd<23, "v22:23", [V22, V23, VFR11]>, DwarfRegNum<[172]>; + def WR12 : Rd<25, "v24:25", [V24, V25, VFR12]>, DwarfRegNum<[173]>; + def WR13 : Rd<27, "v26:27", [V26, V27, VFR13]>, DwarfRegNum<[174]>; + def WR14 : Rd<29, "v28:29", [V28, V29, VFR14]>, DwarfRegNum<[175]>; + def WR15 : Rd<31, "v30:31", [V30, V31, VFR15]>, DwarfRegNum<[176]>; } // Aliases of the V* registers used to hold quad vec values. let SubRegIndices = [wsub_lo, wsub_hi], CoveredBySubRegs = 1 in { - def VQ0 : Rd< 0, "v3:0", [W0, W1]>, DwarfRegNum<[252]>; - def VQ1 : Rd< 4, "v7:4", [W2, W3]>, DwarfRegNum<[253]>; - def VQ2 : Rd< 8, "v11:8", [W4, W5]>, DwarfRegNum<[254]>; - def VQ3 : Rd<12, "v15:12", [W6, W7]>, DwarfRegNum<[255]>; - def VQ4 : Rd<16, "v19:16", [W8, W9]>, DwarfRegNum<[256]>; - def VQ5 : Rd<20, "v23:20", [W10, W11]>, DwarfRegNum<[257]>; - def VQ6 : Rd<24, "v27:24", [W12, W13]>, DwarfRegNum<[258]>; - def VQ7 : Rd<28, "v31:28", [W14, W15]>, DwarfRegNum<[259]>; + def VQ0 : Rd<0, "v3:0", [W0, W1]>, DwarfRegNum<[252]>; + def VQ1 : Rd<4, "v7:4", [W2, W3]>, DwarfRegNum<[253]>; + def VQ2 : Rd<8, "v11:8", [W4, W5]>, DwarfRegNum<[254]>; + def VQ3 : Rd<12, "v15:12", [W6, W7]>, DwarfRegNum<[255]>; + def VQ4 : Rd<16, "v19:16", [W8, W9]>, DwarfRegNum<[256]>; + def VQ5 : Rd<20, "v23:20", [W10, W11]>, DwarfRegNum<[257]>; + def VQ6 : Rd<24, "v27:24", [W12, W13]>, DwarfRegNum<[258]>; + def VQ7 : Rd<28, "v31:28", [W14, W15]>, DwarfRegNum<[259]>; } // Vector Predicate registers. @@ -286,359 +270,357 @@ let Namespace = "Hexagon" in { def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>; // System registers. - def SGP0 : Rs<0, "sgp0", ["s0"]>, DwarfRegNum<[144]>; - def SGP1 : Rs<1, "sgp1", ["s1"]>, DwarfRegNum<[145]>; - def STID : Rs<2, "stid", ["s2"]>, DwarfRegNum<[146]>; - def ELR : Rs<3, "elr", ["s3"]>, DwarfRegNum<[147]>; - def BADVA0 : Rs<4, "badva0", ["s4"]>, DwarfRegNum<[148]>; - def BADVA1 : Rs<5, "badva1", ["s5"]>, DwarfRegNum<[149]>; - def SSR : Rs<6, "ssr", ["s6"]>, DwarfRegNum<[150]>; - def CCR : Rs<7, "ccr", ["s7"]>, DwarfRegNum<[151]>; - def HTID : Rs<8, "htid", ["s8"]>, DwarfRegNum<[152]>; - def BADVA : Rs<9, "badva", ["s9"]>, DwarfRegNum<[153]>; - def IMASK : Rs<10, "imask", ["s10"]>, DwarfRegNum<[154]>; - def S11 : Rs<11, "s11">, DwarfRegNum<[155]>; - def S12 : Rs<12, "s12">, DwarfRegNum<[156]>; - def S13 : Rs<13, "s13">, DwarfRegNum<[157]>; - def S14 : Rs<14, "s14">, DwarfRegNum<[158]>; - def S15 : Rs<15, "s15">, DwarfRegNum<[159]>; - def EVB : Rs<16, "evb", ["s16"]>, DwarfRegNum<[160]>; - def MODECTL : Rs<17, "modectl", ["s17"]>, DwarfRegNum<[161]>; - def SYSCFG : Rs<18, "syscfg", ["s18"]>, DwarfRegNum<[162]>; - def S19 : Rs<19, "s19", ["s19"]>, DwarfRegNum<[163]>; - def S20 : Rs<20, "s20", ["s20"]>, DwarfRegNum<[164]>; - def VID : Rs<21, "vid", ["s21"]>, DwarfRegNum<[165]>; - def S22 : Rs<22, "s22", ["s22"]>, DwarfRegNum<[166]>; - def S23 : Rs<23, "s23">, DwarfRegNum<[167]>; - def S24 : Rs<24, "s24">, DwarfRegNum<[168]>; - def S25 : Rs<25, "s25">, DwarfRegNum<[169]>; - def S26 : Rs<26, "s26">, DwarfRegNum<[170]>; - def CFGBASE : Rs<27, "cfgbase", ["s27"]>, DwarfRegNum<[171]>; - def DIAG : Rs<28, "diag", ["s28"]>, DwarfRegNum<[172]>; - def REV : Rs<29, "rev", ["s29"]>, DwarfRegNum<[173]>; - def PCYCLELO : Rs<30, "pcyclelo", ["s30"]>, DwarfRegNum<[174]>; - def PCYCLEHI : Rs<31, "pcyclehi", ["s31"]>, DwarfRegNum<[175]>; - def ISDBST : Rs<32, "isdbst", ["s32"]>, DwarfRegNum<[176]>; - def ISDBCFG0 : Rs<33, "isdbcfg0", ["s33"]>, DwarfRegNum<[177]>; - def ISDBCFG1 : Rs<34, "isdbcfg1", ["s34"]>, DwarfRegNum<[178]>; - def S35 : Rs<35, "s35">, DwarfRegNum<[179]>; - def BRKPTPC0 : Rs<36, "brkptpc0", ["s36"]>, DwarfRegNum<[180]>; - def BRKPTCFG0: Rs<37, "brkptcfg0", ["s37"]>, DwarfRegNum<[181]>; - def BRKPTPC1 : Rs<38, "brkptpc1", ["s38"]>, DwarfRegNum<[182]>; - def BRKPTCFG1: Rs<39, "brkptcfg1", ["s39"]>, DwarfRegNum<[183]>; - def ISDBMBXIN: Rs<40, "isdbmbxin", ["s40"]>, DwarfRegNum<[184]>; - def ISDBMBXOUT: Rs<41, "isdbmbxout", ["s41"]>, DwarfRegNum<[185]>; - def ISDBEN: Rs<42, "isdben", ["s42"]>, DwarfRegNum<[186]>; - def ISDBGPR: Rs<43, "isdbgpr", ["s43"]>, DwarfRegNum<[187]>; - def S44: Rs<44, "s44">, DwarfRegNum<[188]>; - def S45: Rs<45, "s45">, DwarfRegNum<[189]>; - def S46: Rs<46, "s46">, DwarfRegNum<[190]>; - def S47: Rs<47, "s47">, DwarfRegNum<[191]>; - def PMUCNT0: Rs<48, "pmucnt0", ["s48"]>, DwarfRegNum<[192]>; - def PMUCNT1: Rs<49, "pmucnt1", ["s49"]>, DwarfRegNum<[193]>; - def PMUCNT2: Rs<50, "pmucnt2", ["s50"]>, DwarfRegNum<[194]>; - def PMUCNT3: Rs<51, "pmucnt3", ["s51"]>, DwarfRegNum<[195]>; - def PMUEVTCFG: Rs<52, "pmuevtcfg", ["s52"]>, DwarfRegNum<[196]>; - def PMUCFG: Rs<53, "pmucfg", ["s53"]>, DwarfRegNum<[197]>; - def S54: Rs<54, "s54">, DwarfRegNum<[198]>; - def S55: Rs<55, "s55">, DwarfRegNum<[199]>; - def S56: Rs<56, "s56">, DwarfRegNum<[200]>; - def S57: Rs<57, "s57">, DwarfRegNum<[201]>; - def S58: Rs<58, "s58">, DwarfRegNum<[202]>; - def S59: Rs<59, "s59">, DwarfRegNum<[203]>; - def S60: Rs<60, "s60">, DwarfRegNum<[204]>; - def S61: Rs<61, "s61">, DwarfRegNum<[205]>; - def S62: Rs<62, "s62">, DwarfRegNum<[206]>; - def S63: Rs<63, "s63">, DwarfRegNum<[207]>; - def S64: Rs<64, "s64">, DwarfRegNum<[208]>; - def S65: Rs<65, "s65">, DwarfRegNum<[209]>; - def S66: Rs<66, "s66">, DwarfRegNum<[210]>; - def S67: Rs<67, "s67">, DwarfRegNum<[211]>; - def S68: Rs<68, "s68">, DwarfRegNum<[212]>; - def S69: Rs<69, "s69">, DwarfRegNum<[213]>; - def S70: Rs<70, "s70">, DwarfRegNum<[214]>; - def S71: Rs<71, "s71">, DwarfRegNum<[215]>; - def S72: Rs<72, "s72">, DwarfRegNum<[216]>; - def S73: Rs<73, "s73">, DwarfRegNum<[217]>; - def S74: Rs<74, "s74">, DwarfRegNum<[218]>; - def S75: Rs<75, "s75">, DwarfRegNum<[219]>; - def S76: Rs<76, "s76">, DwarfRegNum<[220]>; - def S77: Rs<77, "s77">, DwarfRegNum<[221]>; - def S78: Rs<78, "s78">, DwarfRegNum<[222]>; - def S79: Rs<79, "s79">, DwarfRegNum<[223]>; - def S80: Rs<80, "s80">, DwarfRegNum<[224]>; + def SGP0 : Rs<0, "sgp0", ["s0"]>, DwarfRegNum<[144]>; + def SGP1 : Rs<1, "sgp1", ["s1"]>, DwarfRegNum<[145]>; + def STID : Rs<2, "stid", ["s2"]>, DwarfRegNum<[146]>; + def ELR : Rs<3, "elr", ["s3"]>, DwarfRegNum<[147]>; + def BADVA0 : Rs<4, "badva0", ["s4"]>, DwarfRegNum<[148]>; + def BADVA1 : Rs<5, "badva1", ["s5"]>, DwarfRegNum<[149]>; + def SSR : Rs<6, "ssr", ["s6"]>, DwarfRegNum<[150]>; + def CCR : Rs<7, "ccr", ["s7"]>, DwarfRegNum<[151]>; + def HTID : Rs<8, "htid", ["s8"]>, DwarfRegNum<[152]>; + def BADVA : Rs<9, "badva", ["s9"]>, DwarfRegNum<[153]>; + def IMASK : Rs<10, "imask", ["s10"]>, DwarfRegNum<[154]>; + def S11 : Rs<11, "s11">, DwarfRegNum<[155]>; + def S12 : Rs<12, "s12">, DwarfRegNum<[156]>; + def S13 : Rs<13, "s13">, DwarfRegNum<[157]>; + def S14 : Rs<14, "s14">, DwarfRegNum<[158]>; + def S15 : Rs<15, "s15">, DwarfRegNum<[159]>; + def EVB : Rs<16, "evb", ["s16"]>, DwarfRegNum<[160]>; + def MODECTL : Rs<17, "modectl", ["s17"]>, DwarfRegNum<[161]>; + def SYSCFG : Rs<18, "syscfg", ["s18"]>, DwarfRegNum<[162]>; + def S19 : Rs<19, "s19", ["s19"]>, DwarfRegNum<[163]>; + def S20 : Rs<20, "s20", ["s20"]>, DwarfRegNum<[164]>; + def VID : Rs<21, "vid", ["s21"]>, DwarfRegNum<[165]>; + def S22 : Rs<22, "s22", ["s22"]>, DwarfRegNum<[166]>; + def S23 : Rs<23, "s23">, DwarfRegNum<[167]>; + def S24 : Rs<24, "s24">, DwarfRegNum<[168]>; + def S25 : Rs<25, "s25">, DwarfRegNum<[169]>; + def S26 : Rs<26, "s26">, DwarfRegNum<[170]>; + def CFGBASE : Rs<27, "cfgbase", ["s27"]>, DwarfRegNum<[171]>; + def DIAG : Rs<28, "diag", ["s28"]>, DwarfRegNum<[172]>; + def REV : Rs<29, "rev", ["s29"]>, DwarfRegNum<[173]>; + def PCYCLELO : Rs<30, "pcyclelo", ["s30"]>, DwarfRegNum<[174]>; + def PCYCLEHI : Rs<31, "pcyclehi", ["s31"]>, DwarfRegNum<[175]>; + def ISDBST : Rs<32, "isdbst", ["s32"]>, DwarfRegNum<[176]>; + def ISDBCFG0 : Rs<33, "isdbcfg0", ["s33"]>, DwarfRegNum<[177]>; + def ISDBCFG1 : Rs<34, "isdbcfg1", ["s34"]>, DwarfRegNum<[178]>; + def S35 : Rs<35, "s35">, DwarfRegNum<[179]>; + def BRKPTPC0 : Rs<36, "brkptpc0", ["s36"]>, DwarfRegNum<[180]>; + def BRKPTCFG0 : Rs<37, "brkptcfg0", ["s37"]>, DwarfRegNum<[181]>; + def BRKPTPC1 : Rs<38, "brkptpc1", ["s38"]>, DwarfRegNum<[182]>; + def BRKPTCFG1 : Rs<39, "brkptcfg1", ["s39"]>, DwarfRegNum<[183]>; + def ISDBMBXIN : Rs<40, "isdbmbxin", ["s40"]>, DwarfRegNum<[184]>; + def ISDBMBXOUT : Rs<41, "isdbmbxout", ["s41"]>, DwarfRegNum<[185]>; + def ISDBEN : Rs<42, "isdben", ["s42"]>, DwarfRegNum<[186]>; + def ISDBGPR : Rs<43, "isdbgpr", ["s43"]>, DwarfRegNum<[187]>; + def S44 : Rs<44, "s44">, DwarfRegNum<[188]>; + def S45 : Rs<45, "s45">, DwarfRegNum<[189]>; + def S46 : Rs<46, "s46">, DwarfRegNum<[190]>; + def S47 : Rs<47, "s47">, DwarfRegNum<[191]>; + def PMUCNT0 : Rs<48, "pmucnt0", ["s48"]>, DwarfRegNum<[192]>; + def PMUCNT1 : Rs<49, "pmucnt1", ["s49"]>, DwarfRegNum<[193]>; + def PMUCNT2 : Rs<50, "pmucnt2", ["s50"]>, DwarfRegNum<[194]>; + def PMUCNT3 : Rs<51, "pmucnt3", ["s51"]>, DwarfRegNum<[195]>; + def PMUEVTCFG : Rs<52, "pmuevtcfg", ["s52"]>, DwarfRegNum<[196]>; + def PMUCFG : Rs<53, "pmucfg", ["s53"]>, DwarfRegNum<[197]>; + def S54 : Rs<54, "s54">, DwarfRegNum<[198]>; + def S55 : Rs<55, "s55">, DwarfRegNum<[199]>; + def S56 : Rs<56, "s56">, DwarfRegNum<[200]>; + def S57 : Rs<57, "s57">, DwarfRegNum<[201]>; + def S58 : Rs<58, "s58">, DwarfRegNum<[202]>; + def S59 : Rs<59, "s59">, DwarfRegNum<[203]>; + def S60 : Rs<60, "s60">, DwarfRegNum<[204]>; + def S61 : Rs<61, "s61">, DwarfRegNum<[205]>; + def S62 : Rs<62, "s62">, DwarfRegNum<[206]>; + def S63 : Rs<63, "s63">, DwarfRegNum<[207]>; + def S64 : Rs<64, "s64">, DwarfRegNum<[208]>; + def S65 : Rs<65, "s65">, DwarfRegNum<[209]>; + def S66 : Rs<66, "s66">, DwarfRegNum<[210]>; + def S67 : Rs<67, "s67">, DwarfRegNum<[211]>; + def S68 : Rs<68, "s68">, DwarfRegNum<[212]>; + def S69 : Rs<69, "s69">, DwarfRegNum<[213]>; + def S70 : Rs<70, "s70">, DwarfRegNum<[214]>; + def S71 : Rs<71, "s71">, DwarfRegNum<[215]>; + def S72 : Rs<72, "s72">, DwarfRegNum<[216]>; + def S73 : Rs<73, "s73">, DwarfRegNum<[217]>; + def S74 : Rs<74, "s74">, DwarfRegNum<[218]>; + def S75 : Rs<75, "s75">, DwarfRegNum<[219]>; + def S76 : Rs<76, "s76">, DwarfRegNum<[220]>; + def S77 : Rs<77, "s77">, DwarfRegNum<[221]>; + def S78 : Rs<78, "s78">, DwarfRegNum<[222]>; + def S79 : Rs<79, "s79">, DwarfRegNum<[223]>; + def S80 : Rs<80, "s80">, DwarfRegNum<[224]>; // System Register Pair let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { - def SGP1_0 : Rss<0, "s1:0", [SGP0, SGP1], ["sgp1:0"]>, DwarfRegNum<[144]>; - def S3_2 : Rss<2, "s3:2", [STID, ELR]>, DwarfRegNum<[146]>; - def S5_4 : Rss<4, "s5:4", [BADVA0, BADVA1], ["badva1:0"]>, - DwarfRegNum<[148]>; - def S7_6 : Rss<6, "s7:6", [SSR, CCR], ["ccr:ssr"]>, DwarfRegNum<[150]>; - def S9_8 : Rss<8, "s9:8", [HTID, BADVA]>, DwarfRegNum<[152]>; - def S11_10 : Rss<10, "s11:10", [IMASK, S11]>, DwarfRegNum<[154]>; - def S13_12 : Rss<12, "s13:12", [S12, S13]>, DwarfRegNum<[156]>; - def S15_14 : Rss<14, "s15:14", [S14, S15]>, DwarfRegNum<[158]>; - def S17_16 : Rss<16, "s17:16", [EVB, MODECTL]>, DwarfRegNum<[160]>; - def S19_18 : Rss<18, "s19:18", [SYSCFG, S19]>, DwarfRegNum<[162]>; - def S21_20 : Rss<20, "s21:20", [S20, VID]>, DwarfRegNum<[164]>; - def S23_22 : Rss<22, "s23:22", [S22, S23]>, DwarfRegNum<[166]>; - def S25_24 : Rss<24, "s25:24", [S24, S25]>, DwarfRegNum<[168]>; - def S27_26 : Rss<26, "s27:26", [S26, CFGBASE]>, DwarfRegNum<[170]>; - def S29_28 : Rss<28, "s29:28", [DIAG, REV]>, DwarfRegNum<[172]>; - def S31_30 : Rss<30, "s31:30", [PCYCLELO, PCYCLEHI], ["pcycle"]>, DwarfRegNum<[174]>; - def S33_32 : Rss<32, "s33:32", [ISDBST, ISDBCFG0]>, DwarfRegNum<[176]>; - def S35_34 : Rss<34, "s35:34", [ISDBCFG1, S35]>, DwarfRegNum<[178]>; - def S37_36 : Rss<36, "s37:36", [BRKPTPC0, BRKPTCFG0]>, DwarfRegNum<[180]>; - def S39_38 : Rss<38, "s39:38", [BRKPTPC1, BRKPTCFG1]>, DwarfRegNum<[182]>; + def SGP1_0 : Rss<0, "s1:0", [SGP0, SGP1], ["sgp1:0"]>, DwarfRegNum<[144]>; + def S3_2 : Rss<2, "s3:2", [STID, ELR]>, DwarfRegNum<[146]>; + def S5_4 : Rss<4, "s5:4", [BADVA0, BADVA1], ["badva1:0"]>, + DwarfRegNum<[148]>; + def S7_6 : Rss<6, "s7:6", [SSR, CCR], ["ccr:ssr"]>, DwarfRegNum<[150]>; + def S9_8 : Rss<8, "s9:8", [HTID, BADVA]>, DwarfRegNum<[152]>; + def S11_10 : Rss<10, "s11:10", [IMASK, S11]>, DwarfRegNum<[154]>; + def S13_12 : Rss<12, "s13:12", [S12, S13]>, DwarfRegNum<[156]>; + def S15_14 : Rss<14, "s15:14", [S14, S15]>, DwarfRegNum<[158]>; + def S17_16 : Rss<16, "s17:16", [EVB, MODECTL]>, DwarfRegNum<[160]>; + def S19_18 : Rss<18, "s19:18", [SYSCFG, S19]>, DwarfRegNum<[162]>; + def S21_20 : Rss<20, "s21:20", [S20, VID]>, DwarfRegNum<[164]>; + def S23_22 : Rss<22, "s23:22", [S22, S23]>, DwarfRegNum<[166]>; + def S25_24 : Rss<24, "s25:24", [S24, S25]>, DwarfRegNum<[168]>; + def S27_26 : Rss<26, "s27:26", [S26, CFGBASE]>, DwarfRegNum<[170]>; + def S29_28 : Rss<28, "s29:28", [DIAG, REV]>, DwarfRegNum<[172]>; + def S31_30 : Rss<30, "s31:30", [PCYCLELO, PCYCLEHI], ["pcycle"]>, + DwarfRegNum<[174]>; + def S33_32 : Rss<32, "s33:32", [ISDBST, ISDBCFG0]>, DwarfRegNum<[176]>; + def S35_34 : Rss<34, "s35:34", [ISDBCFG1, S35]>, DwarfRegNum<[178]>; + def S37_36 : Rss<36, "s37:36", [BRKPTPC0, BRKPTCFG0]>, DwarfRegNum<[180]>; + def S39_38 : Rss<38, "s39:38", [BRKPTPC1, BRKPTCFG1]>, DwarfRegNum<[182]>; def S41_40 : Rss<40, "s41:40", [ISDBMBXIN, ISDBMBXOUT]>, DwarfRegNum<[184]>; - def S43_42 : Rss<42, "s43:42", [ISDBEN, ISDBGPR]>, DwarfRegNum<[186]>; - def S45_44 : Rss<44, "s45:44", [S44, S45]>, DwarfRegNum<[188]>; - def S47_46 : Rss<46, "s47:46", [S46, S47]>, DwarfRegNum<[190]>; - def S49_48 : Rss<48, "s49:48", [PMUCNT0, PMUCNT1]>, DwarfRegNum<[192]>; - def S51_50 : Rss<50, "s51:50", [PMUCNT2, PMUCNT3]>, DwarfRegNum<[194]>; - def S53_52 : Rss<52, "s53:52", [PMUEVTCFG, PMUCFG]>, DwarfRegNum<[196]>; - def S55_54 : Rss<54, "s55:54", [S54, S55]>, DwarfRegNum<[198]>; - def S57_56 : Rss<56, "s57:56", [S56, S57]>, DwarfRegNum<[200]>; - def S59_58 : Rss<58, "s59:58", [S58, S59]>, DwarfRegNum<[202]>; - def S61_60 : Rss<60, "s61:60", [S60, S61]>, DwarfRegNum<[204]>; - def S63_62 : Rss<62, "s63:62", [S62, S63]>, DwarfRegNum<[206]>; - def S65_64 : Rss<64, "s65:64", [S64, S65]>, DwarfRegNum<[208]>; - def S67_66 : Rss<66, "s67:66", [S66, S67]>, DwarfRegNum<[210]>; - def S69_68 : Rss<68, "s69:68", [S68, S69]>, DwarfRegNum<[212]>; - def S71_70 : Rss<70, "s71:70", [S70, S71]>, DwarfRegNum<[214]>; - def S73_72 : Rss<72, "s73:72", [S72, S73]>, DwarfRegNum<[216]>; - def S75_74 : Rss<74, "s75:74", [S74, S75]>, DwarfRegNum<[218]>; - def S77_76 : Rss<76, "s77:76", [S77, S76]>, DwarfRegNum<[219]>; - def S79_78 : Rss<78, "s79:78", [S79, S78]>, DwarfRegNum<[220]>; + def S43_42 : Rss<42, "s43:42", [ISDBEN, ISDBGPR]>, DwarfRegNum<[186]>; + def S45_44 : Rss<44, "s45:44", [S44, S45]>, DwarfRegNum<[188]>; + def S47_46 : Rss<46, "s47:46", [S46, S47]>, DwarfRegNum<[190]>; + def S49_48 : Rss<48, "s49:48", [PMUCNT0, PMUCNT1]>, DwarfRegNum<[192]>; + def S51_50 : Rss<50, "s51:50", [PMUCNT2, PMUCNT3]>, DwarfRegNum<[194]>; + def S53_52 : Rss<52, "s53:52", [PMUEVTCFG, PMUCFG]>, DwarfRegNum<[196]>; + def S55_54 : Rss<54, "s55:54", [S54, S55]>, DwarfRegNum<[198]>; + def S57_56 : Rss<56, "s57:56", [S56, S57]>, DwarfRegNum<[200]>; + def S59_58 : Rss<58, "s59:58", [S58, S59]>, DwarfRegNum<[202]>; + def S61_60 : Rss<60, "s61:60", [S60, S61]>, DwarfRegNum<[204]>; + def S63_62 : Rss<62, "s63:62", [S62, S63]>, DwarfRegNum<[206]>; + def S65_64 : Rss<64, "s65:64", [S64, S65]>, DwarfRegNum<[208]>; + def S67_66 : Rss<66, "s67:66", [S66, S67]>, DwarfRegNum<[210]>; + def S69_68 : Rss<68, "s69:68", [S68, S69]>, DwarfRegNum<[212]>; + def S71_70 : Rss<70, "s71:70", [S70, S71]>, DwarfRegNum<[214]>; + def S73_72 : Rss<72, "s73:72", [S72, S73]>, DwarfRegNum<[216]>; + def S75_74 : Rss<74, "s75:74", [S74, S75]>, DwarfRegNum<[218]>; + def S77_76 : Rss<76, "s77:76", [S77, S76]>, DwarfRegNum<[219]>; + def S79_78 : Rss<78, "s79:78", [S79, S78]>, DwarfRegNum<[220]>; } // Guest Registers - def GELR: Rg<0, "gelr", ["g0"]>, DwarfRegNum<[220]>; - def GSR: Rg<1, "gsr", ["g1"]>, DwarfRegNum<[221]>; - def GOSP: Rg<2, "gosp", ["g2"]>, DwarfRegNum<[222]>; - def G3: Rg<3, "gbadva", ["g3"]>, DwarfRegNum<[223]>; - def G4: Rg<4, "g4">, DwarfRegNum<[224]>; - def G5: Rg<5, "g5">, DwarfRegNum<[225]>; - def G6: Rg<6, "g6">, DwarfRegNum<[226]>; - def G7: Rg<7, "g7">, DwarfRegNum<[227]>; - def G8: Rg<8, "g8">, DwarfRegNum<[228]>; - def G9: Rg<9, "g9">, DwarfRegNum<[229]>; - def G10: Rg<10, "g10">, DwarfRegNum<[230]>; - def G11: Rg<11, "g11">, DwarfRegNum<[231]>; - def G12: Rg<12, "g12">, DwarfRegNum<[232]>; - def G13: Rg<13, "g13">, DwarfRegNum<[233]>; - def G14: Rg<14, "g14">, DwarfRegNum<[234]>; - def G15: Rg<15, "g15">, DwarfRegNum<[235]>; - def GPMUCNT4: Rg<16, "gpmucnt4", ["g16"]>, DwarfRegNum<[236]>; - def GPMUCNT5: Rg<17, "gpmucnt5", ["g17"]>, DwarfRegNum<[237]>; - def GPMUCNT6: Rg<18, "gpmucnt6", ["g18"]>, DwarfRegNum<[238]>; - def GPMUCNT7: Rg<19, "gpmucnt7", ["g19"]>, DwarfRegNum<[239]>; - def G20: Rg<20, "g20">, DwarfRegNum<[240]>; - def G21: Rg<21, "g21">, DwarfRegNum<[241]>; - def G22: Rg<22, "g22">, DwarfRegNum<[242]>; - def G23: Rg<23, "g23">, DwarfRegNum<[243]>; - def GPCYCLELO: Rg<24, "gpcyclelo", ["g24"]>, DwarfRegNum<[244]>; - def GPCYCLEHI: Rg<25, "gpcyclehi", ["g25"]>, DwarfRegNum<[245]>; - def GPMUCNT0: Rg<26, "gpmucnt0", ["g26"]>, DwarfRegNum<[246]>; - def GPMUCNT1: Rg<27, "gpmucnt1", ["g27"]>, DwarfRegNum<[247]>; - def GPMUCNT2: Rg<28, "gpmucnt2", ["g28"]>, DwarfRegNum<[248]>; - def GPMUCNT3: Rg<29, "gpmucnt3", ["g29"]>, DwarfRegNum<[249]>; - def G30: Rg<30, "g30">, DwarfRegNum<[250]>; - def G31: Rg<31, "g31">, DwarfRegNum<[251]>; + def GELR : Rg<0, "gelr", ["g0"]>, DwarfRegNum<[220]>; + def GSR : Rg<1, "gsr", ["g1"]>, DwarfRegNum<[221]>; + def GOSP : Rg<2, "gosp", ["g2"]>, DwarfRegNum<[222]>; + def G3 : Rg<3, "gbadva", ["g3"]>, DwarfRegNum<[223]>; + def G4 : Rg<4, "g4">, DwarfRegNum<[224]>; + def G5 : Rg<5, "g5">, DwarfRegNum<[225]>; + def G6 : Rg<6, "g6">, DwarfRegNum<[226]>; + def G7 : Rg<7, "g7">, DwarfRegNum<[227]>; + def G8 : Rg<8, "g8">, DwarfRegNum<[228]>; + def G9 : Rg<9, "g9">, DwarfRegNum<[229]>; + def G10 : Rg<10, "g10">, DwarfRegNum<[230]>; + def G11 : Rg<11, "g11">, DwarfRegNum<[231]>; + def G12 : Rg<12, "g12">, DwarfRegNum<[232]>; + def G13 : Rg<13, "g13">, DwarfRegNum<[233]>; + def G14 : Rg<14, "g14">, DwarfRegNum<[234]>; + def G15 : Rg<15, "g15">, DwarfRegNum<[235]>; + def GPMUCNT4 : Rg<16, "gpmucnt4", ["g16"]>, DwarfRegNum<[236]>; + def GPMUCNT5 : Rg<17, "gpmucnt5", ["g17"]>, DwarfRegNum<[237]>; + def GPMUCNT6 : Rg<18, "gpmucnt6", ["g18"]>, DwarfRegNum<[238]>; + def GPMUCNT7 : Rg<19, "gpmucnt7", ["g19"]>, DwarfRegNum<[239]>; + def G20 : Rg<20, "g20">, DwarfRegNum<[240]>; + def G21 : Rg<21, "g21">, DwarfRegNum<[241]>; + def G22 : Rg<22, "g22">, DwarfRegNum<[242]>; + def G23 : Rg<23, "g23">, DwarfRegNum<[243]>; + def GPCYCLELO : Rg<24, "gpcyclelo", ["g24"]>, DwarfRegNum<[244]>; + def GPCYCLEHI : Rg<25, "gpcyclehi", ["g25"]>, DwarfRegNum<[245]>; + def GPMUCNT0 : Rg<26, "gpmucnt0", ["g26"]>, DwarfRegNum<[246]>; + def GPMUCNT1 : Rg<27, "gpmucnt1", ["g27"]>, DwarfRegNum<[247]>; + def GPMUCNT2 : Rg<28, "gpmucnt2", ["g28"]>, DwarfRegNum<[248]>; + def GPMUCNT3 : Rg<29, "gpmucnt3", ["g29"]>, DwarfRegNum<[249]>; + def G30 : Rg<30, "g30">, DwarfRegNum<[250]>; + def G31 : Rg<31, "g31">, DwarfRegNum<[251]>; // Guest Register Pairs let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { - def G1_0 : Rgg<0, "g1:0", [GELR, GSR]>, DwarfRegNum<[220]>; - def G3_2 : Rgg<2, "g3:2", [GOSP, G3]>, DwarfRegNum<[222]>; - def G5_4 : Rgg<4, "g5:4", [G4, G5]>, DwarfRegNum<[224]>; - def G7_6 : Rgg<6, "g7:6", [G6, G7]>, DwarfRegNum<[226]>; - def G9_8 : Rgg<8, "g9:8", [G8, G9]>, DwarfRegNum<[228]>; - def G11_10 : Rgg<10, "g11:10", [G10, G11]>, DwarfRegNum<[230]>; - def G13_12 : Rgg<12, "g13:12", [G12, G13]>, DwarfRegNum<[232]>; - def G15_14 : Rgg<14, "g15:14", [G14, G15]>, DwarfRegNum<[234]>; - def G17_16 : Rgg<16, "g17:16", [GPMUCNT4, GPMUCNT5]>, DwarfRegNum<[236]>; - def G19_18 : Rgg<18, "g19:18", [GPMUCNT6, GPMUCNT7]>, DwarfRegNum<[238]>; - def G21_20 : Rgg<20, "g21:20", [G20, G21]>, DwarfRegNum<[240]>; - def G23_22 : Rgg<22, "g23:22", [G22, G23]>, DwarfRegNum<[242]>; + def G1_0 : Rgg<0, "g1:0", [GELR, GSR]>, DwarfRegNum<[220]>; + def G3_2 : Rgg<2, "g3:2", [GOSP, G3]>, DwarfRegNum<[222]>; + def G5_4 : Rgg<4, "g5:4", [G4, G5]>, DwarfRegNum<[224]>; + def G7_6 : Rgg<6, "g7:6", [G6, G7]>, DwarfRegNum<[226]>; + def G9_8 : Rgg<8, "g9:8", [G8, G9]>, DwarfRegNum<[228]>; + def G11_10 : Rgg<10, "g11:10", [G10, G11]>, DwarfRegNum<[230]>; + def G13_12 : Rgg<12, "g13:12", [G12, G13]>, DwarfRegNum<[232]>; + def G15_14 : Rgg<14, "g15:14", [G14, G15]>, DwarfRegNum<[234]>; + def G17_16 : Rgg<16, "g17:16", [GPMUCNT4, GPMUCNT5]>, DwarfRegNum<[236]>; + def G19_18 : Rgg<18, "g19:18", [GPMUCNT6, GPMUCNT7]>, DwarfRegNum<[238]>; + def G21_20 : Rgg<20, "g21:20", [G20, G21]>, DwarfRegNum<[240]>; + def G23_22 : Rgg<22, "g23:22", [G22, G23]>, DwarfRegNum<[242]>; def G25_24 : Rgg<24, "g25:24", [GPCYCLELO, GPCYCLEHI]>, DwarfRegNum<[244]>; - def G27_26 : Rgg<26, "g27:26", [GPMUCNT0, GPMUCNT1]>, DwarfRegNum<[246]>; - def G29_28 : Rgg<28, "g29:28", [GPMUCNT2, GPMUCNT3]>, DwarfRegNum<[248]>; - def G31_30 : Rgg<30, "g31:30", [G30, G31]>, DwarfRegNum<[250]>; + def G27_26 : Rgg<26, "g27:26", [GPMUCNT0, GPMUCNT1]>, DwarfRegNum<[246]>; + def G29_28 : Rgg<28, "g29:28", [GPMUCNT2, GPMUCNT3]>, DwarfRegNum<[248]>; + def G31_30 : Rgg<30, "g31:30", [G30, G31]>, DwarfRegNum<[250]>; } - } // HVX types -def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v64i1, v128i1, v64i1]>; -def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v64i8, v128i8, v64i8]>; -def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v32i16, v64i16, v32i16]>; -def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v16i32, v32i32, v16i32]>; -def VecF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v32f16, v64f16, v32f16]>; -def VecF32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v16f32, v32f32, v16f32]>; - -def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v128i8, v256i8, v128i8]>; -def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v64i16, v128i16, v64i16]>; -def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v32i32, v64i32, v32i32]>; -def VecPF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v64f16, v128f16, v64f16]>; -def VecPF32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v32f32, v64f32, v32f32]>; - -def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v64i1, v128i1, v64i1]>; -def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v32i1, v64i1, v32i1]>; -def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v16i1, v32i1, v16i1]>; +def VecI1 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v64i1, v128i1, v64i1]>; +def VecI8 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v64i8, v128i8, v64i8]>; +def VecI16 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v32i16, v64i16, v32i16]>; +def VecI32 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v16i32, v32i32, v16i32]>; +def VecF16 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v32f16, v64f16, v32f16]>; +def VecF32 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v16f32, v32f32, v16f32]>; +def VecBF16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v32bf16, v64bf16, + v32bf16]>; + +def VecPI8 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v128i8, v256i8, v128i8]>; +def VecPI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v64i16, v128i16, + v64i16]>; +def VecPI32 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v32i32, v64i32, v32i32]>; +def VecPF16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v64f16, v128f16, + v64f16]>; +def VecPF32 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v32f32, v64f32, v32f32]>; +def VecPBF16 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v64bf16, v128bf16, + v64bf16]>; + +def VecQ8 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v64i1, v128i1, v64i1]>; +def VecQ16 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v32i1, v64i1, v32i1]>; +def VecQ32 + : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v16i1, v32i1, v16i1]>; // HVX register classes -def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32, VecF16, VecF32], 512, - (add (sequence "V%u", 0, 31), VTMP)> { - let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], - [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>; +def HvxVR + : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32, VecF16, VecBF16, VecF32], + 512, (add (sequence "V%u", 0, 31), VTMP)> { + let RegInfos = + RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], [RegInfo<512, 512, 512>, + RegInfo<1024, 1024, 1024>, + RegInfo<512, 512, 512>]>; } -def HvxWR : RegisterClass<"Hexagon", [VecPI8, VecPI16, VecPI32, VecPF16, VecPF32], 1024, - (add (sequence "W%u", 0, 15), (sequence "WR%u", 0, 15))> { - let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], - [RegInfo<1024,1024,512>, RegInfo<2048,2048,1024>, RegInfo<1024,1024,512>]>; +def HvxWR + : RegisterClass< + "Hexagon", [VecPI8, VecPI16, VecPI32, VecPF16, VecPBF16, VecPF32], + 1024, (add (sequence "W%u", 0, 15), (sequence "WR%u", 0, 15))> { + let RegInfos = + RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], [RegInfo<1024, 1024, 512>, + RegInfo<2048, 2048, 1024>, + RegInfo<1024, 1024, 512>]>; } def HvxQR : RegisterClass<"Hexagon", [VecI1, VecQ8, VecQ16, VecQ32], 128, - (add Q0, Q1, Q2, Q3)> { - let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], - [RegInfo<64,512,512>, RegInfo<128,1024,1024>, RegInfo<64,512,512>]>; + (add Q0, Q1, Q2, Q3)> { + let RegInfos = + RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], [RegInfo<64, 512, 512>, + RegInfo<128, 1024, 1024>, + RegInfo<64, 512, 512>]>; } -def HvxVQR : RegisterClass<"Hexagon", [untyped], 2048, - (add (sequence "VQ%u", 0, 7))> { - let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], - [RegInfo<2048,2048,512>, RegInfo<4096,4096,1024>, RegInfo<2048,2048,512>]>; +def HvxVQR + : RegisterClass<"Hexagon", [untyped], 2048, (add (sequence "VQ%u", 0, 7))> { + let RegInfos = + RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], [RegInfo<2048, 2048, 512>, + RegInfo<4096, 4096, 1024>, + RegInfo<2048, 2048, 512>]>; } // Core register classes -def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, - (add (sequence "R%u", 0, 9), (sequence "R%u", 12, 28), - R10, R11, R29, R30, R31)>; +def IntRegs + : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, + (add (sequence "R%u", 0, 9), (sequence "R%u", 12, 28), R10, + R11, R29, R30, R31)>; // Registers are listed in reverse order for allocation preference reasons. def GeneralSubRegs : RegisterClass<"Hexagon", [i32], 32, - (add R23, R22, R21, R20, R19, R18, R17, R16, - R7, R6, R5, R4, R3, R2, R1, R0)>; + (add R23, R22, R21, R20, R19, R18, R17, R16, + R7, R6, R5, R4, R3, R2, R1, R0)>; -def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32, - (add R7, R6, R5, R4, R3, R2, R1, R0)> ; +def IntRegsLow8 + : RegisterClass<"Hexagon", [i32], 32, (add R7, R6, R5, R4, R3, R2, R1, R0)>; def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, - (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>; - -def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64, - (add D11, D10, D9, D8, D3, D2, D1, D0)>; - -let Size = 32 in -def PredRegs : RegisterClass<"Hexagon", - [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>; - -let Size = 32 in -def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>; - -let Size = 32, isAllocatable = 0 in -def CtrRegs : RegisterClass<"Hexagon", [i32], 32, - (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1, - UPCYCLELO, UPCYCLEHI, - FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, UTIMERLO, UTIMERHI, - M0, M1, USR)>; - -let Size = 64 in -def VectRegRev : RegisterClass<"Hexagon", [i64], 64, - (add (sequence "WR%u", 0, 15))>; - -let isAllocatable = 0 in -def UsrBits : RegisterClass<"Hexagon", [i1], 0, (add USR_OVF)>; - -let Size = 64, isAllocatable = 0 in -def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64, - (add C1_0, C3_2, C5_4, C7_6, C9_8, C11_10, CS, UPCYCLE, C17_16, - PKTCOUNT, UTIMER)>; - -let Size = 32, isAllocatable = 0 in -def GuestRegs : RegisterClass<"Hexagon", [i32], 32, - (add GELR, GSR, GOSP, - (sequence "G%u", 3, 15), - GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7, - G20, G21, G22, G23, - GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1, - GPMUCNT2, GPMUCNT3, - G30, G31)>; - -let Size = 64, isAllocatable = 0 in -def GuestRegs64 : RegisterClass<"Hexagon", [i64], 64, - (add G1_0, G3_2, - G5_4, G7_6, G9_8, G11_10, G13_12, G15_14, - G17_16, G19_18, - G21_20, G23_22, - G25_24, G27_26, G29_28, - G31_30)>; - -let Size = 32, isAllocatable = 0 in -def SysRegs : RegisterClass<"Hexagon", [i32], 32, - (add SGP0, SGP1, STID, ELR, BADVA0, BADVA1, - SSR, CCR, HTID, BADVA, IMASK, - S11, S12, S13, S14, S15, - S19, S23, S25, - EVB, MODECTL, SYSCFG, S20, VID, S22, S24, - S26, CFGBASE, DIAG, REV, PCYCLEHI, - PCYCLELO, ISDBST, ISDBCFG0, ISDBCFG1, S35, - BRKPTPC0, BRKPTCFG0, BRKPTPC1, BRKPTCFG1, - ISDBMBXIN, ISDBMBXOUT, ISDBEN, ISDBGPR, - S44, S45, S46, S47, - PMUCNT0, PMUCNT1, PMUCNT2, PMUCNT3, - PMUEVTCFG, PMUCFG, S54, S55, S56, S57, - S58, S59, S60, S61, S62, S63, S64, S65, S66, S67, - S68, S69, S70, S71, S72, S73, S74, S75, S76, S77, - S78, S79, S80 - )>; - -let Size = 64, isAllocatable = 0 in -def SysRegs64 : RegisterClass<"Hexagon", [i64], 64, - (add SGP1_0, - S3_2, S5_4, S7_6, S9_8, - S11_10, S13_12, S15_14, - S17_16, S19_18, S21_20, - S23_22, S25_24, - S27_26, S29_28, S31_30, S33_32, S35_34, - S37_36, S39_38, S41_40, S43_42, S45_44, - S47_46, S49_48, S51_50, S53_52, - S55_54, S57_56, S59_58, - S61_60, S63_62, S65_64, S67_66, S69_68, - S71_70, S73_72, S75_74, S77_76, S79_78 - )>; + (add (sequence "D%u", 0, 4), + (sequence "D%u", 6, 13), D5, D14, D15)>; + +def GeneralDoubleLow8Regs + : RegisterClass<"Hexagon", [i64], 64, + (add D11, D10, D9, D8, D3, D2, D1, D0)>; + +let Size = 32 in def PredRegs + : RegisterClass<"Hexagon", [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, + (add P0, P1, P2, P3)>; + +let Size = + 32 in def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>; + +let Size = 32, isAllocatable = 0 in def CtrRegs + : RegisterClass<"Hexagon", [i32], 32, + (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, + CS1, UPCYCLELO, UPCYCLEHI, FRAMELIMIT, FRAMEKEY, + PKTCOUNTLO, PKTCOUNTHI, UTIMERLO, UTIMERHI, M0, M1, + USR)>; + +let Size = 64 in def VectRegRev + : RegisterClass<"Hexagon", [i64], 64, (add (sequence "WR%u", 0, 15))>; + +let isAllocatable = + 0 in def UsrBits : RegisterClass<"Hexagon", [i1], 0, (add USR_OVF)>; + +let Size = 64, isAllocatable = 0 in def CtrRegs64 + : RegisterClass<"Hexagon", [i64], 64, + (add C1_0, C3_2, C5_4, C7_6, C9_8, C11_10, CS, UPCYCLE, + C17_16, PKTCOUNT, UTIMER)>; + +let Size = 32, isAllocatable = 0 in def GuestRegs + : RegisterClass<"Hexagon", [i32], 32, + (add GELR, GSR, GOSP, (sequence "G%u", 3, 15), GPMUCNT4, + GPMUCNT5, GPMUCNT6, GPMUCNT7, G20, G21, G22, G23, + GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1, GPMUCNT2, + GPMUCNT3, G30, G31)>; + +let Size = 64, isAllocatable = 0 in def GuestRegs64 + : RegisterClass<"Hexagon", [i64], 64, + (add G1_0, G3_2, G5_4, G7_6, G9_8, G11_10, G13_12, G15_14, + G17_16, G19_18, G21_20, G23_22, G25_24, G27_26, G29_28, + G31_30)>; + +let Size = 32, isAllocatable = 0 in def SysRegs + : RegisterClass<"Hexagon", [i32], 32, + (add SGP0, SGP1, STID, ELR, BADVA0, BADVA1, SSR, CCR, HTID, + BADVA, IMASK, S11, S12, S13, S14, S15, S19, S23, S25, + EVB, MODECTL, SYSCFG, S20, VID, S22, S24, S26, CFGBASE, + DIAG, REV, PCYCLEHI, PCYCLELO, ISDBST, ISDBCFG0, + ISDBCFG1, S35, BRKPTPC0, BRKPTCFG0, BRKPTPC1, BRKPTCFG1, + ISDBMBXIN, ISDBMBXOUT, ISDBEN, ISDBGPR, S44, S45, S46, + S47, PMUCNT0, PMUCNT1, PMUCNT2, PMUCNT3, PMUEVTCFG, + PMUCFG, S54, S55, S56, S57, S58, S59, S60, S61, S62, + S63, S64, S65, S66, S67, S68, S69, S70, S71, S72, S73, + S74, S75, S76, S77, S78, S79, S80)>; + +let Size = 64, isAllocatable = 0 in def SysRegs64 + : RegisterClass<"Hexagon", [i64], 64, + (add SGP1_0, S3_2, S5_4, S7_6, S9_8, S11_10, S13_12, S15_14, + S17_16, S19_18, S21_20, S23_22, S25_24, S27_26, S29_28, + S31_30, S33_32, S35_34, S37_36, S39_38, S41_40, S43_42, + S45_44, S47_46, S49_48, S51_50, S53_52, S55_54, S57_56, + S59_58, S61_60, S63_62, S65_64, S67_66, S69_68, S71_70, + S73_72, S75_74, S77_76, S79_78)>; // These registers are new for v62 and onward. // The function RegisterMatchesArch() uses this list for validation. -let isAllocatable = 0 in -def V62Regs : RegisterClass<"Hexagon", [i32], 32, - (add FRAMELIMIT, FRAMEKEY, C17_16, PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT, - UTIMERLO, UTIMERHI, UTIMER)>; +let isAllocatable = 0 in def V62Regs + : RegisterClass<"Hexagon", [i32], 32, + (add FRAMELIMIT, FRAMEKEY, C17_16, PKTCOUNTLO, PKTCOUNTHI, + PKTCOUNT, UTIMERLO, UTIMERHI, UTIMER)>; // These registers are new for v65 and onward. -let Size = 32, isAllocatable = 0 in -def V65Regs : RegisterClass<"Hexagon", [i32], 32, (add VTMP)>; - +let Size = 32, isAllocatable = 0 in def V65Regs + : RegisterClass<"Hexagon", [i32], 32, (add VTMP)>; -def HexagonCSR - : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23, - R24, R25, R26, R27)>; +def HexagonCSR : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23, + R24, R25, R26, R27)>; diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index 30794f61218a1..5cf0995c66d78 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -343,10 +343,10 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo { ArrayRef getHVXElementTypes() const { static MVT Types[] = {MVT::i8, MVT::i16, MVT::i32}; - static MVT TypesV68[] = {MVT::i8, MVT::i16, MVT::i32, MVT::f16, MVT::f32}; + static MVT TypesV81[] = {MVT::i8, MVT::i16, MVT::i32, MVT::f16, MVT::bf16, MVT::f32}; - if (useHVXV68Ops() && useHVXFloatingPoint()) - return ArrayRef(TypesV68); + if (useHVXV81Ops() && useHVXFloatingPoint()) + return ArrayRef(TypesV81); return ArrayRef(Types); } diff --git a/llvm/test/CodeGen/Hexagon/bfloat.ll b/llvm/test/CodeGen/Hexagon/bfloat.ll new file mode 100644 index 0000000000000..550a2b54b2dea --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/bfloat.ll @@ -0,0 +1,186 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=hexagon -hexagon-bit=false < %s | FileCheck %s + +define bfloat @load_scalar_bf(ptr %addr) { +; CHECK-LABEL: load_scalar_bf: +; CHECK: .cfi_startproc +; CHECK-NEXT: // %bb.0: // %entry +; CHECK-NEXT: { +; CHECK-NEXT: [[REG:r[0-9]+]] = memuh(r0+#0) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r0 = aslh([[REG]]) +; CHECK-NEXT: jumpr r31 +; CHECK-NEXT: } + +entry: + %0 = load bfloat, ptr %addr, align 2 + ret bfloat %0 +} + +define void @store_scalar_bf(bfloat %v, ptr %addr) { +; CHECK-LABEL: store_scalar_bf: +; CHECK: .cfi_startproc +; CHECK-NEXT: // %bb.0: // %entry +; CHECK-NEXT: { +; CHECK-NEXT: [[R_A:r[0-9]+]] = ##131071 +; CHECK-NEXT: [[R_B:r[0-9]+]] = ##32768 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[R_C:r[0-9]+]] = ##65535 +; CHECK-NEXT: [[R_D:r[0-9]+]] = asrh(r0) +; CHECK-NEXT: [[R_A]] = and(r0,[[R_A]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[P0:p[0-9]+]] = sfclass(r0,#16) +; CHECK-NEXT: [[R_E:r[0-9]+]] = and(r0,[[R_B]]) +; CHECK-NEXT: [[P1:p[0-9]+]] = cmp.eq([[R_A]],[[R_B]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r0 = add(r0,[[R_E]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r0 = asrh(r0) +; CHECK-NEXT: if ([[P1]]) [[R_B]] = and([[R_D]],[[R_C]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: if (![[P1]]) [[R_B]] = and(r0,[[R_C]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: if ([[P0]]) [[R_B]] = ##32767 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: jumpr r31 +; CHECK-NEXT: memh(r1+#0) = [[R_B]] +; CHECK-NEXT: } + +entry: + store bfloat %v, ptr %addr, align 2 + ret void +} + +define bfloat @sum(bfloat %a, bfloat %b) #0 { +; CHECK-LABEL: sum: +; CHECK: .cfi_startproc +; CHECK-NEXT: // %bb.0: // %entry +; CHECK-NEXT: { +; CHECK-NEXT: [[R3:r[0-9]+]] = ##32768 +; CHECK-NEXT: [[R4:r[0-9]+]] = ##131071 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[R2:r[0-9]+]] = ##65535 +; CHECK-NEXT: [[R6:r[0-9]+]] = and(r0,[[R3]]) +; CHECK-NEXT: [[R5:r[0-9]+]] = and(r0,[[R4]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[R8:r[0-9]+]] = and(r1,[[R3]]) +; CHECK-NEXT: [[R7:r[0-9]+]] = and(r1,[[R4]]) +; CHECK-NEXT: [[R6]] = add(r0,[[R6]]) +; CHECK-NEXT: [[P0:p[0-9]+]] = cmp.eq([[R5]],[[R3]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[R5]] = asrh(r0) +; CHECK-NEXT: [[P1:p[0-9]+]] = cmp.eq([[R7]],[[R3]]) +; CHECK-NEXT: [[R7]] = asrh(r1) +; CHECK-NEXT: [[R8]] = add(r1,[[R8]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[R6]] = asrh([[R6]]) +; CHECK-NEXT: if ([[P0]]) [[R5]] = and([[R5]],[[R2]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[P0]] = sfclass(r0,#16) +; CHECK-NEXT: if (![[P0]]) [[R5]] = and([[R6]],[[R2]]) +; CHECK-NEXT: [[R6]] = asrh([[R8]]) +; CHECK-NEXT: if ([[P1]]) [[R7]] = and([[R7]],[[R2]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[P1]] = sfclass(r1,#16) +; CHECK-NEXT: [[R0:r[0-9]+]] = #32767 +; CHECK-NEXT: if (![[P1]]) [[R7]] = and([[R6]],[[R2]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: if ([[P0]]) [[R5]] = add([[R0]],#0) +; CHECK-NEXT: if ([[P1]]) [[R7]] = add([[R0]],#0) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[R6]] = aslh([[R7]]) +; CHECK-NEXT: [[R5]] = aslh([[R5]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[R1:r[0-9]+]] = sfadd([[R5]],[[R6]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[R5]] = and([[R1]],[[R3]]) +; CHECK-NEXT: [[R4]] = and([[R1]],[[R4]]) +; CHECK-NEXT: [[R6]] = asrh([[R1]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[P0]] = cmp.eq([[R4]],[[R3]]) +; CHECK-NEXT: [[R5]] = add([[R1]],[[R5]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[R3]] = asrh([[R5]]) +; CHECK-NEXT: if ([[P0]]) [[R4]] = and([[R6]],[[R2]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[P0]] = sfclass([[R1]],#16) +; CHECK-NEXT: if (![[P0]]) [[R4]] = and([[R3]],[[R2]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: if ([[P0]]) [[R4]] = add([[R0]],#0) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r0 = aslh([[R4]]) +; CHECK-NEXT: jumpr r31 +; CHECK-NEXT: } + +entry: + %add = fadd bfloat %a, %b + ret bfloat %add +} + +; Function Attrs: noinline nounwind optnone +define dso_local i32 @double_bf16(bfloat %a, bfloat %b) #0 { +; CHECK-LABEL: double_bf16: +; CHECK: .cfi_startproc +; CHECK-NEXT: // %bb.0: // %entry +; CHECK-NEXT: { +; CHECK-NEXT: [[PAIR_A:r[0-9]+:[0-9]+]] = convert_sf2df(r0) +; CHECK-NEXT: [[PAIR_B:r[0-9]+:[0-9]+]] = convert_sf2df(r1) +; CHECK-NEXT: [[SP:r[0-9]+]] = add([[SP]],#-16) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[RESULT:r[0-9]+:[0-9]+]] = dfadd([[PAIR_A]],[[PAIR_B]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: memd([[SP]]+#8) = [[RESULT]] +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[TMP:r[0-9]+]] = convert_df2sf([[RESULT]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[TMP1:r[0-9]+]] = lsr([[TMP]],#16) +; CHECK-NEXT: [[R0:r[0-9]+]] = and([[TMP]],##-65536) +; CHECK-NEXT: memh([[SP]]+#6) = [[TMP1]].new +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[R0]] = convert_sf2w([[R0]]):chop +; CHECK-NEXT: jumpr r31 +; CHECK-NEXT: [[SP]] = add([[SP]],#16) +; CHECK-NEXT: } + +entry: + %c = alloca double, align 8 + %d = alloca bfloat, align 2 + %conv = fpext bfloat %a to double + %conv1 = fpext bfloat %b to double + %add = fadd double %conv, %conv1 + store double %add, ptr %c, align 8 + %2 = load double, ptr %c, align 8 + %conv2 = fptrunc double %2 to bfloat + store bfloat %conv2, ptr %d, align 2 + %3 = load bfloat, ptr %d, align 2 + %conv3 = fptosi bfloat %3 to i32 + ret i32 %conv3 +} diff --git a/llvm/test/CodeGen/Hexagon/bfloat_vec.ll b/llvm/test/CodeGen/Hexagon/bfloat_vec.ll new file mode 100644 index 0000000000000..e9373d85e16d8 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/bfloat_vec.ll @@ -0,0 +1,116 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=hexagon --mattr=+hvx-length128b,+hvx-qfloat,+hvxv81,+v81 < %s | FileCheck %s + +; Function Attrs: mustprogress nounwind + +define dso_local void @bf16_vec_add(ptr noundef %c, ptr noundef %a, ptr noundef %b) local_unnamed_addr #0 { +; CHECK-LABEL: bf16_vec_add: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: { +; CHECK-NEXT: [[R7:r[0-9]+]] = #-4 +; CHECK-NEXT: [[V0:v[0-9]+]] = vmemu([[R2:r[0-9]+]]+#0) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[R2]] = ##32768 +; CHECK-NEXT: [[V1:v[0-9]+]] = vmemu([[R1:r[0-9]+]]+#0) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[R6:r[0-9]+]] = ##131071 +; CHECK-NEXT: [[V2:v[0-9]+]] = vxor([[V0]],[[V0]]) +; CHECK-NEXT: [[V3:v[0-9]+]] = vxor([[V1]],[[V1]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V25:v[0-9]+]] = vsplat([[R2]]) +; CHECK-NEXT: [[R5:r[0-9]+]] = #16 +; CHECK-NEXT: [[V5_4:v[0-9]+:[0-9]+]].h = vshuffoe([[V0]].h,[[V2]].h) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V26:v[0-9]+]] = vsplat([[R6]]) +; CHECK-NEXT: [[R4:r[0-9]+]] = #32767 +; CHECK-NEXT: [[V31_30:v[0-9]+:[0-9]+]].h = vshuffoe([[V1]].h,[[V3]].h) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V5_4]] = vshuff([[V5:v[0-9]+]],[[V4:v[0-9]+]],[[R7]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V31:v[0-9]+]].h = vsplat([[R4]]) +; CHECK-NEXT: [[V3_2:v[0-9]+:[0-9]+]] = vshuff([[V31]],[[V30:v[0-9]+]],[[R7]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V2]].qf32 = vadd([[V2]].sf,[[V4]].sf) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V3]].qf32 = vadd([[V3]].sf,[[V5]].sf) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V2]].sf = [[V2]].qf32 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V3]].sf = [[V3]].qf32 +; CHECK-NEXT: [[V27:v[0-9]+]] = vand([[V2]],[[V25]]) +; CHECK-NEXT: [[V28:v[0-9]+]] = vand([[V2]],[[V26]]) +; CHECK-NEXT: [[Q2:q[0-9]+]] = vcmp.eq([[V2]].sf,[[V2]].sf) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V29:v[0-9]+]] = vand([[V3]],[[V25]]) +; CHECK-NEXT: [[V1]] = vand([[V3]],[[V26]]) +; CHECK-NEXT: [[Q0:q[0-9]+]] = vcmp.eq([[V28]].w,[[V25]].w) +; CHECK-NEXT: [[V4]].w = vadd([[V2]].w,[[V27]].w) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V5]].w = vadd([[V3]].w,[[V29]].w) +; CHECK-NEXT: [[Q1:q[0-9]+]] = vcmp.eq([[V1]].w,[[V25]].w) +; CHECK-NEXT: [[V30:v[0-9]+]] = vmux([[Q0]],[[V2]],[[V4]]) +; CHECK-NEXT: [[Q3:q[0-9]+]] = vcmp.eq([[V3]].sf,[[V3]].sf) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V1]] = vmux([[Q1]],[[V3]],[[V5]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V0]].uw = vlsr([[V30]].uw,[[R5]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V1]].uw = vlsr([[V1]].uw,[[R5]]) +; CHECK-NEXT: [[V0]] = vmux([[Q2]],[[V0]],[[V31]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V1]] = vmux([[Q3]],[[V1]],[[V31]]) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: [[V0]].uh = vpack([[V1]].w,[[V0]].w):sat +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: jumpr [[R31:r[0-9]+]] +; CHECK-NEXT: vmemu([[R0:r[0-9]+]]+#0) = [[V0]] +; CHECK-NEXT: } + + +entry: + %0 = load <64 x bfloat>, ptr %a, align 2 + %1 = load <64 x bfloat>, ptr %b, align 2 + %add.ripple.vectorized = fadd <64 x bfloat> %0, %1 + store <64 x bfloat> %add.ripple.vectorized, ptr %c, align 2 + ret void +} + +define dso_local void @copy1d(ptr noundef readonly captures(none) %X, ptr noundef writeonly captures(none) %Y) local_unnamed_addr #0 { +; CHECK-LABEL: copy1d: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: { +; CHECK-NEXT: v0 = vmemu(r0+#1) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: v1 = vmemu(r0+#0) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: vmemu(r1+#1) = v0 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: jumpr r31 +; CHECK-NEXT: vmemu(r1+#0) = v1 +; CHECK-NEXT: } +entry: + %0 = load <128 x half>, ptr %X, align 2 + store <128 x half> %0, ptr %Y, align 2 + ret void +}