diff --git a/llvm/lib/Target/Mips/CMakeLists.txt b/llvm/lib/Target/Mips/CMakeLists.txt index 4a2277e9a80dc..726f0af0d8b0b 100644 --- a/llvm/lib/Target/Mips/CMakeLists.txt +++ b/llvm/lib/Target/Mips/CMakeLists.txt @@ -17,6 +17,7 @@ tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter) tablegen(LLVM MipsGenMCPseudoLowering.inc -gen-pseudo-lowering) tablegen(LLVM MipsGenRegisterBank.inc -gen-register-bank) tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info) +tablegen(LLVM MipsGenSDNodeInfo.inc -gen-sd-node-info) tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget) tablegen(LLVM MipsGenExegesis.inc -gen-exegesis) diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td index fead376b8c338..199d210f2f65b 100644 --- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td @@ -22,6 +22,7 @@ def SDT_MipsFSelect : SDTypeProfile<1, 3, [SDTCisFP<1>, SDTCisSameAs<0,2>, SDTCisSameAs<2,3>]>; +// Floating point select def MipsFSelect : SDNode<"MipsISD::FSELECT", SDT_MipsFSelect>; //===----------------------------------------------------------------------===// @@ -1225,4 +1226,3 @@ let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, GPR32Opnd>, ISA_MIPS32R6; } - diff --git a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td index 9498cd015ba3c..bad7d504271af 100644 --- a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td @@ -32,8 +32,12 @@ def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisVT<2, untyped>]>; def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>; -def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, - SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; +def SDT_MipsDPA_H : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, + SDTCisVT<1, v4i8>, SDTCisSameAs<1, 2>]>; +def SDT_MipsDPA_W : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, + SDTCisVT<1, v2i16>, SDTCisSameAs<1, 2>]>; +def SDT_MipsDPA_L : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, + SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>; @@ -43,6 +47,7 @@ class MipsDSPBase : class MipsDSPSideEffectBase : SDNode; +// EXTR.W intrinsic nodes. def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>; def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>; def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>; @@ -53,40 +58,45 @@ def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>; def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>; def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>; -def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>; -def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>; -def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>; -def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>; -def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>; - -def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>; -def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>; -def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>; -def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>; -def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>; -def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>; -def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>; -def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>; - -def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>; -def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>; -def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>; -def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>; -def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>; -def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>; -def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>; -def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>; -def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>; - -def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>; -def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>; -def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>; -def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>; -def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>; -def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>; +// DPA.W intrinsic nodes. +def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA_W>; +def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA_W>; +def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA_W>; +def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA_W>; +def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA_W>; + +def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA_H>; +def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA_H>; +def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA_H>; +def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA_H>; +def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA_W>; +def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA_W>; +def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA_L>; +def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA_L>; + +def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA_W>; +def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA_W>; +def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA_W>; +def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA_W>; +def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA_W>; +def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA_W>; +def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA_W>; +def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA_W>; +def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA_W>; + +def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA_L>; +def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA_L>; +def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA_L>; +def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA_L>; +def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA_L>; +def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA_L>; + +// DSP shift nodes. def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>; def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>; def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>; + +// DSP setcc and select_cc nodes. def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>; def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>; @@ -464,12 +474,12 @@ class WRDSP_DESC_BASE { +class DPA_DESC_BASE { dag OutOperandList = (outs ACC64DSPOpnd:$ac); - dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin); + dag InOperandList = (ins DSPROpnd:$rs, DSPROpnd:$rt, ACC64DSPOpnd:$acin); string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); list Pattern = [(set ACC64DSPOpnd:$ac, - (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))]; + (OpNode VT:$rs, VT:$rt, ACC64DSPOpnd:$acin))]; string Constraints = "$acin = $ac"; string BaseOpcode = instr_asm; } @@ -762,20 +772,20 @@ class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph, NoItinerary, DSPROpnd, DSPROpnd>, IsCommutable, Defs<[DSPOutFlag21]>; -class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph", - MipsMULSAQ_S_W_PH>, +class MULSAQ_S_W_PH_DESC : DPA_DESC_BASE<"mulsaq_s.w.ph", + MipsMULSAQ_S_W_PH, v2i16>, Defs<[DSPOutFlag16_19]>; -class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>, +class MAQ_S_W_PHL_DESC : DPA_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL, v2i16>, Defs<[DSPOutFlag16_19]>; -class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>, +class MAQ_S_W_PHR_DESC : DPA_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR, v2i16>, Defs<[DSPOutFlag16_19]>; -class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>, +class MAQ_SA_W_PHL_DESC : DPA_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL, v2i16>, Defs<[DSPOutFlag16_19]>; -class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>, +class MAQ_SA_W_PHR_DESC : DPA_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR, v2i16>, Defs<[DSPOutFlag16_19]>; // Move from/to hi/lo. @@ -785,24 +795,24 @@ class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>; class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>; // Dot product with accumulate/subtract -class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>; +class DPAU_H_QBL_DESC : DPA_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL, v4i8>; -class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>; +class DPAU_H_QBR_DESC : DPA_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR, v4i8>; -class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>; +class DPSU_H_QBL_DESC : DPA_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL, v4i8>; -class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>; +class DPSU_H_QBR_DESC : DPA_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR, v4i8>; -class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>, +class DPAQ_S_W_PH_DESC : DPA_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH, v2i16>, Defs<[DSPOutFlag16_19]>; -class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>, +class DPSQ_S_W_PH_DESC : DPA_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH, v2i16>, Defs<[DSPOutFlag16_19]>; -class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>, +class DPAQ_SA_L_W_DESC : DPA_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W, i32>, Defs<[DSPOutFlag16_19]>; -class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>, +class DPSQ_SA_L_W_DESC : DPA_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W, i32>, Defs<[DSPOutFlag16_19]>; class MULT_DSP_DESC : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>; @@ -1034,29 +1044,29 @@ class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph, IsCommutable, Defs<[DSPOutFlag21]>; // Dot product with accumulate/subtract -class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>; +class DPA_W_PH_DESC : DPA_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH, v2i16>; -class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>; +class DPS_W_PH_DESC : DPA_DESC_BASE<"dps.w.ph", MipsDPS_W_PH, v2i16>; -class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>, +class DPAQX_S_W_PH_DESC : DPA_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH, v2i16>, Defs<[DSPOutFlag16_19]>; -class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph", - MipsDPAQX_SA_W_PH>, +class DPAQX_SA_W_PH_DESC : DPA_DESC_BASE<"dpaqx_sa.w.ph", + MipsDPAQX_SA_W_PH, v2i16>, Defs<[DSPOutFlag16_19]>; -class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>; +class DPAX_W_PH_DESC : DPA_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH, v2i16>; -class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>; +class DPSX_W_PH_DESC : DPA_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH, v2i16>; -class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>, +class DPSQX_S_W_PH_DESC : DPA_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH, v2i16>, Defs<[DSPOutFlag16_19]>; -class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph", - MipsDPSQX_SA_W_PH>, +class DPSQX_SA_W_PH_DESC : DPA_DESC_BASE<"dpsqx_sa.w.ph", + MipsDPSQX_SA_W_PH, v2i16>, Defs<[DSPOutFlag16_19]>; -class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>; +class MULSA_W_PH_DESC : DPA_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH, v2i16>; // Precision reduce/expand class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph", diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 2fd73275721b1..a0bca0448655f 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -171,128 +171,6 @@ SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, N->getOffset(), Flag); } -const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { - switch ((MipsISD::NodeType)Opcode) { - case MipsISD::FIRST_NUMBER: break; - case MipsISD::JmpLink: return "MipsISD::JmpLink"; - case MipsISD::TailCall: return "MipsISD::TailCall"; - case MipsISD::Highest: return "MipsISD::Highest"; - case MipsISD::Higher: return "MipsISD::Higher"; - case MipsISD::Hi: return "MipsISD::Hi"; - case MipsISD::Lo: return "MipsISD::Lo"; - case MipsISD::GotHi: return "MipsISD::GotHi"; - case MipsISD::TlsHi: return "MipsISD::TlsHi"; - case MipsISD::GPRel: return "MipsISD::GPRel"; - case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; - case MipsISD::Ret: return "MipsISD::Ret"; - case MipsISD::ERet: return "MipsISD::ERet"; - case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; - case MipsISD::FAbs: return "MipsISD::FAbs"; - case MipsISD::FMS: return "MipsISD::FMS"; - case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; - case MipsISD::FPCmp: return "MipsISD::FPCmp"; - case MipsISD::FSELECT: return "MipsISD::FSELECT"; - case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; - case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; - case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; - case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; - case MipsISD::MFHI: return "MipsISD::MFHI"; - case MipsISD::MFLO: return "MipsISD::MFLO"; - case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; - case MipsISD::Mult: return "MipsISD::Mult"; - case MipsISD::Multu: return "MipsISD::Multu"; - case MipsISD::MAdd: return "MipsISD::MAdd"; - case MipsISD::MAddu: return "MipsISD::MAddu"; - case MipsISD::MSub: return "MipsISD::MSub"; - case MipsISD::MSubu: return "MipsISD::MSubu"; - case MipsISD::DivRem: return "MipsISD::DivRem"; - case MipsISD::DivRemU: return "MipsISD::DivRemU"; - case MipsISD::DivRem16: return "MipsISD::DivRem16"; - case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; - case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; - case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; - case MipsISD::Wrapper: return "MipsISD::Wrapper"; - case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; - case MipsISD::Sync: return "MipsISD::Sync"; - case MipsISD::Ext: return "MipsISD::Ext"; - case MipsISD::Ins: return "MipsISD::Ins"; - case MipsISD::CIns: return "MipsISD::CIns"; - case MipsISD::LWL: return "MipsISD::LWL"; - case MipsISD::LWR: return "MipsISD::LWR"; - case MipsISD::SWL: return "MipsISD::SWL"; - case MipsISD::SWR: return "MipsISD::SWR"; - case MipsISD::LDL: return "MipsISD::LDL"; - case MipsISD::LDR: return "MipsISD::LDR"; - case MipsISD::SDL: return "MipsISD::SDL"; - case MipsISD::SDR: return "MipsISD::SDR"; - case MipsISD::EXTP: return "MipsISD::EXTP"; - case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; - case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; - case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; - case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; - case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; - case MipsISD::SHILO: return "MipsISD::SHILO"; - case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; - case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; - case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; - case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; - case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; - case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; - case MipsISD::DOUBLE_SELECT_I: return "MipsISD::DOUBLE_SELECT_I"; - case MipsISD::DOUBLE_SELECT_I64: return "MipsISD::DOUBLE_SELECT_I64"; - case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; - case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; - case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; - case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; - case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; - case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; - case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; - case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; - case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; - case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; - case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; - case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; - case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; - case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; - case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; - case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; - case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; - case MipsISD::MULT: return "MipsISD::MULT"; - case MipsISD::MULTU: return "MipsISD::MULTU"; - case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; - case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; - case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; - case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; - case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; - case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; - case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; - case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; - case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; - case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; - case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; - case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; - case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; - case MipsISD::VCEQ: return "MipsISD::VCEQ"; - case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; - case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; - case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; - case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; - case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; - case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; - case MipsISD::VNOR: return "MipsISD::VNOR"; - case MipsISD::VSHF: return "MipsISD::VSHF"; - case MipsISD::SHF: return "MipsISD::SHF"; - case MipsISD::ILVEV: return "MipsISD::ILVEV"; - case MipsISD::ILVOD: return "MipsISD::ILVOD"; - case MipsISD::ILVL: return "MipsISD::ILVL"; - case MipsISD::ILVR: return "MipsISD::ILVR"; - case MipsISD::PCKEV: return "MipsISD::PCKEV"; - case MipsISD::PCKOD: return "MipsISD::PCKOD"; - case MipsISD::INSVE: return "MipsISD::INSVE"; - } - return nullptr; -} - MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI) : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h index 25a0bf9b797d5..7d1d8ff4cd128 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.h +++ b/llvm/lib/Target/Mips/MipsISelLowering.h @@ -18,6 +18,7 @@ #include "MCTargetDesc/MipsBaseInfo.h" #include "MCTargetDesc/MipsMCTargetDesc.h" #include "Mips.h" +#include "MipsSelectionDAGInfo.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/CodeGen/MachineMemOperand.h" @@ -50,217 +51,6 @@ class MipsTargetMachine; class TargetLibraryInfo; class TargetRegisterClass; - namespace MipsISD { - - enum NodeType : unsigned { - // Start the numbering from where ISD NodeType finishes. - FIRST_NUMBER = ISD::BUILTIN_OP_END, - - // Jump and link (call) - JmpLink, - - // Tail call - TailCall, - - // Get the Highest (63-48) 16 bits from a 64-bit immediate - Highest, - - // Get the Higher (47-32) 16 bits from a 64-bit immediate - Higher, - - // Get the High 16 bits from a 32/64-bit immediate - // No relation with Mips Hi register - Hi, - - // Get the Lower 16 bits from a 32/64-bit immediate - // No relation with Mips Lo register - Lo, - - // Get the High 16 bits from a 32 bit immediate for accessing the GOT. - GotHi, - - // Get the High 16 bits from a 32-bit immediate for accessing TLS. - TlsHi, - - // Handle gp_rel (small data/bss sections) relocation. - GPRel, - - // Thread Pointer - ThreadPointer, - - // Vector Floating Point Multiply and Subtract - FMS, - - // Floating Point Branch Conditional - FPBrcond, - - // Floating Point Compare - FPCmp, - - // Floating point Abs - FAbs, - - // Floating point select - FSELECT, - - // Node used to generate an MTC1 i32 to f64 instruction - MTC1_D64, - - // Floating Point Conditional Moves - CMovFP_T, - CMovFP_F, - - // FP-to-int truncation node. - TruncIntFP, - - // Return - Ret, - - // Interrupt, exception, error trap Return - ERet, - - // Software Exception Return. - EH_RETURN, - - // Node used to extract integer from accumulator. - MFHI, - MFLO, - - // Node used to insert integers to accumulator. - MTLOHI, - - // Mult nodes. - Mult, - Multu, - - // MAdd/Sub nodes - MAdd, - MAddu, - MSub, - MSubu, - - // DivRem(u) - DivRem, - DivRemU, - DivRem16, - DivRemU16, - - BuildPairF64, - ExtractElementF64, - - Wrapper, - - DynAlloc, - - Sync, - - Ext, - Ins, - CIns, - - // EXTR.W intrinsic nodes. - EXTP, - EXTPDP, - EXTR_S_H, - EXTR_W, - EXTR_R_W, - EXTR_RS_W, - SHILO, - MTHLIP, - - // DPA.W intrinsic nodes. - MULSAQ_S_W_PH, - MAQ_S_W_PHL, - MAQ_S_W_PHR, - MAQ_SA_W_PHL, - MAQ_SA_W_PHR, - DPAU_H_QBL, - DPAU_H_QBR, - DPSU_H_QBL, - DPSU_H_QBR, - DPAQ_S_W_PH, - DPSQ_S_W_PH, - DPAQ_SA_L_W, - DPSQ_SA_L_W, - DPA_W_PH, - DPS_W_PH, - DPAQX_S_W_PH, - DPAQX_SA_W_PH, - DPAX_W_PH, - DPSX_W_PH, - DPSQX_S_W_PH, - DPSQX_SA_W_PH, - MULSA_W_PH, - - MULT, - MULTU, - MADD_DSP, - MADDU_DSP, - MSUB_DSP, - MSUBU_DSP, - - // DSP shift nodes. - SHLL_DSP, - SHRA_DSP, - SHRL_DSP, - - // DSP setcc and select_cc nodes. - SETCC_DSP, - SELECT_CC_DSP, - - // Vector comparisons. - // These take a vector and return a boolean. - VALL_ZERO, - VANY_ZERO, - VALL_NONZERO, - VANY_NONZERO, - - // These take a vector and return a vector bitmask. - VCEQ, - VCLE_S, - VCLE_U, - VCLT_S, - VCLT_U, - - // Vector Shuffle with mask as an operand - VSHF, // Generic shuffle - SHF, // 4-element set shuffle. - ILVEV, // Interleave even elements - ILVOD, // Interleave odd elements - ILVL, // Interleave left elements - ILVR, // Interleave right elements - PCKEV, // Pack even elements - PCKOD, // Pack odd elements - - // Vector Lane Copy - INSVE, // Copy element from one vector to another - - // Combined (XOR (OR $a, $b), -1) - VNOR, - - // Extended vector element extraction - VEXTRACT_SEXT_ELT, - VEXTRACT_ZEXT_ELT, - - // Double select nodes for machines without conditional-move. - DOUBLE_SELECT_I, - DOUBLE_SELECT_I64, - - // Load/Store Left/Right nodes. - FIRST_MEMORY_OPCODE, - LWL = FIRST_MEMORY_OPCODE, - LWR, - SWL, - SWR, - LDL, - LDR, - SDL, - SDR, - LAST_MEMORY_OPCODE = SDR, - }; - - } // ene namespace MipsISD - //===--------------------------------------------------------------------===// // TargetLowering Implementation //===--------------------------------------------------------------------===// @@ -330,10 +120,6 @@ class TargetRegisterClass; void ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results, SelectionDAG &DAG) const override; - /// getTargetNodeName - This method returns the name of a target specific - // DAG node. - const char *getTargetNodeName(unsigned Opcode) const override; - /// getSetCCResultType - get the ISD::SETCC result ValueType EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override; diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index 4ca329d214981..e2c7e721b75a6 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -41,17 +41,26 @@ def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, def SDT_MipsMTC1_D64 : SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisVT<1, i32>]>; +// Floating Point Compare def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; + +// Floating Point Conditional Moves def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; + +// Floating Point Branch Conditional def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, [SDNPHasChain, SDNPOptInGlue]>; + +// FP-to-int truncation node. def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; + def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; def : GINodeEquiv; def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", SDT_MipsExtractElementF64>; +// Node used to generate an MTC1 i32 to f64 instruction def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>; // Operand for printing out a condition code. diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 21d8dedbf51f9..e4d81986eb47d 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -47,7 +47,7 @@ def SDTMipsLoadLR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisSameAs<0, 2>]>; -// Call +// Jump and link (call) def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; @@ -63,26 +63,37 @@ def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, // Hi is the odd node out, on MIPS64 it can expand to either daddiu when // using static relocations with 64 bit symbols, or lui when using 32 bit // symbols. +// Get the Higher (47-32) 16 bits from a 64-bit immediate def MipsHigher : SDNode<"MipsISD::Higher", SDTIntUnaryOp>; + +// Get the Highest (63-48) 16 bits from a 64-bit immediate def MipsHighest : SDNode<"MipsISD::Highest", SDTIntUnaryOp>; + +// Get the High 16 bits from a 32/64-bit immediate +// No relation with Mips Hi register def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; + +// Get the Lower 16 bits from a 32/64-bit immediate +// No relation with Mips Lo register def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; +// Handle gp_rel (small data/bss sections) relocation. def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; -// Hi node for accessing the GOT. +// Get the High 16 bits from a 32 bit immediate for accessing the GOT. def MipsGotHi : SDNode<"MipsISD::GotHi", SDTIntUnaryOp>; -// Hi node for handling TLS offsets +// Get the High 16 bits from a 32-bit immediate for accessing TLS. def MipsTlsHi : SDNode<"MipsISD::TlsHi", SDTIntUnaryOp>; -// Thread pointer +// Thread Pointer def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; // Return def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; +// Interrupt, exception, error trap Return def MipsERet : SDNode<"MipsISD::ERet", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPSideEffect]>; @@ -136,6 +147,7 @@ def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; def MipsCIns : SDNode<"MipsISD::CIns", SDT_Ext>; +// Load/Store Left/Right nodes. def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, @@ -2333,6 +2345,7 @@ def PseudoReturn : PseudoReturnBase; // the offset and return address respectively. def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; +// Software Exception Return. def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td index 621612ebfb04b..bf1d8933f0e0c 100644 --- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td @@ -30,26 +30,38 @@ def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, SDTCisSameAs<0, 3>, SDTCisVT<4, i32>]>; +// Vector comparisons. +// These take a vector and return a boolean. def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; + +// Combined (XOR (OR $a, $b), -1) def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; -def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; -def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; -def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; -def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; -def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; -def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; -def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; -def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; + +// Vector Shuffle with mask as an operand +def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; // Generic shuffle +def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; // 4-element set shuffle. +def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; // Interleave even elements +def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; // Interleave odd elements +def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; // Interleave left elements +def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; // Interleave right elements +def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; // Pack even elements +def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; // Pack odd elements + +// Vector Lane Copy +// Copy element from one vector to another def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>; + +// Vector Floating Point Multiply and Subtract def MipsFMS : SDNode<"MipsISD::FMS", SDTFPTernaryOp>; def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>; def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>; +// Extended vector element extraction def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT", SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td index 80ff119be37d5..7b9c7ac043802 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.td +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td @@ -315,7 +315,7 @@ def GPR32NONZERO : RegisterClass<"Mips", [i32], 32, (add // Reserved K0, K1, GP, SP, FP, RA)>; -def DSPR : GPR32Class<[v4i8, v2i16]>; +def DSPR : GPR32Class<[v4i8, v2i16, i32]>; def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add // Callee save diff --git a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp index 6497ac5bb2df6..d216624fd3934 100644 --- a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp @@ -7,13 +7,40 @@ //===----------------------------------------------------------------------===// #include "MipsSelectionDAGInfo.h" -#include "MipsISelLowering.h" + +#define GET_SDNODE_DESC +#include "MipsGenSDNodeInfo.inc" using namespace llvm; +MipsSelectionDAGInfo::MipsSelectionDAGInfo() + : SelectionDAGGenTargetInfo(MipsGenSDNodeInfo) {} + MipsSelectionDAGInfo::~MipsSelectionDAGInfo() = default; -bool MipsSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const { - return Opcode >= MipsISD::FIRST_MEMORY_OPCODE && - Opcode <= MipsISD::LAST_MEMORY_OPCODE; +const char *MipsSelectionDAGInfo::getTargetNodeName(unsigned Opcode) const { + // These nodes don't have corresponding entries in *.td files yet. + switch (static_cast(Opcode)) { + // clang-format off + case MipsISD::FAbs: return "MipsISD::FAbs"; + case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; + case MipsISD::DOUBLE_SELECT_I: return "MipsISD::DOUBLE_SELECT_I"; + case MipsISD::DOUBLE_SELECT_I64: return "MipsISD::DOUBLE_SELECT_I64"; + // clang-format on + } + + return SelectionDAGGenTargetInfo::getTargetNodeName(Opcode); +} + +void MipsSelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG, + const SDNode *N) const { + switch (N->getOpcode()) { + default: + break; + case MipsISD::ERet: + // invalid number of operands; expected at most 2, got 3 + return; + } + + SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N); } diff --git a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h index 934cd2e056595..6b3682648b575 100644 --- a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h +++ b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h @@ -11,13 +11,35 @@ #include "llvm/CodeGen/SelectionDAGTargetInfo.h" +#define GET_SDNODE_ENUM +#include "MipsGenSDNodeInfo.inc" + namespace llvm { +namespace MipsISD { + +enum NodeType : unsigned { + // Floating point Abs + FAbs = GENERATED_OPCODE_END, + + DynAlloc, + + // Double select nodes for machines without conditional-move. + DOUBLE_SELECT_I, + DOUBLE_SELECT_I64, +}; + +} // namespace MipsISD -class MipsSelectionDAGInfo : public SelectionDAGTargetInfo { +class MipsSelectionDAGInfo : public SelectionDAGGenTargetInfo { public: + MipsSelectionDAGInfo(); + ~MipsSelectionDAGInfo() override; - bool isTargetMemoryOpcode(unsigned Opcode) const override; + const char *getTargetNodeName(unsigned Opcode) const override; + + void verifyTargetNode(const SelectionDAG &DAG, + const SDNode *N) const override; }; } // namespace llvm