From 75f844d3235f6f5f62f24b2665aac530921ce579 Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra Date: Tue, 18 Nov 2025 15:22:47 +0000 Subject: [PATCH 1/4] [LV] Pre-commit crashing induction-wrapflags test From Alexey Bataev. --- .../LoopVectorize/induction-wrapflags.ll | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll diff --git a/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll b/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll new file mode 100644 index 0000000000000..d9e474748f95f --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll @@ -0,0 +1,24 @@ +; RUN: not --crash opt -p loop-vectorize -force-vector-width=4 -S %s + +define void @induction_with_multiple_instructions_in_chain(ptr %p, ptr noalias %q) { +entry: + br label %loop + +loop: + %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] + %ind.1 = phi i32 [ %ind.1.next, %loop ], [ 3, %entry ] + %ind.2 = phi i32 [ %ind.1, %loop ], [ 0, %entry ] + %sext.1 = sext i32 %ind.1 to i64 + %gep.1 = getelementptr i8, ptr %p, i64 %sext.1 + store i8 0, ptr %gep.1 + %sext.2 = sext i32 %ind.2 to i64 + %gep.2 = getelementptr i8, ptr %q, i64 %sext.2 + store i8 0, ptr %gep.2 + %iv.next = add i64 %iv, 1 + %ind.1.next = add i32 %ind.1, 3 + %ec = icmp eq i64 %iv, 1024 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} From 7eb1da31396d6f82b805ddf13e164731c4683299 Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra Date: Tue, 18 Nov 2025 15:26:06 +0000 Subject: [PATCH 2/4] [VPlan] Fix OpType-mismatch in getFlagsFromIndDesc Follow up on a cse OpType-mismatch crash reported due to ef023cae388d (Reland [VPlan] Expand WidenInt inductions with nuw/nsw), setting the OpType correctly when returning from getFlagsFromIndDesc. --- llvm/lib/Transforms/Vectorize/VPlanUtils.h | 2 +- .../LoopVectorize/induction-wrapflags.ll | 48 ++++++++++++++++++- 2 files changed, 48 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.h b/llvm/lib/Transforms/Vectorize/VPlanUtils.h index 38073380eb54c..f59dd46755b54 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanUtils.h +++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.h @@ -90,7 +90,7 @@ inline VPIRFlags getFlagsFromIndDesc(const InductionDescriptor &ID) { ID.getInductionBinOp())) return VPIRFlags::WrapFlagsTy(OBO->hasNoUnsignedWrap(), OBO->hasNoSignedWrap()); - return {}; + return VPIRFlags::WrapFlagsTy(false, false); } } // namespace vputils diff --git a/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll b/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll index d9e474748f95f..584f9b572927b 100644 --- a/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll +++ b/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll @@ -1,6 +1,52 @@ -; RUN: not --crash opt -p loop-vectorize -force-vector-width=4 -S %s +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "^scalar.ph" --version 6 +; RUN: opt -p loop-vectorize -force-vector-width=4 -S %s | FileCheck %s define void @induction_with_multiple_instructions_in_chain(ptr %p, ptr noalias %q) { +; CHECK-LABEL: define void @induction_with_multiple_instructions_in_chain( +; CHECK-SAME: ptr [[P:%.*]], ptr noalias [[Q:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: br label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND1:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT2:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = sext <4 x i32> [[VEC_IND]] to <4 x i64> +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i64> [[TMP0]], i32 0 +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i64> [[TMP0]], i32 1 +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[TMP0]], i32 2 +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i64> [[TMP0]], i32 3 +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP4]] +; CHECK-NEXT: store i8 0, ptr [[TMP5]], align 1 +; CHECK-NEXT: store i8 0, ptr [[TMP6]], align 1 +; CHECK-NEXT: store i8 0, ptr [[TMP7]], align 1 +; CHECK-NEXT: store i8 0, ptr [[TMP8]], align 1 +; CHECK-NEXT: [[TMP9:%.*]] = sext <4 x i32> [[VEC_IND1]] to <4 x i64> +; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i64> [[TMP9]], i32 0 +; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i64> [[TMP9]], i32 1 +; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i64> [[TMP9]], i32 2 +; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i64> [[TMP9]], i32 3 +; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP10]] +; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP11]] +; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP12]] +; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP13]] +; CHECK-NEXT: store i8 0, ptr [[TMP14]], align 1 +; CHECK-NEXT: store i8 0, ptr [[TMP15]], align 1 +; CHECK-NEXT: store i8 0, ptr [[TMP16]], align 1 +; CHECK-NEXT: store i8 0, ptr [[TMP17]], align 1 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 12) +; CHECK-NEXT: [[VEC_IND_NEXT2]] = add <4 x i32> [[VEC_IND1]], splat (i32 12) +; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 +; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: br label %[[SCALAR_PH:.*]] +; CHECK: [[SCALAR_PH]]: +; entry: br label %loop From 41ce4790b83278451d1ce7ce047c3597b9cf928f Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra Date: Tue, 18 Nov 2025 16:14:54 +0000 Subject: [PATCH 3/4] [LV] NFC test improvement --- llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll b/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll index 584f9b572927b..f16a1b258c3e5 100644 --- a/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll +++ b/llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll @@ -51,9 +51,9 @@ entry: br label %loop loop: - %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] - %ind.1 = phi i32 [ %ind.1.next, %loop ], [ 3, %entry ] - %ind.2 = phi i32 [ %ind.1, %loop ], [ 0, %entry ] + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %ind.1 = phi i32 [ 3, %entry ], [ %ind.1.next, %loop ] + %ind.2 = phi i32 [ 0, %entry ], [ %ind.1, %loop ] %sext.1 = sext i32 %ind.1 to i64 %gep.1 = getelementptr i8, ptr %p, i64 %sext.1 store i8 0, ptr %gep.1 From 55b13f1100d0867d365b5d38e6fa3705de960d8a Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra Date: Tue, 18 Nov 2025 18:40:40 +0000 Subject: [PATCH 4/4] [VPlan] Add assert --- llvm/lib/Transforms/Vectorize/VPlanUtils.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.h b/llvm/lib/Transforms/Vectorize/VPlanUtils.h index f59dd46755b54..6f74a99f3738e 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanUtils.h +++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.h @@ -90,6 +90,9 @@ inline VPIRFlags getFlagsFromIndDesc(const InductionDescriptor &ID) { ID.getInductionBinOp())) return VPIRFlags::WrapFlagsTy(OBO->hasNoUnsignedWrap(), OBO->hasNoSignedWrap()); + + assert(ID.getKind() == InductionDescriptor::IK_IntInduction && + "Expected int induction"); return VPIRFlags::WrapFlagsTy(false, false); } } // namespace vputils