diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index cfc8a4243e894..05833f97bc035 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -1754,8 +1754,8 @@ class ConstantSDNode : public SDNode { const ConstantInt *Value; ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, - SDVTList VTs) - : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(), + SDVTList VTs, const DebugLoc &DL) + : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DL, VTs), Value(val) { assert(!isa(val->getType()) && "Unexpected vector type!"); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 16fdef06d6679..5502bddbc3ba7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1773,7 +1773,7 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, const SDLoc &DL, return SDValue(N, 0); if (!N) { - N = newSDNode(isT, isO, Elt, VTs); + N = newSDNode(isT, isO, Elt, VTs, DL.getDebugLoc()); CSEMap.InsertNode(N, IP); InsertNode(N); NewSDValueDbgMsg(SDValue(N, 0), "Creating constant: ", this); diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp index 10762edc16264..355b97cdb9ee8 100644 --- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp +++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp @@ -1179,16 +1179,17 @@ void SIWholeQuadMode::toExact(MachineBasicBlock &MBB, } } + const DebugLoc &DL = MBB.findDebugLoc(Before); MachineInstr *MI; if (SaveWQM) { unsigned Opcode = IsTerminator ? LMC.AndSaveExecTermOpc : LMC.AndSaveExecOpc; - MI = BuildMI(MBB, Before, DebugLoc(), TII->get(Opcode), SaveWQM) + MI = BuildMI(MBB, Before, DL, TII->get(Opcode), SaveWQM) .addReg(LiveMaskReg); } else { unsigned Opcode = IsTerminator ? LMC.AndTermOpc : LMC.AndOpc; - MI = BuildMI(MBB, Before, DebugLoc(), TII->get(Opcode), LMC.ExecReg) + MI = BuildMI(MBB, Before, DL, TII->get(Opcode), LMC.ExecReg) .addReg(LMC.ExecReg) .addReg(LiveMaskReg); } @@ -1200,13 +1201,14 @@ void SIWholeQuadMode::toExact(MachineBasicBlock &MBB, void SIWholeQuadMode::toWQM(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before, Register SavedWQM) { + const DebugLoc &DL = MBB.findDebugLoc(Before); MachineInstr *MI; if (SavedWQM) { - MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), LMC.ExecReg) + MI = BuildMI(MBB, Before, DL, TII->get(AMDGPU::COPY), LMC.ExecReg) .addReg(SavedWQM); } else { - MI = BuildMI(MBB, Before, DebugLoc(), TII->get(LMC.WQMOpc), LMC.ExecReg) + MI = BuildMI(MBB, Before, DL, TII->get(LMC.WQMOpc), LMC.ExecReg) .addReg(LMC.ExecReg); } @@ -1222,12 +1224,14 @@ void SIWholeQuadMode::toStrictMode(MachineBasicBlock &MBB, assert(StrictStateNeeded == StateStrictWWM || StrictStateNeeded == StateStrictWQM); + const DebugLoc &DL = MBB.findDebugLoc(Before); + if (StrictStateNeeded == StateStrictWWM) { - MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::ENTER_STRICT_WWM), + MI = BuildMI(MBB, Before, DL, TII->get(AMDGPU::ENTER_STRICT_WWM), SaveOrig) .addImm(-1); } else { - MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::ENTER_STRICT_WQM), + MI = BuildMI(MBB, Before, DL, TII->get(AMDGPU::ENTER_STRICT_WQM), SaveOrig) .addImm(-1); } @@ -1245,12 +1249,14 @@ void SIWholeQuadMode::fromStrictMode(MachineBasicBlock &MBB, assert(CurrentStrictState == StateStrictWWM || CurrentStrictState == StateStrictWQM); + const DebugLoc &DL = MBB.findDebugLoc(Before); + if (CurrentStrictState == StateStrictWWM) { - MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::EXIT_STRICT_WWM), + MI = BuildMI(MBB, Before, DL, TII->get(AMDGPU::EXIT_STRICT_WWM), LMC.ExecReg) .addReg(SavedOrig); } else { - MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::EXIT_STRICT_WQM), + MI = BuildMI(MBB, Before, DL, TII->get(AMDGPU::EXIT_STRICT_WQM), LMC.ExecReg) .addReg(SavedOrig); }