From c30f626d1f5b2eb09135c1f8d7b43f73c7378665 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 18 Nov 2025 10:21:21 -0800 Subject: [PATCH] [GISel] Use getScalarSizeInBits in LegalizerHelper::lowerBitCount For vectors, CTLZ, CTTZ, CTPOP all operate on individual elements. The lowering should be based on the element width. I noticed this by inspection. No tests in tree are currently affected, but I thought it would be good to fix so someone doesn't have to debug it in the future. --- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index ba28e4dda3313..8a9a297805583 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -7609,7 +7609,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI) { } case TargetOpcode::G_CTLZ: { auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs(); - unsigned Len = SrcTy.getSizeInBits(); + unsigned Len = SrcTy.getScalarSizeInBits(); if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) { // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero. @@ -7657,7 +7657,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI) { case TargetOpcode::G_CTTZ: { auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs(); - unsigned Len = SrcTy.getSizeInBits(); + unsigned Len = SrcTy.getScalarSizeInBits(); if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) { // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with // zero. @@ -7695,7 +7695,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI) { case TargetOpcode::G_CTPOP: { Register SrcReg = MI.getOperand(1).getReg(); LLT Ty = MRI.getType(SrcReg); - unsigned Size = Ty.getSizeInBits(); + unsigned Size = Ty.getScalarSizeInBits(); MachineIRBuilder &B = MIRBuilder; // Count set bits in blocks of 2 bits. Default approach would be