From 14e0816b8db278e20ff20fc53944a928d201683e Mon Sep 17 00:00:00 2001
From: Petr Penzin <ppenzin@tenstorrent.com>
Date: Wed, 19 Nov 2025 18:44:39 -0600
Subject: [PATCH] [RISCV] Add segmented tunes to tt-ascalon-d8

Add TuneOptimizedNFnSegmentedLoadStore tune flags to tt-ascalon-d8
processor definition.
---
 llvm/lib/Target/RISCV/RISCVProcessors.td | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index e86431f78f1ba..07f6a38c77897 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -633,6 +633,13 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
                                                   FeatureUnalignedVectorMem]),
                                                  [TuneNoDefaultUnroll,
                                                   TuneNLogNVRGather,
+                                                  TuneOptimizedNF2SegmentLoadStore,
+                                                  TuneOptimizedNF3SegmentLoadStore,
+                                                  TuneOptimizedNF4SegmentLoadStore,
+                                                  TuneOptimizedNF5SegmentLoadStore,
+                                                  TuneOptimizedNF6SegmentLoadStore,
+                                                  TuneOptimizedNF7SegmentLoadStore,
+                                                  TuneOptimizedNF8SegmentLoadStore,
                                                   TuneOptimizedZeroStrideLoad,
                                                   TunePostRAScheduler]>;