From cb626e47044d7a193ffea66279458d1da5b4ff58 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Thu, 20 Nov 2025 10:36:08 -0800
Subject: [PATCH] [RISCV] Only add v2i32 to GPR regclass in the RV64 hardware
 mode.

Removes about 200 bytes of unneeded patterns from RISCVGenDAGISel.inc
---
 llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 87095e75d5dc4..11b7a0a3c691a 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -228,6 +228,8 @@ def XLenVecI8VT : ValueTypeByHwMode<[RV32, RV64],
                                     [v4i8, v8i8]>;
 def XLenVecI16VT : ValueTypeByHwMode<[RV32,  RV64],
                                      [v2i16, v4i16]>;
+def XLenVecI32VT : ValueTypeByHwMode<[RV64],
+                                     [v2i32]>;
 def XLenRI : RegInfoByHwMode<
       [RV32,              RV64],
       [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
@@ -246,7 +248,7 @@ class RISCVRegisterClass<list<ValueType> regTypes, int align, dag regList>
 class GPRRegisterClass<dag regList>
     : RISCVRegisterClass<[XLenVT, XLenFVT,
                           // P extension packed vector types:
-                          XLenVecI8VT, XLenVecI16VT, v2i32], 32, regList> {
+                          XLenVecI8VT, XLenVecI16VT, XLenVecI32VT], 32, regList> {
   let RegInfos = XLenRI;
 }