From 0642f737e020ed7957f93f7ec4350b537851ef30 Mon Sep 17 00:00:00 2001 From: Justin Fargnoli Date: Fri, 21 Nov 2025 01:56:13 +0000 Subject: [PATCH] [NVPTX] Fix `mul.wide` operand type when matching on `shl` in `combineMulWide` --- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 3ac7c2874408b..19fab430883b6 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -5705,8 +5705,8 @@ static SDValue combineMulWide(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SDValue RHS = Op.getOperand(1); if (Op.getOpcode() == ISD::SHL) { const auto ShiftAmt = Op.getConstantOperandVal(1); - const auto MulVal = APInt(ToVT.getSizeInBits(), 1) << ShiftAmt; - RHS = DCI.DAG.getConstant(MulVal, DL, ToVT); + const auto MulVal = APInt(FromVT.getSizeInBits(), 1) << ShiftAmt; + RHS = DCI.DAG.getConstant(MulVal, DL, FromVT); } return DCI.DAG.getNode(Opcode, DL, ToVT, Op.getOperand(0), RHS); }