From c9741cf1bd3ba347089f000652a118678ddc3a95 Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Mon, 24 Nov 2025 17:26:11 -0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q?itial=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.8-beta.1 --- .../ValueTypeByHwModeMissingRegInfo.td | 30 +++++++++++++++++++ .../TableGen/Common/CodeGenRegisters.cpp | 4 +-- 2 files changed, 32 insertions(+), 2 deletions(-) create mode 100644 llvm/test/TableGen/ValueTypeByHwModeMissingRegInfo.td diff --git a/llvm/test/TableGen/ValueTypeByHwModeMissingRegInfo.td b/llvm/test/TableGen/ValueTypeByHwModeMissingRegInfo.td new file mode 100644 index 0000000000000..e34a7ffb8a4d3 --- /dev/null +++ b/llvm/test/TableGen/ValueTypeByHwModeMissingRegInfo.td @@ -0,0 +1,30 @@ +// RUN: not llvm-tblgen -gen-asm-matcher -I %p/../../include %s -o - 2>&1 | FileCheck %s + +include "llvm/Target/Target.td" + +def Is32Bit : Predicate<"!Subtarget->is64Bit()">; +def Is64Bit : Predicate<"Subtarget->is64Bit()">; +defvar Ptr32 = DefaultMode; +def Ptr64 : HwMode<[Is64Bit]>; + +class MyReg : Register { + let Namespace = "MyTarget"; +} + +def X0 : MyReg<"x0">; +def X1 : MyReg<"x1">; +def X2 : MyReg<"x2">; +def X3 : MyReg<"x3">; + +def XLenVT : ValueTypeByHwMode<[Ptr32, Ptr64], [i32, i64]>; +def XLenRI : RegInfoByHwMode<[Ptr32, Ptr64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; + +def XRegs : RegisterClass<"MyTarget", [XLenVT], 32, (add X0, X1, X2, X3)> { + // Note: Would need this to determine size, otherwise we get an error. + // let RegInfos = XLenRI; +} +// CHECK: [[#@LINE-4]]:5: error: Impossible to determine register size + +def MyTargetISA : InstrInfo; +def MyTarget : Target { let InstructionSet = MyTargetISA; } diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp index 2f0ff3f59c47c..446163eb52772 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp @@ -734,8 +734,8 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, if (const Record *RV = R->getValueAsOptionalDef("RegInfos")) RSI = RegSizeInfoByHwMode(RV, RegBank.getHwModes()); unsigned Size = R->getValueAsInt("Size"); - assert((RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) && - "Impossible to determine register size"); + if (!(RSI.hasDefault() || Size != 0 || VTs[0].isSimple())) + PrintFatalError(R->getLoc(), "Impossible to determine register size"); if (!RSI.hasDefault()) { RegSizeInfo RI; RI.RegSize = RI.SpillSize = From 7e1a03de9a9e3ff59c3d765e3cd22e8305c9f23d Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Mon, 24 Nov 2025 18:45:47 -0800 Subject: [PATCH 2/2] fix condition Created using spr 1.3.8-beta.1 --- llvm/utils/TableGen/Common/CodeGenRegisters.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp index 446163eb52772..e853303c37aff 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp @@ -734,7 +734,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, if (const Record *RV = R->getValueAsOptionalDef("RegInfos")) RSI = RegSizeInfoByHwMode(RV, RegBank.getHwModes()); unsigned Size = R->getValueAsInt("Size"); - if (!(RSI.hasDefault() || Size != 0 || VTs[0].isSimple())) + if (!RSI.hasDefault() && Size == 0 && !VTs[0].isSimple()) PrintFatalError(R->getLoc(), "Impossible to determine register size"); if (!RSI.hasDefault()) { RegSizeInfo RI;