diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 0125580fc28bd..526250a04e001 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -326,7 +326,7 @@ def mfma_f32_32x32x64_f8f6f4 : UnscaledMFMAOptimizationPat { - bit ret = !and(SrcVT.isInteger, !ne(SrcVT.Value, i1.Value)); + bit ret = !and(SrcVT.isInteger, !ne(SrcVT, i1)); } def SDTSBufferPrefetch : SDTypeProfile<0, 3, @@ -1787,10 +1787,10 @@ class SIMCInstr { class getNumSrcArgs { int ret = - !if (!eq(Src0.Value, untyped.Value), 0, - !if (!eq(Src1.Value, untyped.Value), 1, // VOP1 - !if (!eq(Src2.Value, untyped.Value), 2, // VOP2 - 3))); // VOP3 + !if (!eq(Src0, untyped), 0, + !if (!eq(Src1, untyped), 1, // VOP1 + !if (!eq(Src2, untyped), 2, // VOP2 + 3))); // VOP3 } // Returns the register class to use for the destination of VOP[123C] @@ -1859,17 +1859,17 @@ class getVCSrcForVT { !if(VT.isFP, !if(!eq(VT.Size, 64), VCSrc_f64, - !cond(!eq(VT.Value, f16.Value) : VCSrc_f16, - !eq(VT.Value, bf16.Value) : VCSrc_bf16, - !eq(VT.Value, v2f16.Value) : VCSrc_v2f16, - !eq(VT.Value, v2bf16.Value) : VCSrc_v2bf16, + !cond(!eq(VT, f16) : VCSrc_f16, + !eq(VT, bf16) : VCSrc_bf16, + !eq(VT, v2f16) : VCSrc_v2f16, + !eq(VT, v2bf16) : VCSrc_v2bf16, 1 : VCSrc_f32) ), !if(!eq(VT.Size, 64), VCSrc_b64, - !if(!eq(VT.Value, i16.Value), + !if(!eq(VT, i16), VCSrc_b16, - !if(!eq(VT.Value, v2i16.Value), + !if(!eq(VT, v2i16), VCSrc_v2b16, VCSrc_b32 ) @@ -1994,28 +1994,28 @@ class getVOP3DPPSrcForVT { // Float or packed int class isModifierType { - bit ret = !or(!eq(SrcVT.Value, f16.Value), - !eq(SrcVT.Value, bf16.Value), - !eq(SrcVT.Value, f32.Value), - !eq(SrcVT.Value, f64.Value), - !eq(SrcVT.Value, v2f16.Value), - !eq(SrcVT.Value, v2i16.Value), - !eq(SrcVT.Value, v2bf16.Value), - !eq(SrcVT.Value, v2f32.Value), - !eq(SrcVT.Value, v2i32.Value), - !eq(SrcVT.Value, v4f16.Value), - !eq(SrcVT.Value, v4i16.Value), - !eq(SrcVT.Value, v4bf16.Value), - !eq(SrcVT.Value, v4f32.Value), - !eq(SrcVT.Value, v4i32.Value), - !eq(SrcVT.Value, v8f16.Value), - !eq(SrcVT.Value, v8i16.Value), - !eq(SrcVT.Value, v8bf16.Value), - !eq(SrcVT.Value, v8f32.Value), - !eq(SrcVT.Value, v8i32.Value), - !eq(SrcVT.Value, v16f16.Value), - !eq(SrcVT.Value, v16i16.Value), - !eq(SrcVT.Value, v16bf16.Value)); + bit ret = !or(!eq(SrcVT, f16), + !eq(SrcVT, bf16), + !eq(SrcVT, f32), + !eq(SrcVT, f64), + !eq(SrcVT, v2f16), + !eq(SrcVT, v2i16), + !eq(SrcVT, v2bf16), + !eq(SrcVT, v2f32), + !eq(SrcVT, v2i32), + !eq(SrcVT, v4f16), + !eq(SrcVT, v4i16), + !eq(SrcVT, v4bf16), + !eq(SrcVT, v4f32), + !eq(SrcVT, v4i32), + !eq(SrcVT, v8f16), + !eq(SrcVT, v8i16), + !eq(SrcVT, v8bf16), + !eq(SrcVT, v8f32), + !eq(SrcVT, v8i32), + !eq(SrcVT, v16f16), + !eq(SrcVT, v16i16), + !eq(SrcVT, v16bf16)); } // Return type of input modifiers operand for specified input operand. @@ -2048,9 +2048,9 @@ class getSrcModDPP { class getSrcModDPP_t16 { Operand ret = !if (VT.isFP, - !if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), + !if (!or(!eq(VT, f16), !eq(VT, bf16)), FPT16_Lo128VRegInputMods, FPVRegInputMods), - !if (!eq(VT.Value, i16.Value), + !if (!eq(VT, i16), IntT16_Lo128VRegInputMods, IntVRegInputMods)); } @@ -2059,11 +2059,11 @@ class getSrcModDPP_t16 { class getSrcModVOP3VC { Operand ret = !if (VT.isFP, - !if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), + !if (!or(!eq(VT, f16), !eq(VT, bf16)), FPT16VCSrcInputMods, - !if (!eq(VT.Value, f64.Value), FP64VCSrcInputMods, + !if (!eq(VT, f64), FP64VCSrcInputMods, FP32VCSrcInputMods)), - !if (!eq(VT.Value, i16.Value), + !if (!eq(VT, i16), IntT16VCSrcInputMods, Int32VCSrcInputMods)); } @@ -2075,15 +2075,15 @@ class getSrcModVOP3VC { class getSrc0ModVOP3DPP { defvar T16Dst = !if (VT.isFP, - !if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), + !if (!or(!eq(VT, f16), !eq(VT, bf16)), FPT16VRegInputMods, FPVRegT16DstInputMods), - !if (!eq(VT.Value, i16.Value), IntT16VRegInputMods, + !if (!eq(VT, i16), IntT16VRegInputMods, IntVRegT16DstInputMods)); defvar Normal = !if (VT.isFP, - !if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), + !if (!or(!eq(VT, f16), !eq(VT, bf16)), FPT16VRegInputMods, FPVRegInputMods), - !if (!eq(VT.Value, i16.Value), + !if (!eq(VT, i16), IntT16VRegInputMods, IntVRegInputMods)); Operand ret = !if(!and(!not(IsFake16), !eq(DstVT.Size, 16)), T16Dst, Normal); @@ -2093,16 +2093,16 @@ class getSrc0ModVOP3DPP { // only operands (VOPD3 vsrc1 and vsrc2). class getSrcModVOP3V { Operand ret = - !if (!eq(VT.Value, f64.Value), FP64VRegSrcInputMods, + !if (!eq(VT, f64), FP64VRegSrcInputMods, FP32VRegSrcInputMods); } // Return type of input modifiers operand specified input operand for SDWA class getSrcModSDWA { - Operand ret = !if(!eq(VT.Value, f16.Value), FP16SDWAInputMods, - !if(!eq(VT.Value, f32.Value), FP32SDWAInputMods, - !if(!eq(VT.Value, i16.Value), Int16SDWAInputMods, - !if(!eq(VT.Value, bf16.Value), FP16SDWAInputMods, + Operand ret = !if(!eq(VT, f16), FP16SDWAInputMods, + !if(!eq(VT, f32), FP32SDWAInputMods, + !if(!eq(VT, i16), Int16SDWAInputMods, + !if(!eq(VT, bf16), FP16SDWAInputMods, Int32SDWAInputMods)))); } @@ -2769,14 +2769,14 @@ class VOPProfile _ArgVT, bit _EnableClamp = 0> { field bit HasFP8ByteSel = !or(HasFP8SrcByteSel, HasFP8DstByteSel); field bit HasBitOp3 = 0; - field bit HasDst = !ne(DstVT.Value, untyped.Value); + field bit HasDst = !ne(DstVT, untyped); field bit HasDst32 = HasDst; field bit EmitDst = HasDst; // force dst encoding, see v_movreld_b32 special case field bit EmitDstSel = EmitDst; field int NumSrcArgs = getNumSrcArgs.ret; - field bit HasSrc0 = !ne(Src0VT.Value, untyped.Value); - field bit HasSrc1 = !ne(Src1VT.Value, untyped.Value); - field bit HasSrc2 = !ne(Src2VT.Value, untyped.Value); + field bit HasSrc0 = !ne(Src0VT, untyped); + field bit HasSrc1 = !ne(Src1VT, untyped); + field bit HasSrc2 = !ne(Src2VT, untyped); field bit HasSrc0FloatMods = Src0VT.isFP; field bit HasSrc1FloatMods = Src1VT.isFP; diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index 872bde501cd2d..faab9f3062829 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -151,7 +151,7 @@ class getInterp16Ins ArgVT, bit OpSel = 0> : VOPProfile { let IsSingle = 1; - let HasOMod = !ne(DstVT.Value, f16.Value); + let HasOMod = !ne(DstVT, f16); let HasHigh = 1; let HasOpSel = OpSel;