From 8e3d9c43d02397047512455b866ccab6e400d498 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Tue, 25 Nov 2025 21:44:36 -0800 Subject: [PATCH] [RISCV] Rename SFB Base Feature New SFB subsets are being added with the scheduler class name as a suffix, so now is the time to go back to the base extension and add IALU to its name. This also: - Drops a hyphen from the other SFB features for mul and minmax, to more closely match their scheduling classes. - Updates the predicates on specific SFB pseudos so we get verifier errors if we introduce the pseudos when we don't have the right subtarget feature. - Updates the SFB Documentation comment to make it no longer SiFive-specific. --- llvm/lib/Target/RISCV/RISCVFeatures.td | 47 ++++++++++++++----- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 8 ++-- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 4 +- llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td | 25 ++++++---- llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 4 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 4 +- llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 +- .../Analysis/CostModel/RISCV/cmp-select.ll | 2 +- llvm/test/CodeGen/RISCV/cmov-branch-opt.ll | 8 ++-- llvm/test/CodeGen/RISCV/features-info.ll | 6 +-- llvm/test/CodeGen/RISCV/min-max.ll | 6 +-- llvm/test/CodeGen/RISCV/select-bare.ll | 2 +- llvm/test/CodeGen/RISCV/select-cc.ll | 2 +- llvm/test/CodeGen/RISCV/select-cond.ll | 2 +- llvm/test/CodeGen/RISCV/select-const.ll | 2 +- llvm/test/CodeGen/RISCV/select.ll | 2 +- .../RISCV/short-forward-branch-load-imm.ll | 4 +- .../RISCV/short-forward-branch-opt-min-max.ll | 8 ++-- .../RISCV/short-forward-branch-opt-mul.ll | 8 ++-- llvm/test/CodeGen/RISCV/xqcicli.ll | 2 +- llvm/test/CodeGen/RISCV/xqcicm.ll | 2 +- llvm/test/CodeGen/RISCV/xqcics.ll | 2 +- 23 files changed, 90 insertions(+), 64 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index bf1caafc2f9ba..4fc776fcdeb9a 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1850,23 +1850,44 @@ def TuneNoDefaultUnroll : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false", "Disable default unroll preference.">; -// SiFive 7 is able to fuse integer ALU operations with a preceding branch -// instruction. -def TuneShortForwardBranchOpt - : SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt", - "true", "Enable short forward branch optimization">; -def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">; -def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">; +// Many Microarchitectures are able to fuse a branch over a single instruction +// with the branched-over instruction. We call this fusion "short forward +// branches". +// +// We can do this for a variety of instruction groups, depending on the +// microarch. We broadly group these by their scheduler class: +// - IALU: RVI Integer instructions, plus ANDN/ORN/XNOR (Zbb/Zbkb) +// - IMinMax: Zbb MIN(U)/MAX(U) +// - IMul: MUL +// +// We make the simplifying assumption that any microarches that implement +// any "short forward branches" can do the IALU fusions, and can opt into +// the other fusions they implement. +// +// The important Pseudo used by all these instructions requires the IALU +// short forward branches. +// +// Vendor-specific short-forward-branch opts may be added under IALU, as +// the vendor-specific instructions should only be enabled for vendor +// cores. +def TuneShortForwardBranchIALU + : SubtargetFeature<"short-forward-branch-ialu", "HasShortForwardBranchIALU", + "true", "Enable short forward branch optimization for RVI base instructions">; +def HasShortForwardBranchIALU : Predicate<"Subtarget->hasShortForwardBranchIALU()">; +def NoShortForwardBranch : Predicate<"!Subtarget->hasShortForwardBranchIALU()">; def TuneShortForwardBranchIMinMax - : SubtargetFeature<"short-forward-branch-i-minmax", "HasShortForwardBranchIMinMax", - "true", "Enable short forward branch optimization for min,max instructions in Zbb", - [TuneShortForwardBranchOpt]>; + : SubtargetFeature<"short-forward-branch-iminmax", "HasShortForwardBranchIMinMax", + "true", "Enable short forward branch optimization for MIN,MAX instructions in Zbb", + [TuneShortForwardBranchIALU]>; +def HasShortForwardBranchIMinMax : Predicate<"Subtarget->hasShortForwardBranchIMinMax()">; def TuneShortForwardBranchIMul - : SubtargetFeature<"short-forward-branch-i-mul", "HasShortForwardBranchIMul", - "true", "Enable short forward branch optimization for mul instruction", - [TuneShortForwardBranchOpt]>; + : SubtargetFeature<"short-forward-branch-imul", "HasShortForwardBranchIMul", + "true", "Enable short forward branch optimization for MUL instruction", + [TuneShortForwardBranchIALU]>; +def HasShortForwardBranchIMul : Predicate<"Subtarget->hasShortForwardBranchIMul()">; + // Some subtargets require a S2V transfer buffer to move scalars into vectors. // FIXME: Forming .vx/.vf/.wx/.wf can reduce register pressure. diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 3b250d7d9ad1f..c22a2e11322eb 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -453,7 +453,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::ABS, XLenVT, Legal); if (Subtarget.is64Bit()) setOperationAction(ISD::ABS, MVT::i32, Custom); - } else if (Subtarget.hasShortForwardBranchOpt()) { + } else if (Subtarget.hasShortForwardBranchIALU()) { // We can use PseudoCCSUB to implement ABS. setOperationAction(ISD::ABS, XLenVT, Legal); } else if (Subtarget.is64Bit()) { @@ -9480,7 +9480,7 @@ static SDValue lowerSelectToBinOp(SDNode *N, SelectionDAG &DAG, static SDValue foldBinOpIntoSelectIfProfitable(SDNode *BO, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { - if (Subtarget.hasShortForwardBranchOpt()) + if (Subtarget.hasShortForwardBranchIALU()) return SDValue(); unsigned SelOpNo = 0; @@ -20944,7 +20944,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, // (select (x < 0), y, z) -> x >> (XLEN - 1) & (y - z) + z // (select (x >= 0), y, z) -> x >> (XLEN - 1) & (z - y) + y - if (!Subtarget.hasShortForwardBranchOpt() && isa(TrueV) && + if (!Subtarget.hasShortForwardBranchIALU() && isa(TrueV) && isa(FalseV) && isNullConstant(RHS) && (CCVal == ISD::CondCode::SETLT || CCVal == ISD::CondCode::SETGE)) { if (CCVal == ISD::CondCode::SETGE) @@ -25522,7 +25522,7 @@ RISCVTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor, return SDValue(N, 0); // Lower SDIV as SDIV // Only perform this transform if short forward branch opt is supported. - if (!Subtarget.hasShortForwardBranchOpt()) + if (!Subtarget.hasShortForwardBranchIALU()) return SDValue(); EVT VT = N->getValueType(0); if (!(VT == MVT::i32 || (VT == MVT::i64 && Subtarget.is64Bit()))) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 9d3663cb72ecd..89ec4a2a4a3e1 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1821,7 +1821,7 @@ bool RISCVInstrInfo::analyzeSelect(const MachineInstr &MI, Cond.push_back(MI.getOperand(2)); Cond.push_back(MI.getOperand(3)); // We can only fold when we support short forward branch opt. - Optimizable = STI.hasShortForwardBranchOpt(); + Optimizable = STI.hasShortForwardBranchIALU(); return false; } @@ -1831,7 +1831,7 @@ RISCVInstrInfo::optimizeSelect(MachineInstr &MI, bool PreferFalse) const { assert(MI.getOpcode() == RISCV::PseudoCCMOVGPR && "Unknown select instruction"); - if (!STI.hasShortForwardBranchOpt()) + if (!STI.hasShortForwardBranchIALU()) return nullptr; MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td index 5b1c13493bbf2..6563cc27ecb76 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td @@ -10,7 +10,7 @@ // //===----------------------------------------------------------------------===// -let Predicates = [HasShortForwardBranchOpt], isSelect = 1, +let Predicates = [HasShortForwardBranchIALU], isSelect = 1, Constraints = "$dst = $falsev", isCommutable = 1, Size = 8 in { // This instruction moves $truev to $dst when the condition is true. It will // be expanded to control flow in RISCVExpandPseudoInsts. @@ -28,7 +28,7 @@ def PseudoCCMOVGPR : Pseudo<(outs GPR:$dst), // This should always expand to a branch+c.mv so the size is 6 or 4 if the // branch is compressible. -let Predicates = [HasConditionalMoveFusion, NoShortForwardBranchOpt], +let Predicates = [HasConditionalMoveFusion, NoShortForwardBranch], Constraints = "$dst = $falsev", isCommutable = 1, Size = 6 in { // This instruction moves $truev to $dst when the condition is true. It will // be expanded to control flow in RISCVExpandPseudoInsts. @@ -108,7 +108,7 @@ class SFBShiftW_ri // is true. Returns $falsev otherwise. Selected by optimizeSelect. // TODO: Can we use DefaultOperands on the regular binop to accomplish this more // like how ARM does predication? -let Predicates = [HasShortForwardBranchOpt] in { +let Predicates = [HasShortForwardBranchIALU] in { def PseudoCCADD : SFBALU_rr; def PseudoCCSUB : SFBALU_rr; def PseudoCCSLL : SFBALU_rr; @@ -117,11 +117,6 @@ def PseudoCCSRA : SFBALU_rr; def PseudoCCAND : SFBALU_rr; def PseudoCCOR : SFBALU_rr; def PseudoCCXOR : SFBALU_rr; -def PseudoCCMAX : SFBALU_rr; -def PseudoCCMIN : SFBALU_rr; -def PseudoCCMAXU : SFBALU_rr; -def PseudoCCMINU : SFBALU_rr; -def PseudoCCMUL : SFBALU_rr; def PseudoCCADDI : SFBALU_ri; def PseudoCCANDI : SFBALU_ri; @@ -153,11 +148,21 @@ def PseudoCCORN : SFBALU_rr; def PseudoCCXNOR : SFBALU_rr; } -let Predicates = [HasShortForwardBranchOpt] in +let Predicates = [HasShortForwardBranchIALU] in def : Pat<(XLenVT (abs GPR:$rs1)), (PseudoCCSUB (XLenVT GPR:$rs1), (XLenVT X0), /* COND_LT */ 2, (XLenVT GPR:$rs1), (XLenVT X0), (XLenVT GPR:$rs1))>; -let Predicates = [HasShortForwardBranchOpt, IsRV64] in +let Predicates = [HasShortForwardBranchIALU, IsRV64] in def : Pat<(sext_inreg (abs 33signbits_node:$rs1), i32), (PseudoCCSUBW (i64 GPR:$rs1), (i64 X0), /* COND_LT */ 2, (i64 GPR:$rs1), (i64 X0), (i64 GPR:$rs1))>; + +let Predicates = [HasShortForwardBranchIMinMax] in { +def PseudoCCMAX : SFBALU_rr; +def PseudoCCMIN : SFBALU_rr; +def PseudoCCMAXU : SFBALU_rr; +def PseudoCCMINU : SFBALU_rr; +} + +let Predicates = [HasShortForwardBranchIMul] in +def PseudoCCMUL : SFBALU_rr; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td index b683e895c31c0..8a8b4953a9c12 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td @@ -914,7 +914,7 @@ defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotsu", "PseudoNDS_VD4DOTSU", // Pseudo-instructions for SFB (Short Forward Branch) //===----------------------------------------------------------------------===// -let Predicates = [HasShortForwardBranchOpt], hasSideEffects = 0, +let Predicates = [HasShortForwardBranchIALU], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, Constraints = "$dst = $falsev" in { def PseudoCCNDS_BFOS : Pseudo<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 8a38fe2f5ae16..13ceead2d28b4 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -1330,7 +1330,7 @@ def PseudoQC_E_SH : PseudoStore<"qc.e.sh">; def PseudoQC_E_SW : PseudoStore<"qc.e.sw">; } // Predicates = [HasVendorXqcilo, IsRV32] -let Predicates = [HasShortForwardBranchOpt] in { +let Predicates = [HasShortForwardBranchIALU] in { def PseudoCCQC_LI : SFBQC_LI; def PseudoCCQC_E_LI : SFBQC_E_LI; } @@ -1571,7 +1571,7 @@ def: Pat<(i32 (ctlz (not (i32 GPR:$rs1)))), (QC_CLO GPR:$rs1)>; let Predicates = [HasVendorXqciint, IsRV32] in def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>; -let Predicates = [HasVendorXqcicm, NoShortForwardBranchOpt, IsRV32] in { +let Predicates = [HasVendorXqcicm, NoShortForwardBranch, IsRV32] in { def : QCIMVCCPat; def : QCIMVCCPat; def : QCIMVCCPat; diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 07f6a38c77897..5becfd2ad502b 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -141,7 +141,7 @@ def ROCKET : RISCVTuneProcessorModel<"rocket", RocketModel>; defvar SiFive7TuneFeatures = [TuneSiFive7, TuneNoDefaultUnroll, - TuneShortForwardBranchOpt, + TuneShortForwardBranchIALU, TunePostRAScheduler]; def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series", SiFive7Model, SiFive7TuneFeatures>; @@ -805,7 +805,7 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25", defvar Andes45TuneFeatures = [TuneAndes45, TuneNoDefaultUnroll, - TuneShortForwardBranchOpt, + TuneShortForwardBranchIALU, TunePostRAScheduler]; def ANDES_45 : RISCVTuneProcessorModel<"andes-45-series", diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index b659bb96f2f11..c16b23e290df1 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -208,7 +208,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { bool hasConditionalMoveFusion() const { // Do we support fusing a branch+mv or branch+c.mv as a conditional move. return (hasConditionalCompressedMoveFusion() && hasStdExtZca()) || - hasShortForwardBranchOpt(); + hasShortForwardBranchIALU(); } bool hasShlAdd(int64_t ShAmt) const { diff --git a/llvm/test/Analysis/CostModel/RISCV/cmp-select.ll b/llvm/test/Analysis/CostModel/RISCV/cmp-select.ll index dc0810b128698..58848cc4a97ef 100644 --- a/llvm/test/Analysis/CostModel/RISCV/cmp-select.ll +++ b/llvm/test/Analysis/CostModel/RISCV/cmp-select.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt < %s -mtriple=riscv64 -mattr=+v,+f,+short-forward-branch-opt -passes="print" -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefixes=SFB64 +; RUN: opt < %s -mtriple=riscv64 -mattr=+v,+f,+short-forward-branch-ialu -passes="print" -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefixes=SFB64 ; RUN: opt < %s -mtriple=riscv64 -mattr=+v,+f -passes="print" -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefixes=RV64 define i32 @icmp-iselect(i64 %ca, i64 %cb, i32 %a, i32 %b) { diff --git a/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll b/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll index 1957019f055a2..a03a53215be38 100644 --- a/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll +++ b/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll @@ -5,13 +5,13 @@ ; RUN: | FileCheck -check-prefixes=CMOV,CMOV-NOZICOND %s ; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c,+zicond -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CMOV,CMOV-ZICOND %s -; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-ialu -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND,SFB-NOZICOND-NOC %s -; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+c -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-ialu,+c -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND,SFB-NOZICOND-C %s -; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+zicond -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-ialu,+zicond -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-ZICOND %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI ; The conditional move optimization in sifive-p450 requires that only a diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 010d3c68b5ef1..b3fa871c859a0 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -137,9 +137,9 @@ ; CHECK-NEXT: shgatpa - 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare). ; CHECK-NEXT: shifted-zextw-fusion - Enable SLLI+SRLI to be fused when computing (shifted) word zero extension. ; CHECK-NEXT: shlcofideleg - 'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode). -; CHECK-NEXT: short-forward-branch-i-minmax - Enable short forward branch optimization for min,max instructions in Zbb. -; CHECK-NEXT: short-forward-branch-i-mul - Enable short forward branch optimization for mul instruction. -; CHECK-NEXT: short-forward-branch-opt - Enable short forward branch optimization. +; CHECK-NEXT: short-forward-branch-ialu - Enable short forward branch optimization for RVI base instructions. +; CHECK-NEXT: short-forward-branch-iminmax - Enable short forward branch optimization for MIN,MAX instructions in Zbb. +; CHECK-NEXT: short-forward-branch-imul - Enable short forward branch optimization for MUL instruction. ; CHECK-NEXT: shtvala - 'Shtvala' (htval provides all needed values). ; CHECK-NEXT: shvsatpa - 'Shvsatpa' (vsatp supports all modes supported by satp). ; CHECK-NEXT: shvstvala - 'Shvstvala' (vstval provides all needed values). diff --git a/llvm/test/CodeGen/RISCV/min-max.ll b/llvm/test/CodeGen/RISCV/min-max.ll index e7f6899f18d16..6f63301db5019 100644 --- a/llvm/test/CodeGen/RISCV/min-max.ll +++ b/llvm/test/CodeGen/RISCV/min-max.ll @@ -5,11 +5,11 @@ ; RUN: FileCheck %s --check-prefixes=ZBB,RV32ZBB ; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | \ ; RUN: FileCheck %s --check-prefixes=ZBB,RV64ZBB -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s | \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s | \ ; RUN: FileCheck %s --check-prefixes=XQCI -; RUN: llc < %s -mtriple=riscv32 -mattr=+short-forward-branch-opt | \ +; RUN: llc < %s -mtriple=riscv32 -mattr=+short-forward-branch-ialu | \ ; RUN: FileCheck %s --check-prefixes=RV32I-SFB -; RUN: llc < %s -mtriple=riscv64 -mattr=+short-forward-branch-opt | \ +; RUN: llc < %s -mtriple=riscv64 -mattr=+short-forward-branch-ialu | \ ; RUN: FileCheck %s --check-prefixes=RV64I-SFB ; Basic tests. diff --git a/llvm/test/CodeGen/RISCV/select-bare.ll b/llvm/test/CodeGen/RISCV/select-bare.ll index 550eb94724ff2..fe0f74f5f2fa3 100644 --- a/llvm/test/CodeGen/RISCV/select-bare.ll +++ b/llvm/test/CodeGen/RISCV/select-bare.ll @@ -3,7 +3,7 @@ ; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind { diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll index 95f5a9d0925de..a215f893837a8 100644 --- a/llvm/test/CodeGen/RISCV/select-cc.ll +++ b/llvm/test/CodeGen/RISCV/select-cc.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI ; RUN: llc -mtriple=riscv64 -disable-block-placement -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64I %s diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll index a3c48737edc3c..ab3306e4e78e3 100644 --- a/llvm/test/CodeGen/RISCV/select-cond.ll +++ b/llvm/test/CodeGen/RISCV/select-cond.ll @@ -7,7 +7,7 @@ ; RUN: | FileCheck %s --check-prefixes=RV32-XQCICM ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32-XQCICS -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV64 diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll index f2924bb364adb..1c6cc6dc97900 100644 --- a/llvm/test/CodeGen/RISCV/select-const.ll +++ b/llvm/test/CodeGen/RISCV/select-const.ll @@ -5,7 +5,7 @@ ; RUN: | FileCheck -check-prefixes=RV32,RV32IF %s ; RUN: llc -mtriple=riscv32 -mattr=+zicond -target-abi=ilp32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32,RV32ZICOND %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI ; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64,RV64I %s diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll index 1eb47e4c0ede2..d7a6056a4feb4 100644 --- a/llvm/test/CodeGen/RISCV/select.ll +++ b/llvm/test/CodeGen/RISCV/select.ll @@ -4,7 +4,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IMXVTCONDOPS %s ; RUN: llc -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI define i16 @select_xor_1(i16 %A, i8 %cond) { diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll index 6aae6cd0e82ee..4f51e602d1346 100644 --- a/llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll +++ b/llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+experimental-xqcili | FileCheck %s --check-prefixes=RV32I ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64I -; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+experimental-xqcili,+short-forward-branch-opt | \ +; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+experimental-xqcili,+short-forward-branch-ialu | \ ; RUN: FileCheck %s --check-prefixes=RV32I-SFB -; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64 -mattr=+short-forward-branch-opt | \ +; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64 -mattr=+short-forward-branch-ialu | \ ; RUN: FileCheck %s --check-prefixes=RV64I-SFB define i32 @select_example_1(i32 %a, i32 %b, i1 zeroext %x, i32 %y) { diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-min-max.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-min-max.ll index 05e06cea9967a..3d32ce9b9ada6 100644 --- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-min-max.ll +++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-min-max.ll @@ -1,13 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s --check-prefixes=RV32I-ZBB ; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s --check-prefixes=RV64I-ZBB -; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb,+short-forward-branch-opt | \ +; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb,+short-forward-branch-ialu | \ ; RUN: FileCheck %s --check-prefixes=RV32I-SFB-ZBB -; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb,+short-forward-branch-opt | \ +; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb,+short-forward-branch-ialu | \ ; RUN: FileCheck %s --check-prefixes=RV64I-SFB-ZBB -; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb,+short-forward-branch-i-minmax | \ +; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb,+short-forward-branch-iminmax | \ ; RUN: FileCheck %s --check-prefixes=RV32I-SFBIMinMax-ZBB -; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb,+short-forward-branch-i-minmax | \ +; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb,+short-forward-branch-iminmax | \ ; RUN: FileCheck %s --check-prefixes=RV64I-SFBIMinMax-ZBB define i32 @select_example_smax(i32 %a, i32 %b, i1 zeroext %x, i32 %y) { diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-mul.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-mul.ll index 3f780fddafcce..47ad9755154b6 100644 --- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-mul.ll +++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-mul.ll @@ -1,13 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32I-M ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64I-M -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+short-forward-branch-opt | \ +; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+short-forward-branch-ialu | \ ; RUN: FileCheck %s --check-prefixes=RV32I-SFB-M -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+short-forward-branch-opt | \ +; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+short-forward-branch-ialu | \ ; RUN: FileCheck %s --check-prefixes=RV64I-SFB-M -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+short-forward-branch-i-mul | \ +; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+short-forward-branch-imul | \ ; RUN: FileCheck %s --check-prefixes=RV32I-SFBIMul-M -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+short-forward-branch-i-mul | \ +; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+short-forward-branch-imul | \ ; RUN: FileCheck %s --check-prefixes=RV64I-SFBIMul-M define i32 @select_example_mul_i32(i32 %a, i32 %b, i1 zeroext %x, i32 %y) { diff --git a/llvm/test/CodeGen/RISCV/xqcicli.ll b/llvm/test/CodeGen/RISCV/xqcicli.ll index cdb1947339736..229ef67e208fb 100644 --- a/llvm/test/CodeGen/RISCV/xqcicli.ll +++ b/llvm/test/CodeGen/RISCV/xqcicli.ll @@ -4,7 +4,7 @@ ; RUN: | FileCheck %s --check-prefixes=RV32I ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCICLI -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) { diff --git a/llvm/test/CodeGen/RISCV/xqcicm.ll b/llvm/test/CodeGen/RISCV/xqcicm.ll index 8e934963c258b..dbfbaa7c033a2 100644 --- a/llvm/test/CodeGen/RISCV/xqcicm.ll +++ b/llvm/test/CodeGen/RISCV/xqcicm.ll @@ -6,7 +6,7 @@ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI define i32 @select_example(i32 %cond, i32 %x, i32 %y) { diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll index 7656a0c0e78e0..123226655de3f 100644 --- a/llvm/test/CodeGen/RISCV/xqcics.ll +++ b/llvm/test/CodeGen/RISCV/xqcics.ll @@ -6,7 +6,7 @@ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics,+experimental-xqcicm -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI define i32 @select_cc_example_eq_s1(i32 %a, i32 %b, i32 %x, i32 %y) {