[CodeGenTypes] Remove explicit VT numbers from ValueTypes.td #169670

jayfoad · 2025-11-26T16:01:11Z

Remove explicit VT numbers from ValueTypes.td so that patches that add a
new VT do not have to renumber the entire file.

In TableGen VTs are now identified by ValueType.LLVMName instead of
ValueType.Value. This is important for target-defined types (typically
based on PtrValueType) which are not mentioned in ValueTypes.td itself.

Remove explicit VT numbers from ValueTypes.td so that patches that add a new VT do not have to renumber the entire file. In TableGen VTs are now identified by ValueType.LLVMName instead of ValueType.Value. This is important for target-defined types (typically based on PtrValueType) which are not mentioned in ValueTypes.td itself.

llvmbot · 2025-11-26T16:01:45Z

@llvm/pr-subscribers-mlir
@llvm/pr-subscribers-mlir-llvm
@llvm/pr-subscribers-tablegen

@llvm/pr-subscribers-backend-spir-v

Author: Jay Foad (jayfoad)

Changes

Remove explicit VT numbers from ValueTypes.td so that patches that add a
new VT do not have to renumber the entire file.

In TableGen VTs are now identified by ValueType.LLVMName instead of
ValueType.Value. This is important for target-defined types (typically
based on PtrValueType) which are not mentioned in ValueTypes.td itself.

Patch is 47.97 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/169670.diff

6 Files Affected:

(modified) llvm/include/llvm/CodeGen/ValueTypes.td (+306-313)
(modified) llvm/include/llvm/CodeGenTypes/MachineValueType.h (+9-11)
(modified) llvm/include/llvm/Target/Target.td (+2-2)
(modified) llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td (+1-1)
(modified) llvm/utils/TableGen/Basic/VTEmitter.cpp (+9-8)
(modified) llvm/utils/TableGen/Common/CodeGenTarget.cpp (+9-2)

diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td
index dfcc97b5880f5..74ea86774a8ee 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.td
+++ b/llvm/include/llvm/CodeGen/ValueTypes.td
@@ -6,16 +6,15 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// ValueTypes.td - list of ValueType instances supported by the the
+// ValueTypes.td - list of ValueType instances supported by the
 // CodeGen infrastructure.
 //
 //===----------------------------------------------------------------------===//
 
-class ValueType<int size, int value> {
+class ValueType<int size, string llvm_name = NAME> {
   string Namespace = "MVT";
-  string LLVMName = NAME;
+  string LLVMName = llvm_name;
   int Size = size;
-  int Value = value;
   int nElem = 1;
   ValueType ElementType = ?;
   bit isOverloaded = false;
@@ -31,22 +30,22 @@ class ValueType<int size, int value> {
   bit isCheriCapability = false;
 }
 
-class VTAny<int value> : ValueType<0, value> {
+class VTAny : ValueType<0> {
   let isOverloaded = true;
 }
 
-class VTInt<int size, int value>
-    : ValueType<size, value> {
+class VTInt<int size>
+    : ValueType<size> {
   let isInteger = true;
 }
 
-class VTFP<int size, int value>
-    : ValueType<size, value> {
+class VTFP<int size>
+    : ValueType<size> {
   let isFP = true;
 }
 
-class VTVec<int nelem, ValueType elt, int value>
-    : ValueType<!mul(nelem, elt.Size), value> {
+class VTVec<int nelem, ValueType elt, string llvm_name = NAME>
+    : ValueType<!mul(nelem, elt.Size), llvm_name> {
   let nElem = nelem;
   let ElementType = elt;
   let isInteger = elt.isInteger;
@@ -54,354 +53,348 @@ class VTVec<int nelem, ValueType elt, int value>
   let isVector = true;
 }
 
-class VTScalableVec<int nelem, ValueType elt, int value>
-    : VTVec<nelem, elt, value> {
+class VTScalableVec<int nelem, ValueType elt>
+    : VTVec<nelem, elt> {
   let isScalable = true;
 }
 
-class VTVecTup<int size, int nf, ValueType dummy_elt, int value>
-    : ValueType<size, value> {
+class VTVecTup<int size, int nf, ValueType dummy_elt>
+    : ValueType<size> {
   let NF = nf;
   let ElementType = dummy_elt;
   let isRISCVVecTuple = true;
 }
 
-class VTCheriCapability<int size, int value> : ValueType<size, value> {
+class VTCheriCapability<int size> : ValueType<size> {
   let isCheriCapability = true;
 }
 
 defset list<ValueType> ValueTypes = {
 
-def OtherVT : ValueType<0,   1> {  // "Other" value
-  let LLVMName = "Other";
-}
-
-def i1      : VTInt<1,   2>;  // One bit boolean value
-def i2      : VTInt<2,   3>;  // 2-bit integer value
-def i4      : VTInt<4,   4>;  // 4-bit integer value
-def i8      : VTInt<8,   5>;  // 8-bit integer value
-def i16     : VTInt<16,  6>;  // 16-bit integer value
-def i32     : VTInt<32,  7>;  // 32-bit integer value
-def i64     : VTInt<64,  8>;  // 64-bit integer value
-def i128    : VTInt<128, 9>;  // 128-bit integer value
-def i256    : VTInt<256, 10>; // 256-bit integer value
-def i512    : VTInt<512, 11>; // 512-bit integer value
-
-def bf16    : VTFP<16,  12>;  // 16-bit brain floating point value
-def f16     : VTFP<16,  13>;  // 16-bit floating point value
-def f32     : VTFP<32,  14>;  // 32-bit floating point value
-def f64     : VTFP<64,  15>;  // 64-bit floating point value
-def f80     : VTFP<80,  16>;  // 80-bit floating point value
-def f128    : VTFP<128, 17>;  // 128-bit floating point value
-def ppcf128 : VTFP<128, 18>;  // PPC 128-bit floating point value
-
-def v1i1    : VTVec<1,    i1, 19>;  //    1 x i1 vector value
-def v2i1    : VTVec<2,    i1, 20>;  //    2 x i1 vector value
-def v3i1    : VTVec<3,    i1, 21>;  //    3 x i1 vector value
-def v4i1    : VTVec<4,    i1, 22>;  //    4 x i1 vector value
-def v5i1    : VTVec<5,    i1, 23>;  //    5 x i1 vector value
-def v6i1    : VTVec<6,    i1, 24>;  //    6 x i1 vector value
-def v7i1    : VTVec<7,    i1, 25>;  //    7 x i1 vector value
-def v8i1    : VTVec<8,    i1, 26>;  //    8 x i1 vector value
-def v16i1   : VTVec<16,   i1, 27>;  //   16 x i1 vector value
-def v32i1   : VTVec<32,   i1, 28>;  //   32 x i1 vector value
-def v64i1   : VTVec<64,   i1, 29>;  //   64 x i1 vector value
-def v128i1  : VTVec<128,  i1, 30>;  //  128 x i1 vector value
-def v256i1  : VTVec<256,  i1, 31>;  //  256 x i1 vector value
-def v512i1  : VTVec<512,  i1, 32>;  //  512 x i1 vector value
-def v1024i1 : VTVec<1024, i1, 33>;  // 1024 x i1 vector value
-def v2048i1 : VTVec<2048, i1, 34>;  // 2048 x i1 vector value
-def v4096i1 : VTVec<4096, i1, 35>;  // 4096 x i1 vector value
-
-def v128i2  : VTVec<128,  i2, 36>;   //  128 x i2 vector value
-def v256i2  : VTVec<256,  i2, 37>;   //  256 x i2 vector value
-
-def v64i4   : VTVec<64,   i4, 38>;   //   64 x i4 vector value
-def v128i4  : VTVec<128,  i4, 39>;   //  128 x i4 vector value
-
-def v1i8    : VTVec<1,    i8, 40>;  //    1 x i8 vector value
-def v2i8    : VTVec<2,    i8, 41>;  //    2 x i8 vector value
-def v3i8    : VTVec<3,    i8, 42>;  //    3 x i8 vector value
-def v4i8    : VTVec<4,    i8, 43>;  //    4 x i8 vector value
-def v5i8    : VTVec<5,    i8, 44>;  //    5 x i8 vector value
-def v6i8    : VTVec<6,    i8, 45>;  //    6 x i8 vector value
-def v7i8    : VTVec<7,    i8, 46>;  //    7 x i8 vector value
-def v8i8    : VTVec<8,    i8, 47>;  //    8 x i8 vector value
-def v16i8   : VTVec<16,   i8, 48>;  //   16 x i8 vector value
-def v32i8   : VTVec<32,   i8, 49>;  //   32 x i8 vector value
-def v64i8   : VTVec<64,   i8, 50>;  //   64 x i8 vector value
-def v128i8  : VTVec<128,  i8, 51>;  //  128 x i8 vector value
-def v256i8  : VTVec<256,  i8, 52>;  //  256 x i8 vector value
-def v512i8  : VTVec<512,  i8, 53>;  //  512 x i8 vector value
-def v1024i8 : VTVec<1024, i8, 54>;  // 1024 x i8 vector value
-
-def v1i16    : VTVec<1,    i16, 55>;  //    1 x i16 vector value
-def v2i16    : VTVec<2,    i16, 56>;  //    2 x i16 vector value
-def v3i16    : VTVec<3,    i16, 57>;  //    3 x i16 vector value
-def v4i16    : VTVec<4,    i16, 58>;  //    4 x i16 vector value
-def v5i16    : VTVec<5,    i16, 59>;  //    5 x i16 vector value
-def v6i16    : VTVec<6,    i16, 60>;  //    6 x i16 vector value
-def v7i16    : VTVec<7,    i16, 61>;  //    7 x i16 vector value
-def v8i16    : VTVec<8,    i16, 62>;  //    8 x i16 vector value
-def v16i16   : VTVec<16,   i16, 63>;  //   16 x i16 vector value
-def v32i16   : VTVec<32,   i16, 64>;  //   32 x i16 vector value
-def v64i16   : VTVec<64,   i16, 65>;  //   64 x i16 vector value
-def v128i16  : VTVec<128,  i16, 66>;  //  128 x i16 vector value
-def v256i16  : VTVec<256,  i16, 67>;  //  256 x i16 vector value
-def v512i16  : VTVec<512,  i16, 68>;  //  512 x i16 vector value
-def v4096i16 : VTVec<4096, i16, 69>;  // 4096 x i16 vector value
-
-def v1i32    : VTVec<1,    i32, 70>;  //    1 x i32 vector value
-def v2i32    : VTVec<2,    i32, 71>;  //    2 x i32 vector value
-def v3i32    : VTVec<3,    i32, 72>;  //    3 x i32 vector value
-def v4i32    : VTVec<4,    i32, 73>;  //    4 x i32 vector value
-def v5i32    : VTVec<5,    i32, 74>;  //    5 x i32 vector value
-def v6i32    : VTVec<6,    i32, 75>;  //    6 x i32 vector value
-def v7i32    : VTVec<7,    i32, 76>;  //    7 x i32 vector value
-def v8i32    : VTVec<8,    i32, 77>;  //    8 x i32 vector value
-def v9i32    : VTVec<9,    i32, 78>;  //    9 x i32 vector value
-def v10i32   : VTVec<10,   i32, 79>;  //   10 x i32 vector value
-def v11i32   : VTVec<11,   i32, 80>;  //   11 x i32 vector value
-def v12i32   : VTVec<12,   i32, 81>;  //   12 x i32 vector value
-def v16i32   : VTVec<16,   i32, 82>;  //   16 x i32 vector value
-def v32i32   : VTVec<32,   i32, 83>;  //   32 x i32 vector value
-def v64i32   : VTVec<64,   i32, 84>;  //   64 x i32 vector value
-def v128i32  : VTVec<128,  i32, 85>;  //  128 x i32 vector value
-def v256i32  : VTVec<256,  i32, 86>;  //  256 x i32 vector value
-def v512i32  : VTVec<512,  i32, 87>;  //  512 x i32 vector value
-def v1024i32 : VTVec<1024, i32, 88>;  // 1024 x i32 vector value
-def v2048i32 : VTVec<2048, i32, 89>;  // 2048 x i32 vector value
-def v4096i32 : VTVec<4096, i32, 90>;  // 4096 x i32 vector value
-
-def v1i64   : VTVec<1,   i64, 91>;  //   1 x i64 vector value
-def v2i64   : VTVec<2,   i64, 92>;  //   2 x i64 vector value
-def v3i64   : VTVec<3,   i64, 93>;  //   3 x i64 vector value
-def v4i64   : VTVec<4,   i64, 94>;  //   4 x i64 vector value
-def v8i64   : VTVec<8,   i64, 95>;  //   8 x i64 vector value
-def v16i64  : VTVec<16,  i64, 96>;  //  16 x i64 vector value
-def v32i64  : VTVec<32,  i64, 97>;  //  32 x i64 vector value
-def v64i64  : VTVec<64,  i64, 98>;  //  64 x i64 vector value
-def v128i64 : VTVec<128, i64, 99>;  // 128 x i64 vector value
-def v256i64 : VTVec<256, i64, 100>; // 256 x i64 vector value
-
-def v1i128  : VTVec<1,  i128, 101>; //  1 x i128 vector value
-
-def v1f16    : VTVec<1,    f16, 102>;  //    1 x f16 vector value
-def v2f16    : VTVec<2,    f16, 103>;  //    2 x f16 vector value
-def v3f16    : VTVec<3,    f16, 104>;  //    3 x f16 vector value
-def v4f16    : VTVec<4,    f16, 105>;  //    4 x f16 vector value
-def v5f16    : VTVec<5,    f16, 106>;  //    5 x f16 vector value
-def v6f16    : VTVec<6,    f16, 107>;  //    6 x f16 vector value
-def v7f16    : VTVec<7,    f16, 108>;  //    7 x f16 vector value
-def v8f16    : VTVec<8,    f16, 109>;  //    8 x f16 vector value
-def v16f16   : VTVec<16,   f16, 110>;  //   16 x f16 vector value
-def v32f16   : VTVec<32,   f16, 111>;  //   32 x f16 vector value
-def v64f16   : VTVec<64,   f16, 112>;  //   64 x f16 vector value
-def v128f16  : VTVec<128,  f16, 113>;  //  128 x f16 vector value
-def v256f16  : VTVec<256,  f16, 114>;  //  256 x f16 vector value
-def v512f16  : VTVec<512,  f16, 115>;  //  512 x f16 vector value
-def v4096f16 : VTVec<4096, f16, 116>;  // 4096 x f16 vector value
-
-def v1bf16    : VTVec<1,    bf16, 117>;  //    1 x bf16 vector value
-def v2bf16    : VTVec<2,    bf16, 118>;  //    2 x bf16 vector value
-def v3bf16    : VTVec<3,    bf16, 119>;  //    3 x bf16 vector value
-def v4bf16    : VTVec<4,    bf16, 120>;  //    4 x bf16 vector value
-def v8bf16    : VTVec<8,    bf16, 121>;  //    8 x bf16 vector value
-def v16bf16   : VTVec<16,   bf16, 122>;  //   16 x bf16 vector value
-def v32bf16   : VTVec<32,   bf16, 123>;  //   32 x bf16 vector value
-def v64bf16   : VTVec<64,   bf16, 124>;  //   64 x bf16 vector value
-def v128bf16  : VTVec<128,  bf16, 125>;  //  128 x bf16 vector value
-def v4096bf16 : VTVec<4096, bf16, 126>;  // 4096 x bf16 vector value
-
-def v1f32    : VTVec<1,    f32, 127>;  //    1 x f32 vector value
-def v2f32    : VTVec<2,    f32, 128>;  //    2 x f32 vector value
-def v3f32    : VTVec<3,    f32, 129>;  //    3 x f32 vector value
-def v4f32    : VTVec<4,    f32, 130>;  //    4 x f32 vector value
-def v5f32    : VTVec<5,    f32, 131>;  //    5 x f32 vector value
-def v6f32    : VTVec<6,    f32, 132>;  //    6 x f32 vector value
-def v7f32    : VTVec<7,    f32, 133>;  //    7 x f32 vector value
-def v8f32    : VTVec<8,    f32, 134>;  //    8 x f32 vector value
-def v9f32    : VTVec<9,    f32, 135>;  //    9 x f32 vector value
-def v10f32   : VTVec<10,   f32, 136>;  //   10 x f32 vector value
-def v11f32   : VTVec<11,   f32, 137>;  //   11 x f32 vector value
-def v12f32   : VTVec<12,   f32, 138>;  //   12 x f32 vector value
-def v16f32   : VTVec<16,   f32, 139>;  //   16 x f32 vector value
-def v32f32   : VTVec<32,   f32, 140>;  //   32 x f32 vector value
-def v64f32   : VTVec<64,   f32, 141>;  //   64 x f32 vector value
-def v128f32  : VTVec<128,  f32, 142>;  //  128 x f32 vector value
-def v256f32  : VTVec<256,  f32, 143>;  //  256 x f32 vector value
-def v512f32  : VTVec<512,  f32, 144>;  //  512 x f32 vector value
-def v1024f32 : VTVec<1024, f32, 145>;  // 1024 x f32 vector value
-def v2048f32 : VTVec<2048, f32, 146>;  // 2048 x f32 vector value
-
-def v1f64    : VTVec<1,    f64, 147>;  //    1 x f64 vector value
-def v2f64    : VTVec<2,    f64, 148>;  //    2 x f64 vector value
-def v3f64    : VTVec<3,    f64, 149>;  //    3 x f64 vector value
-def v4f64    : VTVec<4,    f64, 150>;  //    4 x f64 vector value
-def v8f64    : VTVec<8,    f64, 151>;  //    8 x f64 vector value
-def v16f64   : VTVec<16,   f64, 152>;  //   16 x f64 vector value
-def v32f64   : VTVec<32,   f64, 153>;  //   32 x f64 vector value
-def v64f64   : VTVec<64,   f64, 154>;  //   64 x f64 vector value
-def v128f64  : VTVec<128,  f64, 155>;  //  128 x f64 vector value
-def v256f64  : VTVec<256,  f64, 156>;  //  256 x f64 vector value
-
-def nxv1i1  : VTScalableVec<1,  i1, 157>;  // n x  1 x i1  vector value
-def nxv2i1  : VTScalableVec<2,  i1, 158>;  // n x  2 x i1  vector value
-def nxv4i1  : VTScalableVec<4,  i1, 159>;  // n x  4 x i1  vector value
-def nxv8i1  : VTScalableVec<8,  i1, 160>;  // n x  8 x i1  vector value
-def nxv16i1 : VTScalableVec<16, i1, 161>;  // n x 16 x i1  vector value
-def nxv32i1 : VTScalableVec<32, i1, 162>;  // n x 32 x i1  vector value
-def nxv64i1 : VTScalableVec<64, i1, 163>;  // n x 64 x i1  vector value
-
-def nxv1i8  : VTScalableVec<1,  i8, 164>;  // n x  1 x i8  vector value
-def nxv2i8  : VTScalableVec<2,  i8, 165>;  // n x  2 x i8  vector value
-def nxv4i8  : VTScalableVec<4,  i8, 166>;  // n x  4 x i8  vector value
-def nxv8i8  : VTScalableVec<8,  i8, 167>;  // n x  8 x i8  vector value
-def nxv16i8 : VTScalableVec<16, i8, 168>;  // n x 16 x i8  vector value
-def nxv32i8 : VTScalableVec<32, i8, 169>;  // n x 32 x i8  vector value
-def nxv64i8 : VTScalableVec<64, i8, 170>;  // n x 64 x i8  vector value
-
-def nxv1i16  : VTScalableVec<1,  i16, 171>;  // n x  1 x i16 vector value
-def nxv2i16  : VTScalableVec<2,  i16, 172>;  // n x  2 x i16 vector value
-def nxv4i16  : VTScalableVec<4,  i16, 173>;  // n x  4 x i16 vector value
-def nxv8i16  : VTScalableVec<8,  i16, 174>;  // n x  8 x i16 vector value
-def nxv16i16 : VTScalableVec<16, i16, 175>;  // n x 16 x i16 vector value
-def nxv32i16 : VTScalableVec<32, i16, 176>;  // n x 32 x i16 vector value
-
-def nxv1i32  : VTScalableVec<1,  i32, 177>;  // n x  1 x i32 vector value
-def nxv2i32  : VTScalableVec<2,  i32, 178>;  // n x  2 x i32 vector value
-def nxv4i32  : VTScalableVec<4,  i32, 179>;  // n x  4 x i32 vector value
-def nxv8i32  : VTScalableVec<8,  i32, 180>;  // n x  8 x i32 vector value
-def nxv16i32 : VTScalableVec<16, i32, 181>;  // n x 16 x i32 vector value
-def nxv32i32 : VTScalableVec<32, i32, 182>;  // n x 32 x i32 vector value
-
-def nxv1i64  : VTScalableVec<1,  i64, 183>;  // n x  1 x i64 vector value
-def nxv2i64  : VTScalableVec<2,  i64, 184>;  // n x  2 x i64 vector value
-def nxv4i64  : VTScalableVec<4,  i64, 185>;  // n x  4 x i64 vector value
-def nxv8i64  : VTScalableVec<8,  i64, 186>;  // n x  8 x i64 vector value
-def nxv16i64 : VTScalableVec<16, i64, 187>;  // n x 16 x i64 vector value
-def nxv32i64 : VTScalableVec<32, i64, 188>;  // n x 32 x i64 vector value
-
-def nxv1f16  : VTScalableVec<1,  f16, 189>;  // n x  1 x  f16 vector value
-def nxv2f16  : VTScalableVec<2,  f16, 190>;  // n x  2 x  f16 vector value
-def nxv4f16  : VTScalableVec<4,  f16, 191>;  // n x  4 x  f16 vector value
-def nxv8f16  : VTScalableVec<8,  f16, 192>;  // n x  8 x  f16 vector value
-def nxv16f16 : VTScalableVec<16, f16, 193>;  // n x 16 x  f16 vector value
-def nxv32f16 : VTScalableVec<32, f16, 194>;  // n x 32 x  f16 vector value
-
-def nxv1bf16  : VTScalableVec<1,  bf16, 195>;  // n x  1 x bf16 vector value
-def nxv2bf16  : VTScalableVec<2,  bf16, 196>;  // n x  2 x bf16 vector value
-def nxv4bf16  : VTScalableVec<4,  bf16, 197>;  // n x  4 x bf16 vector value
-def nxv8bf16  : VTScalableVec<8,  bf16, 198>;  // n x  8 x bf16 vector value
-def nxv16bf16 : VTScalableVec<16, bf16, 199>;  // n x 16 x bf16 vector value
-def nxv32bf16 : VTScalableVec<32, bf16, 200>;  // n x 32 x bf16 vector value
-
-def nxv1f32  : VTScalableVec<1,  f32, 201>;  // n x  1 x  f32 vector value
-def nxv2f32  : VTScalableVec<2,  f32, 202>;  // n x  2 x  f32 vector value
-def nxv4f32  : VTScalableVec<4,  f32, 203>;  // n x  4 x  f32 vector value
-def nxv8f32  : VTScalableVec<8,  f32, 204>;  // n x  8 x  f32 vector value
-def nxv16f32 : VTScalableVec<16, f32, 205>;  // n x 16 x  f32 vector value
-
-def nxv1f64  : VTScalableVec<1,  f64, 206>;  // n x  1 x  f64 vector value
-def nxv2f64  : VTScalableVec<2,  f64, 207>;  // n x  2 x  f64 vector value
-def nxv4f64  : VTScalableVec<4,  f64, 208>;  // n x  4 x  f64 vector value
-def nxv8f64  : VTScalableVec<8,  f64, 209>;  // n x  8 x  f64 vector value
+def OtherVT : ValueType<0, "Other">; // "Other" value
+
+def i1      : VTInt<1>;   // One bit boolean value
+def i2      : VTInt<2>;   // 2-bit integer value
+def i4      : VTInt<4>;   // 4-bit integer value
+def i8      : VTInt<8>;   // 8-bit integer value
+def i16     : VTInt<16>;  // 16-bit integer value
+def i32     : VTInt<32>;  // 32-bit integer value
+def i64     : VTInt<64>;  // 64-bit integer value
+def i128    : VTInt<128>; // 128-bit integer value
+def i256    : VTInt<256>; // 256-bit integer value
+def i512    : VTInt<512>; // 512-bit integer value
+
+def bf16    : VTFP<16>;  // 16-bit brain floating point value
+def f16     : VTFP<16>;  // 16-bit floating point value
+def f32     : VTFP<32>;  // 32-bit floating point value
+def f64     : VTFP<64>;  // 64-bit floating point value
+def f80     : VTFP<80>;  // 80-bit floating point value
+def f128    : VTFP<128>; // 128-bit floating point value
+def ppcf128 : VTFP<128>; // PPC 128-bit floating point value
+
+def v1i1    : VTVec<1,    i1>; //    1 x i1 vector value
+def v2i1    : VTVec<2,    i1>; //    2 x i1 vector value
+def v3i1    : VTVec<3,    i1>; //    3 x i1 vector value
+def v4i1    : VTVec<4,    i1>; //    4 x i1 vector value
+def v5i1    : VTVec<5,    i1>; //    5 x i1 vector value
+def v6i1    : VTVec<6,    i1>; //    6 x i1 vector value
+def v7i1    : VTVec<7,    i1>; //    7 x i1 vector value
+def v8i1    : VTVec<8,    i1>; //    8 x i1 vector value
+def v16i1   : VTVec<16,   i1>; //   16 x i1 vector value
+def v32i1   : VTVec<32,   i1>; //   32 x i1 vector value
+def v64i1   : VTVec<64,   i1>; //   64 x i1 vector value
+def v128i1  : VTVec<128,  i1>; //  128 x i1 vector value
+def v256i1  : VTVec<256,  i1>; //  256 x i1 vector value
+def v512i1  : VTVec<512,  i1>; //  512 x i1 vector value
+def v1024i1 : VTVec<1024, i1>; // 1024 x i1 vector value
+def v2048i1 : VTVec<2048, i1>; // 2048 x i1 vector value
+def v4096i1 : VTVec<4096, i1>; // 4096 x i1 vector value
+
+def v128i2  : VTVec<128,  i2>; //  128 x i2 vector value
+def v256i2  : VTVec<256,  i2>; //  256 x i2 vector value
+
+def v64i4   : VTVec<64,   i4>; //   64 x i4 vector value
+def v128i4  : VTVec<128,  i4>; //  128 x i4 vector value
+
+def v1i8    : VTVec<1,    i8>; //    1 x i8 vector value
+def v2i8    : VTVec<2,    i8>; //    2 x i8 vector value
+def v3i8    : VTVec<3,    i8>; //    3 x i8 vector value
+def v4i8    : VTVec<4,    i8>; //    4 x i8 vector value
+def v5i8    : VTVec<5,    i8>; //    5 x i8 vector value
+def v6i8    : VTVec<6,    i8>; //    6 x i8 vector value
+def v7i8    : VTVec<7,    i8>; //    7 x i8 vector value
+def v8i8    : VTVec<8,    i8>; //    8 x i8 vector value
+def v16i8   : VTVec<16,   i8>; //   16 x i8 vector value
+def v32i8   : VTVec<32,   i8>; //   32 x i8 vector value
+def v64i8   : VTVec<64,   i8>; //   64 x i8 vector value
+def v128i8  : VTVec<128,  i8>; //  128 x i8 vector value
+def v256i8  : VTVec<256,  i8>; //  256 x i8 vector value
+def v512i8  : VTVec<512,  i8>; //  512 x i8 vector value
+def v1024i8 : VTVec<1024, i8>; // 1024 x i8 vector value
+
+def v1i16    : VTVec<1,    i16>; //    1 x i16 vector value
+def v2i16    : VTVec<2,    i16>; //    2 x i16 vector value
+def v3i16    : VTVec<3,    i16>; //    3 x i16 vector value
+def v4i16    : VTVec<4,    i16>; //    4 x i16 vector value
+def v5i16    : VTVec<5,    i16>; //    5 x i16 vector value
+def v6i16    : VTVec<6,    i16>; //    6 x i16 vector value
+def v7i16    : VTVec<7,    i16>; //    7 x i16 vector value
+def v8i16    : VTVec<8,    i16>; //    8 x i16 vector value
+def v16i16   : VTVec<16,   i16>; //   16 x i16 vector value
+def v32i16   : VTVec<32,   i16>; //   32 x i16 vector value
+def v64i16   : VTVec<64,   i16>; //   64 x i16 vector value
+def v128i16  : VTVec<128,  i16>; //  128 x i16 vector value
+def v256i16  : VTVec<256,  i16>; //  256 x i16 vector value
+def...
[truncated]

github-actions · 2025-11-26T16:36:33Z

🐧 Linux x64 Test Results

186643 tests passed
4888 tests skipped

topperc

LGTM

jayfoad · 2025-11-26T16:47:22Z

@s-barannikov pointed out an alternative patch from just a few days ago: #169071

topperc · 2025-11-26T16:53:29Z

@s-barannikov pointed out an alternative patch from just a few days ago: #169071

I think I prefer the patch in this PR over using instances. But let's see what other reviewers think.

AlexMaclean

Nice, I prefer this to #169071 as well

jayfoad · 2025-11-26T18:37:54Z

Nice, I prefer this to #169071 as well

Thanks, I appreciate that! I was impressed by the simplicity of your patch, but I am not too keen on relying so heavily on !instances.

chapuni

Looks good, thanks.

chapuni · 2025-11-26T22:15:14Z

llvm/utils/TableGen/Basic/VTEmitter.cpp

+  std::vector<const Record *> Defs(
+      Records.getAllDerivedDefinitions("ValueType"));
+  // Emit VTs in the order they were declared so that VTRanges stay contiguous.
+  llvm::sort(Defs, LessRecordByID());


4vtomat

LGTM, nice patch!

This PR adds a dependency to the `BUILD` files overlay silently added by #169670. Signed-off-by: Ingo Müller <ingomueller@google.com>

mikaelholmen · 2025-11-28T06:17:51Z

Huge thanks to you for this @jayfoad !

I live with a downstream compiler were we've added i24 and i40 to ValueTypes.td. You can imagine the amount of pain we've had through the years every time someone added a new type :)

This is awesome!

ingomueller-net · 2025-11-28T08:04:03Z

From this revision on, the __builtin_ia32_sqrtss intrinsic isn't found anymore in our builds. Can that be related to this PR?

s-barannikov · 2025-11-28T08:11:39Z

From this revision on, the __builtin_ia32_sqrtss intrinsic isn't found anymore in our builds. Can that be related to this PR?

Probably 0dbedd1?

ingomueller-net · 2025-11-28T10:10:02Z

Oh, good catch! Yes, that looks like a more plausible root cause 😉 Thanks!

llvmbot added tablegen backend:SPIR-V labels Nov 26, 2025

jayfoad requested review from chapuni, jurahul, s-barannikov and shiltian November 26, 2025 16:02

s-barannikov requested a review from AlexMaclean November 26, 2025 16:08

jayfoad requested review from 4vtomat and topperc November 26, 2025 16:09

s-barannikov mentioned this pull request Nov 26, 2025

[ValueTypes] Automatically assign value numbers (NFC) #169071

Closed

topperc approved these changes Nov 26, 2025

View reviewed changes

AlexMaclean approved these changes Nov 26, 2025

View reviewed changes

chapuni approved these changes Nov 26, 2025

View reviewed changes

4vtomat approved these changes Nov 27, 2025

View reviewed changes

Update mlir-tblgen

83e7322

llvmbot added mlir:core MLIR Core Infrastructure mlir:llvm mlir labels Nov 27, 2025

jayfoad merged commit ea1e62d into llvm:main Nov 27, 2025
14 checks passed

jayfoad deleted the remove-vt-numbers branch November 27, 2025 13:11

ingomueller-net mentioned this pull request Nov 27, 2025

[mlir:bazel] Fix build broken by #169670. #169804

Merged

ingomueller-net added a commit that referenced this pull request Nov 27, 2025

[mlir:bazel] Fix build broken by #169670. (#169804)

48e34d9

This PR adds a dependency to the `BUILD` files overlay silently added by #169670. Signed-off-by: Ingo Müller <ingomueller@google.com>

[CodeGenTypes] Remove explicit VT numbers from ValueTypes.td #169670

[CodeGenTypes] Remove explicit VT numbers from ValueTypes.td #169670

Uh oh!

Conversation

jayfoad commented Nov 26, 2025

Uh oh!

llvmbot commented Nov 26, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

github-actions bot commented Nov 26, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

🐧 Linux x64 Test Results

Uh oh!

topperc left a comment

Choose a reason for hiding this comment

Uh oh!

jayfoad commented Nov 26, 2025

Uh oh!

topperc commented Nov 26, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

AlexMaclean left a comment

Choose a reason for hiding this comment

Uh oh!

jayfoad commented Nov 26, 2025

Uh oh!

chapuni left a comment

Choose a reason for hiding this comment

Uh oh!

chapuni Nov 26, 2025

Choose a reason for hiding this comment

Uh oh!

4vtomat left a comment

Choose a reason for hiding this comment

Uh oh!

Uh oh!

mikaelholmen commented Nov 28, 2025

Uh oh!

ingomueller-net commented Nov 28, 2025

Uh oh!

s-barannikov commented Nov 28, 2025

Uh oh!

ingomueller-net commented Nov 28, 2025

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

9 participants

llvmbot commented Nov 26, 2025 •

edited

Loading

github-actions bot commented Nov 26, 2025 •

edited

Loading

topperc commented Nov 26, 2025 •

edited

Loading