[SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0) #170076

rez5427 · 2025-12-01T05:23:02Z

I recently observed that LLVM generates the following code:

	addi	a1, a0, -1
	sltu	a0, a0, a1
	addi	a0, a0, -1
	and	a0, a0, a1
	ret

This could be optimized using the snez instruction instead.

llvmbot · 2025-12-01T05:23:34Z

@llvm/pr-subscribers-backend-x86
@llvm/pr-subscribers-llvm-selectiondag
@llvm/pr-subscribers-backend-aarch64

@llvm/pr-subscribers-backend-risc-v

Author: guan jian (rez5427)

Changes

I recently observed that LLVM generates the following code:

	addi	a1, a0, -1
	sltu	a0, a0, a1
	addi	a0, a0, -1
	and	a0, a0, a1
	ret

This could be optimized using the snez instruction instead.

Full diff: https://github.com/llvm/llvm-project/pull/170076.diff

3 Files Affected:

(modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+10)
(modified) llvm/test/CodeGen/AArch64/and-mask-removal.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/usub_sat.ll (+28)

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 521d8f07434e6..b3af59b6528b9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -10867,6 +10867,16 @@ SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
   assert(VT == RHS.getValueType() && "Expected operands to be the same type");
   assert(VT.isInteger() && "Expected operands to be integers");
 
+  // usub.sat(a, 1) -> a - zext(a != 0)
+  if (Opcode == ISD::USUBSAT && !VT.isVector() && isOneConstant(RHS)) {
+    SDValue Zero = DAG.getConstant(0, dl, VT);
+    EVT BoolVT =
+        getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+    SDValue IsNonZero = DAG.getSetCC(dl, BoolVT, LHS, Zero, ISD::SETNE);
+    SDValue Subtrahend = DAG.getBoolExtOrTrunc(IsNonZero, dl, VT, BoolVT);
+    return DAG.getNode(ISD::SUB, dl, VT, LHS, Subtrahend);
+  }
+
   // usub.sat(a, b) -> umax(a, b) - b
   if (Opcode == ISD::USUBSAT && isOperationLegal(ISD::UMAX, VT)) {
     SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS);
diff --git a/llvm/test/CodeGen/AArch64/and-mask-removal.ll b/llvm/test/CodeGen/AArch64/and-mask-removal.ll
index 5046c0571ad2b..855fe5caf97b2 100644
--- a/llvm/test/CodeGen/AArch64/and-mask-removal.ll
+++ b/llvm/test/CodeGen/AArch64/and-mask-removal.ll
@@ -483,9 +483,9 @@ define i64 @pr58109(i8 signext %0) {
 ; CHECK-SD-LABEL: pr58109:
 ; CHECK-SD:       ; %bb.0:
 ; CHECK-SD-NEXT:    add w8, w0, #1
-; CHECK-SD-NEXT:    and w8, w8, #0xff
-; CHECK-SD-NEXT:    subs w8, w8, #1
-; CHECK-SD-NEXT:    csel w0, wzr, w8, lo
+; CHECK-SD-NEXT:    ands w8, w8, #0xff
+; CHECK-SD-NEXT:    cset w9, ne
+; CHECK-SD-NEXT:    sub w0, w8, w9
 ; CHECK-SD-NEXT:    ret
 ;
 ; CHECK-GI-LABEL: pr58109:
diff --git a/llvm/test/CodeGen/RISCV/usub_sat.ll b/llvm/test/CodeGen/RISCV/usub_sat.ll
index 33056682dcc79..7084885a0ee2c 100644
--- a/llvm/test/CodeGen/RISCV/usub_sat.ll
+++ b/llvm/test/CodeGen/RISCV/usub_sat.ll
@@ -185,3 +185,31 @@ define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
   %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y);
   ret i4 %tmp;
 }
+
+define signext i32 @sat_dec_i32(i32 signext %x) nounwind {
+; RV32I-LABEL: sat_dec_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    snez a1, a0
+; RV32I-NEXT:    sub a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: sat_dec_i32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    snez a1, a0
+; RV64I-NEXT:    subw a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32IZbb-LABEL: sat_dec_i32:
+; RV32IZbb:       # %bb.0:
+; RV32IZbb-NEXT:    snez a1, a0
+; RV32IZbb-NEXT:    sub a0, a0, a1
+; RV32IZbb-NEXT:    ret
+;
+; RV64IZbb-LABEL: sat_dec_i32:
+; RV64IZbb:       # %bb.0:
+; RV64IZbb-NEXT:    snez a1, a0
+; RV64IZbb-NEXT:    subw a0, a0, a1
+; RV64IZbb-NEXT:    ret
+  %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 1)
+  ret i32 %tmp
+}

github-actions · 2025-12-01T05:24:47Z

✅ With the latest revision this PR passed the C/C++ code formatter.

RKSimon · 2025-12-01T09:09:35Z

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

+    EVT BoolVT =
+        getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+    SDValue IsNonZero = DAG.getSetCC(dl, BoolVT, LHS, Zero, ISD::SETNE);
+    SDValue Subtrahend = DAG.getBoolExtOrTrunc(IsNonZero, dl, VT, BoolVT);


Doesn't this assume ZeroOrOneBooleanContent? Also what is Subtrahend short for?

Isn't Subtrahend the word for the right hand side of a subtraction?

I learned "minuend" and "subtrahend" from the ZX Spectrum BASIC manual :)

Doesn't this assume ZeroOrOneBooleanContent?

I think so. For ZeroNegativeOneBooleanContent we would need to use ADD instead of SUB.

RKSimon · 2025-12-01T09:10:34Z

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

  assert(VT.isInteger() && "Expected operands to be integers");

+  // usub.sat(a, 1) -> a - zext(a != 0)
+  if (Opcode == ISD::USUBSAT && !VT.isVector() && isOneConstant(RHS)) {


Why no vector support?

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

jayfoad · 2025-12-03T09:21:04Z

Another option is usub.sat(a,1) -> umin(a,a-1). The best option might depend on whether the target has setcc and/or min/max instructions.

topperc · 2025-12-03T18:40:04Z

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

+    SDValue Zero = DAG.getConstant(0, dl, VT);
+    EVT BoolVT =
+        getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+    SDValue IsNonZero = DAG.getSetCC(dl, BoolVT, LHS, Zero, ISD::SETNE);


Do we need to freeze LHS?

https://alive2.llvm.org/ce/z/XSP_Sj

That shows that it works with freeze. Looks like it fails if the freeze is removed?

RKSimon · 2025-12-04T15:22:56Z

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

+    SDValue Zero = DAG.getConstant(0, dl, VT);
+    EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+    SDValue IsNonZero = DAG.getSetCC(dl, BoolVT, LHS, Zero, ISD::SETNE);
+    SDValue Subtrahend = DAG.getZExtOrTrunc(IsNonZero, dl, VT);


This isn't going to work as BoolVT might already be the same size as VT

You might have to do this:

SDValue Subtrahend = DAG.getBoolExtOrTrunc(IsNonZero, dl, VT); Subtrahend = getNode(ISD::AND, DL, VT, Subtrahend, getConstant(1, DL, VT));

RKSimon · 2025-12-04T16:08:39Z

@rez5427 I've added x86 test coverage at #170681 - you will need to merge and update the test after it lands

…llvm#170681)

topperc · 2025-12-05T01:27:06Z

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

  assert(VT.isInteger() && "Expected operands to be integers");

+  // usub.sat(a, 1) -> sub(a, zext(a != 0))
+  if (Opcode == ISD::USUBSAT && isOneConstant(RHS)) {


isOneConstant only returns true for scalar. So this still doesn't support vector.

I saw some regressions on some test files, I use !VT.isVector() && isOneConstant(RHS) now.

Co-authored-by: Simon Pilgrim <git@redking.me.uk>

rez5427 · 2025-12-06T12:13:35Z

Well, I rebase it, And add freeze, and limit if for scalar, because I saw some regressions on test files.

llvmbot added backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well labels Dec 1, 2025

RKSimon reviewed Dec 1, 2025

View reviewed changes

RKSimon requested review from davemgreen, jayfoad and topperc December 1, 2025 09:12

RKSimon reviewed Dec 3, 2025

View reviewed changes

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp Outdated Show resolved Hide resolved

topperc reviewed Dec 3, 2025

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RKSimon reviewed Dec 4, 2025

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RKSimon added a commit to RKSimon/llvm-project that referenced this pull request Dec 4, 2025

[X86] combine-sub-usat.ll - add test coverage inspired by llvm#170076

316a91a

RKSimon added a commit to RKSimon/llvm-project that referenced this pull request Dec 4, 2025

[X86] combine-sub-usat.ll - add test coverage inspired by llvm#170076

fd62197

alanzhao1 pushed a commit to alanzhao1/llvm-project that referenced this pull request Dec 4, 2025

[X86] combine-sub-usat.ll - add test coverage inspired by llvm#170076 (…

b109bf5

…llvm#170681)

topperc reviewed Dec 5, 2025

View reviewed changes

Jian1.Guan and others added 4 commits December 6, 2025 14:14

[SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0)

701bcdf

Update llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

2cc21b2

Co-authored-by: Simon Pilgrim <git@redking.me.uk>

Use getZExtOrTrunc

87c6428

Add getBoolExtOrTrunc and and

0c20d33

rez5427 force-pushed the usubsat branch from 383cbed to 8f7054c Compare December 6, 2025 12:11

llvmbot added the backend:X86 label Dec 6, 2025

Add freeze, ban vector

ae1bccf

rez5427 force-pushed the usubsat branch from 8f7054c to ae1bccf Compare December 6, 2025 12:14

[SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0) #170076

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[SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0) #170076

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