From bb9b1a9353e3c5ddc74ae9beae912c40d422d1ed Mon Sep 17 00:00:00 2001 From: Jasmine Tang Date: Mon, 1 Dec 2025 04:47:34 -0800 Subject: [PATCH 1/3] Precommit --- .../test/CodeGen/WebAssembly/masked-shifts.ll | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/llvm/test/CodeGen/WebAssembly/masked-shifts.ll b/llvm/test/CodeGen/WebAssembly/masked-shifts.ll index 368f30fd5d7ed..bcec9ed43a773 100644 --- a/llvm/test/CodeGen/WebAssembly/masked-shifts.ll +++ b/llvm/test/CodeGen/WebAssembly/masked-shifts.ll @@ -46,6 +46,23 @@ define i32 @sra_i32(i32 %v, i32 %x) { ret i32 %a } +define i64 @sra_i64_zext(i64 %v, i32 %x) { +; CHECK-LABEL: sra_i64_zext: +; CHECK: .functype sra_i64_zext (i64, i32) -> (i64) +; CHECK-NEXT: # %bb.0: +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: i32.const 63 +; CHECK-NEXT: i32.and +; CHECK-NEXT: i64.extend_i32_u +; CHECK-NEXT: i64.shr_s +; CHECK-NEXT: # fallthrough-return + %m = and i32 %x, 63 + %z = zext i32 %m to i64 + %a = ashr i64 %v, %z + ret i64 %a +} + define i32 @srl_i32(i32 %v, i32 %x) { ; CHECK-LABEL: srl_i32: ; CHECK: .functype srl_i32 (i32, i32) -> (i32) @@ -59,6 +76,24 @@ define i32 @srl_i32(i32 %v, i32 %x) { ret i32 %a } +define i64 @srl_i64_zext(i64 %v, i32 %x) { +; CHECK-LABEL: srl_i64_zext: +; CHECK: .functype srl_i64_zext (i64, i32) -> (i64) +; CHECK-NEXT: # %bb.0: +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: i32.const 63 +; CHECK-NEXT: i32.and +; CHECK-NEXT: i64.extend_i32_u +; CHECK-NEXT: i64.shr_u +; CHECK-NEXT: # fallthrough-return + %m = and i32 %x, 63 + %z = zext i32 %m to i64 + %a = lshr i64 %v, %z + ret i64 %a +} + + define i64 @shl_i64(i64 %v, i64 %x) { ; CHECK-LABEL: shl_i64: ; CHECK: .functype shl_i64 (i64, i64) -> (i64) From 219c674127242bad97d6e328745f5997dd667531 Mon Sep 17 00:00:00 2001 From: Jasmine Tang Date: Mon, 1 Dec 2025 04:52:22 -0800 Subject: [PATCH 2/3] Optimize away mask of 63 for sra and srl ( zext (and i32 63))) --- llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td | 4 ++++ llvm/test/CodeGen/WebAssembly/masked-shifts.ll | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td index eb692679f5971..991507e883f28 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td @@ -109,6 +109,10 @@ def : Pat<(rotr I64:$lhs, (and I64:$rhs, 63)), (ROTR_I64 I64:$lhs, I64:$rhs)>; def : Pat<(shl I64:$lhs, (zext (and I32:$rhs, 63))), (SHL_I64 I64:$lhs, (I64_EXTEND_U_I32 I32:$rhs))>; +def : Pat<(sra I64:$lhs, (zext (and I32:$rhs, 63))), + (SHR_S_I64 I64:$lhs, (I64_EXTEND_U_I32 I32:$rhs))>; +def : Pat<(srl I64:$lhs, (zext (and I32:$rhs, 63))), + (SHR_U_I64 I64:$lhs, (I64_EXTEND_U_I32 I32:$rhs))>; defm SELECT_I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs, I32:$cond), (outs), (ins), diff --git a/llvm/test/CodeGen/WebAssembly/masked-shifts.ll b/llvm/test/CodeGen/WebAssembly/masked-shifts.ll index bcec9ed43a773..95b0a8a866eb1 100644 --- a/llvm/test/CodeGen/WebAssembly/masked-shifts.ll +++ b/llvm/test/CodeGen/WebAssembly/masked-shifts.ll @@ -52,8 +52,6 @@ define i64 @sra_i64_zext(i64 %v, i32 %x) { ; CHECK-NEXT: # %bb.0: ; CHECK-NEXT: local.get 0 ; CHECK-NEXT: local.get 1 -; CHECK-NEXT: i32.const 63 -; CHECK-NEXT: i32.and ; CHECK-NEXT: i64.extend_i32_u ; CHECK-NEXT: i64.shr_s ; CHECK-NEXT: # fallthrough-return @@ -82,8 +80,6 @@ define i64 @srl_i64_zext(i64 %v, i32 %x) { ; CHECK-NEXT: # %bb.0: ; CHECK-NEXT: local.get 0 ; CHECK-NEXT: local.get 1 -; CHECK-NEXT: i32.const 63 -; CHECK-NEXT: i32.and ; CHECK-NEXT: i64.extend_i32_u ; CHECK-NEXT: i64.shr_u ; CHECK-NEXT: # fallthrough-return From 89b3cf18e42dcc8895b943c2b3b5d07c2bac2689 Mon Sep 17 00:00:00 2001 From: Jasmine Tang Date: Tue, 2 Dec 2025 09:50:50 -0800 Subject: [PATCH 3/3] Fix added extra newline --- llvm/test/CodeGen/WebAssembly/masked-shifts.ll | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/test/CodeGen/WebAssembly/masked-shifts.ll b/llvm/test/CodeGen/WebAssembly/masked-shifts.ll index 95b0a8a866eb1..8f90fa68e8fbd 100644 --- a/llvm/test/CodeGen/WebAssembly/masked-shifts.ll +++ b/llvm/test/CodeGen/WebAssembly/masked-shifts.ll @@ -89,7 +89,6 @@ define i64 @srl_i64_zext(i64 %v, i32 %x) { ret i64 %a } - define i64 @shl_i64(i64 %v, i64 %x) { ; CHECK-LABEL: shl_i64: ; CHECK: .functype shl_i64 (i64, i64) -> (i64)