[RISCV] Add Propeller support for RISC-V #170992

leidian977 · 2025-12-06T18:23:44Z

Summary

This PR adds Propeller optimization framework support to the RISC-V backend.

Motivation

Currently, LLVM's Propeller is only supported on x86 and aarch64. This limits profile-guided
optimizations for RISC-V targets. This patch extends Propeller support to RISC-V.

github-actions · 2025-12-06T18:24:04Z

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llvmbot · 2025-12-06T18:24:35Z

@llvm/pr-subscribers-backend-risc-v

Author: None (leidian977)

Changes

Summary

This PR adds Propeller optimization framework support to the RISC-V backend.

Motivation

Currently, LLVM's Propeller is only supported on x86. This limits profile-guided
optimizations for RISC-V targets. This patch extends Propeller support to RISC-V.

Full diff: https://github.com/llvm/llvm-project/pull/170992.diff

3 Files Affected:

(modified) clang/lib/Driver/ToolChains/Clang.cpp (+7)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+9)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+3)

diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index 0380568412e62..d6b93777b8dd1 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -6128,6 +6128,13 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
             << A->getAsString(Args) << A->getValue();
       else
         A->render(Args, CmdArgs);
+    } else if (Triple.isRISCV() && Triple.isOSBinFormatELF()) {
+      // Add RISC-V support for basic block sections
+      if (Val != "labels" && Val != "none" && !Val.starts_with("list="))
+        D.Diag(diag::err_drv_invalid_value)
+            << A->getAsString(Args) << A->getValue();
+      else
+        A->render(Args, CmdArgs);
     } else if (Triple.isNVPTX()) {
       // Do not pass the option to the GPU compilation. We still want it enabled
       // for the host-side compilation, so seeing it here is not an error.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 9fb7ac0573824..269a3ca539635 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -89,6 +89,15 @@ RISCVInstrInfo::RISCVInstrInfo(const RISCVSubtarget &STI)
 #define GET_INSTRINFO_HELPERS
 #include "RISCVGenInstrInfo.inc"
 
+void RISCVInstrInfo::insertNoop(MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator MI) const {
+  DebugLoc DL;
+  BuildMI(MBB, MI, DL, get(RISCV::ADDI))
+      .addReg(RISCV::X0)
+      .addReg(RISCV::X0)
+      .addImm(0);
+}
+
 MCInst RISCVInstrInfo::getNop() const {
   if (STI.hasStdExtZca())
     return MCInstBuilder(RISCV::C_NOP);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 0ffe015b9fac8..bf12c1900be25 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -86,6 +86,9 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 
   const RISCVRegisterInfo &getRegisterInfo() const { return RegInfo; }
 
+  void insertNoop(MachineBasicBlock &MBB,
+                  MachineBasicBlock::iterator MI) const override;
+
   MCInst getNop() const override;
 
   Register isLoadFromStackSlot(const MachineInstr &MI,

llvmbot · 2025-12-06T18:24:35Z

@llvm/pr-subscribers-clang-driver

Author: None (leidian977)

Changes

Summary

This PR adds Propeller optimization framework support to the RISC-V backend.

Motivation

Currently, LLVM's Propeller is only supported on x86. This limits profile-guided
optimizations for RISC-V targets. This patch extends Propeller support to RISC-V.

Full diff: https://github.com/llvm/llvm-project/pull/170992.diff

3 Files Affected:

(modified) clang/lib/Driver/ToolChains/Clang.cpp (+7)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+9)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+3)

diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index 0380568412e62..d6b93777b8dd1 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -6128,6 +6128,13 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
             << A->getAsString(Args) << A->getValue();
       else
         A->render(Args, CmdArgs);
+    } else if (Triple.isRISCV() && Triple.isOSBinFormatELF()) {
+      // Add RISC-V support for basic block sections
+      if (Val != "labels" && Val != "none" && !Val.starts_with("list="))
+        D.Diag(diag::err_drv_invalid_value)
+            << A->getAsString(Args) << A->getValue();
+      else
+        A->render(Args, CmdArgs);
     } else if (Triple.isNVPTX()) {
       // Do not pass the option to the GPU compilation. We still want it enabled
       // for the host-side compilation, so seeing it here is not an error.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 9fb7ac0573824..269a3ca539635 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -89,6 +89,15 @@ RISCVInstrInfo::RISCVInstrInfo(const RISCVSubtarget &STI)
 #define GET_INSTRINFO_HELPERS
 #include "RISCVGenInstrInfo.inc"
 
+void RISCVInstrInfo::insertNoop(MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator MI) const {
+  DebugLoc DL;
+  BuildMI(MBB, MI, DL, get(RISCV::ADDI))
+      .addReg(RISCV::X0)
+      .addReg(RISCV::X0)
+      .addImm(0);
+}
+
 MCInst RISCVInstrInfo::getNop() const {
   if (STI.hasStdExtZca())
     return MCInstBuilder(RISCV::C_NOP);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 0ffe015b9fac8..bf12c1900be25 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -86,6 +86,9 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 
   const RISCVRegisterInfo &getRegisterInfo() const { return RegInfo; }
 
+  void insertNoop(MachineBasicBlock &MBB,
+                  MachineBasicBlock::iterator MI) const override;
+
   MCInst getNop() const override;
 
   Register isLoadFromStackSlot(const MachineInstr &MI,

wangpc-pp

Thanks! We are interested in this work!

There are some suggestions:

Please add some tests for these driver changes.
Can you describe what we are missing for the support of Propeller in the middle/back ends? For example, I don't know the relationship between Propeller and insertNoop.
Can you show the current status and the state after your changes? Have you tried it on real hardware and do we need anything else to make Propeller work?

clang/lib/Driver/ToolChains/Clang.cpp

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

leidian977 · 2025-12-08T15:45:45Z

Thanks! We are interested in this work!

There are some suggestions:

1. Please add some tests for these driver changes.

2. Can you describe what we are missing for the support of Propeller in the middle/back ends? For example, I don't know the relationship between Propeller and `insertNoop`.

3. Can you show the current status and the state after your changes? Have you tried it on real hardware and do we need anything else to make Propeller work?

1.I've added the tests. Please take a look.

2.The Basic Block Sections feature requires inserting NOP instructions in certain cases to avoid zero-offset exception landing pads.When I compile 510.parest_r from SPEC CPU2017 using the propeller feature, it triggers:

Target didn't implement insertNoop!
UNREACHABLE executed at llvm/lib/CodeGen/TargetInstrInfo.cpp:84!
......
Running pass 'Function Pass Manager' on module 'ld-temp.o'.
Running pass 'Basic Block Sections Analysis' on function '@_GLOBAL__sub_I_Compute.C' #0 0x00007ed74bafaefc llvm::sys::PrintStackTrace(llvm::raw_ostream&, int)
......
ErrorHandling.cpp:242:55 #11 0x00007ed7449f858c llvm::TargetInstrInfo::insertNoops(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, unsigned int) const llvm/lib/CodeGen/TargetInstrInfo.cpp:91:60 #12 0x0000

Successfully implemented and tested the Propeller feature on RISC-V Clang

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

wangpc-pp

LGTM. Thanks!

topperc

LGTM

[RISCV] Add basic Propeller infrastructure

c906914

llvmbot added backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' labels Dec 6, 2025

wangpc-pp reviewed Dec 8, 2025

View reviewed changes

topperc reviewed Dec 8, 2025

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clang/lib/Driver/ToolChains/Clang.cpp Show resolved Hide resolved

topperc reviewed Dec 8, 2025

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llvm/lib/Target/RISCV/RISCVInstrInfo.cpp Show resolved Hide resolved

leidian977 added 2 commits December 8, 2025 10:00

[RISCV] Add basic Propeller Test

8d37c32

[RISCV] update RISCVInstrInfo::insertNoop

bf8eeb6

wangpc-pp reviewed Dec 9, 2025

View reviewed changes

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp Outdated Show resolved Hide resolved

[RISCV] update RISCVInstrInfo::insertNoop

e799179

wangpc-pp approved these changes Dec 9, 2025

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topperc approved these changes Dec 9, 2025

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[RISCV] Add Propeller support for RISC-V #170992

[RISCV] Add Propeller support for RISC-V #170992

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