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[MCAsmStreamer] Print register names in --show-inst mode #171252

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Merged
arichardson merged 1 commit into from
Dec 9, 2025
Merged

[MCAsmStreamer] Print register names in --show-inst mode #171252

arichardson merged 1 commit into from
Dec 9, 2025

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@arichardson arichardson commented Dec 9, 2025

Passing the context to Inst.dump_pretty() allows printing symbolic
register names instead of <MCOperand Reg:1234> in the output.
I plan to use this in a future RVY test cases where we have register
class with the same name in assembly syntax, but different underlying
register enum values. Printing the name of the enum value makes it
easier to test that we selected the correct register.

@arichardson
[𝘀𝗽𝗿] initial version
621a15d 
Created using spr 1.3.8-beta.1
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llvmbot commented Dec 9, 2025 •
edited
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@llvm/pr-subscribers-llvm-mc
@llvm/pr-subscribers-backend-amdgpu

@llvm/pr-subscribers-backend-mips

Author: Alexander Richardson (arichardson)

Changes

Passing the context to Inst.dump_pretty() allows printing symbolic
register names instead of &lt;MCOperand Reg:1234&gt; in the output.
I plan to use this in a future RVY test cases where we have register
class with the same name in assembly syntax, but different underlying
register enum values. Printing the name of the enum value makes it
easier to test that we selected the correct register.

Patch is 236.12 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/171252.diff

11 Files Affected:

  • (modified) llvm/lib/MC/MCAsmStreamer.cpp (+1-1)
  • (modified) llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll (+148-148)
  • (modified) llvm/test/CodeGen/Mips/llvm-ir/load.ll (+795-795)
  • (modified) llvm/test/CodeGen/Mips/llvm-ir/store.ll (+450-450)
  • (modified) llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll (+40-40)
  • (modified) llvm/test/CodeGen/Mips/setcc-se.ll (+157-157)
  • (modified) llvm/test/MC/AMDGPU/buffer-op-swz-operand.s (+12-12)
  • (modified) llvm/test/MC/Disassembler/ARM/sub-sp-imm-thumb2.txt (+11-11)
  • (modified) llvm/test/MC/Lanai/conditional_inst.s (+10-10)
  • (modified) llvm/test/MC/Lanai/memory.s (+66-66)
  • (modified) llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/asm-show-inst.ll.expected (+12-12)
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index 885fa55b65d50..e2543058394a2 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -2452,7 +2452,7 @@ void MCAsmStreamer::emitInstruction(const MCInst &Inst,
 
   // Show the MCInst if enabled.
   if (ShowInst) {
-    Inst.dump_pretty(getCommentOS(), InstPrinter.get(), "\n ");
+    Inst.dump_pretty(getCommentOS(), InstPrinter.get(), "\n ", &getContext());
     getCommentOS() << "\n";
   }
 
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
index 79fe2fd26a6e2..a5be8ca28bf00 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
@@ -39,123 +39,123 @@ define i32 @test1(float %t) {
 ; M32-LABEL: test1:
 ; M32:       # %bb.0: # %entry
 ; M32-NEXT:    trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
-; M32-NEXT:    # <MCOperand Reg:[[#MCREG1:]]>
-; M32-NEXT:    # <MCOperand Reg:[[#MCREG2:]]>>
+; M32-NEXT:    # <MCOperand Reg:F0>
+; M32-NEXT:    # <MCOperand Reg:F12>>
 ; M32-NEXT:    jr $ra # <MCInst #[[#MCINST2:]] JR
-; M32-NEXT:    # <MCOperand Reg:[[#MCREG3:]]>>
+; M32-NEXT:    # <MCOperand Reg:RA>>
 ; M32-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M32-NEXT:    # <MCOperand Reg:[[#MCREG4:]]>
-; M32-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; M32-NEXT:    # <MCOperand Reg:V0>
+; M32-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; M32R2-FP64-LABEL: test1:
 ; M32R2-FP64:       # %bb.0: # %entry
 ; M32R2-FP64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
-; M32R2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG1:]]>
-; M32R2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG2:]]>>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:F0>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:F12>>
 ; M32R2-FP64-NEXT:    jr $ra # <MCInst #[[#MCINST2:]] JR
-; M32R2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG3:]]>>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:RA>>
 ; M32R2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M32R2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG4:]]>
-; M32R2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:V0>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; M32R2-SF-LABEL: test1:
 ; M32R2-SF:       # %bb.0: # %entry
 ; M32R2-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #[[#MCINST4:]] ADDiu
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5:]]>
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; M32R2-SF-NEXT:    # <MCOperand Reg:SP>
+; M32R2-SF-NEXT:    # <MCOperand Reg:SP>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:-24>>
 ; M32R2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; M32R2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; M32R2-SF-NEXT:    # <MCInst #[[#MCINST5:]] SW
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG3:]]>
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; M32R2-SF-NEXT:    # <MCOperand Reg:RA>
+; M32R2-SF-NEXT:    # <MCOperand Reg:SP>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
 ; M32R2-SF-NEXT:    .cfi_offset 31, -4
 ; M32R2-SF-NEXT:    jal __fixsfsi # <MCInst #[[#MCINST6:]] JAL
 ; M32R2-SF-NEXT:    # <MCOperand Expr:__fixsfsi>>
 ; M32R2-SF-NEXT:    nop # <MCInst #[[#MCINST7:]] SLL
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG6:]]>
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG6]]>
+; M32R2-SF-NEXT:    # <MCOperand Reg:ZERO>
+; M32R2-SF-NEXT:    # <MCOperand Reg:ZERO>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:0>>
 ; M32R2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; M32R2-SF-NEXT:    # <MCInst #[[#MCINST8:]] LW
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG3]]>
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; M32R2-SF-NEXT:    # <MCOperand Reg:RA>
+; M32R2-SF-NEXT:    # <MCOperand Reg:SP>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
 ; M32R2-SF-NEXT:    jr $ra # <MCInst #[[#MCINST2:]] JR
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG3]]>>
+; M32R2-SF-NEXT:    # <MCOperand Reg:RA>>
 ; M32R2-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; M32R2-SF-NEXT:    # <MCOperand Reg:SP>
+; M32R2-SF-NEXT:    # <MCOperand Reg:SP>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:24>>
 ;
 ; M32R3R5-LABEL: test1:
 ; M32R3R5:       # %bb.0: # %entry
 ; M32R3R5-NEXT:    trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
-; M32R3R5-NEXT:    # <MCOperand Reg:[[#MCREG1:]]>
-; M32R3R5-NEXT:    # <MCOperand Reg:[[#MCREG2:]]>>
+; M32R3R5-NEXT:    # <MCOperand Reg:F0>
+; M32R3R5-NEXT:    # <MCOperand Reg:F12>>
 ; M32R3R5-NEXT:    jr $ra # <MCInst #[[#MCINST2:]] JR
-; M32R3R5-NEXT:    # <MCOperand Reg:[[#MCREG3:]]>>
+; M32R3R5-NEXT:    # <MCOperand Reg:RA>>
 ; M32R3R5-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M32R3R5-NEXT:    # <MCOperand Reg:[[#MCREG4:]]>
-; M32R3R5-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; M32R3R5-NEXT:    # <MCOperand Reg:V0>
+; M32R3R5-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; M32R6-LABEL: test1:
 ; M32R6:       # %bb.0: # %entry
 ; M32R6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
-; M32R6-NEXT:    # <MCOperand Reg:[[#MCREG1:]]>
-; M32R6-NEXT:    # <MCOperand Reg:[[#MCREG2:]]>>
+; M32R6-NEXT:    # <MCOperand Reg:F0>
+; M32R6-NEXT:    # <MCOperand Reg:F12>>
 ; M32R6-NEXT:    jr $ra # <MCInst #[[#MCINST9:]] JALR
-; M32R6-NEXT:    # <MCOperand Reg:[[#MCREG6:]]>
-; M32R6-NEXT:    # <MCOperand Reg:[[#MCREG3:]]>>
+; M32R6-NEXT:    # <MCOperand Reg:ZERO>
+; M32R6-NEXT:    # <MCOperand Reg:RA>>
 ; M32R6-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M32R6-NEXT:    # <MCOperand Reg:[[#MCREG4:]]>
-; M32R6-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; M32R6-NEXT:    # <MCOperand Reg:V0>
+; M32R6-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; M64-LABEL: test1:
 ; M64:       # %bb.0: # %entry
 ; M64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
-; M64-NEXT:    # <MCOperand Reg:[[#MCREG1:]]>
-; M64-NEXT:    # <MCOperand Reg:[[#MCREG2:]]>>
+; M64-NEXT:    # <MCOperand Reg:F0>
+; M64-NEXT:    # <MCOperand Reg:F12>>
 ; M64-NEXT:    jr $ra # <MCInst #[[#MCINST2:]] JR
-; M64-NEXT:    # <MCOperand Reg:[[#MCREG7:]]>>
+; M64-NEXT:    # <MCOperand Reg:RA_64>>
 ; M64-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M64-NEXT:    # <MCOperand Reg:[[#MCREG4:]]>
-; M64-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; M64-NEXT:    # <MCOperand Reg:V0>
+; M64-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; M64R6-LABEL: test1:
 ; M64R6:       # %bb.0: # %entry
 ; M64R6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
-; M64R6-NEXT:    # <MCOperand Reg:[[#MCREG1:]]>
-; M64R6-NEXT:    # <MCOperand Reg:[[#MCREG2:]]>>
+; M64R6-NEXT:    # <MCOperand Reg:F0>
+; M64R6-NEXT:    # <MCOperand Reg:F12>>
 ; M64R6-NEXT:    jr $ra # <MCInst #[[#MCINST10:]] JALR64
-; M64R6-NEXT:    # <MCOperand Reg:[[#MCREG8:]]>
-; M64R6-NEXT:    # <MCOperand Reg:[[#MCREG7:]]>>
+; M64R6-NEXT:    # <MCOperand Reg:ZERO_64>
+; M64R6-NEXT:    # <MCOperand Reg:RA_64>>
 ; M64R6-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
-; M64R6-NEXT:    # <MCOperand Reg:[[#MCREG4:]]>
-; M64R6-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; M64R6-NEXT:    # <MCOperand Reg:V0>
+; M64R6-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; MMR2-FP32-LABEL: test1:
 ; MMR2-FP32:       # %bb.0: # %entry
 ; MMR2-FP32-NEXT:    trunc.w.s $f0, $f12 # <MCInst #[[#MCINST11:]] TRUNC_W_S_MM
-; MMR2-FP32-NEXT:    # <MCOperand Reg:[[#MCREG1:]]>
-; MMR2-FP32-NEXT:    # <MCOperand Reg:[[#MCREG2:]]>>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:F0>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:F12>>
 ; MMR2-FP32-NEXT:    jr $ra # <MCInst #[[#MCINST12:]] JR_MM
-; MMR2-FP32-NEXT:    # <MCOperand Reg:[[#MCREG3:]]>>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:RA>>
 ; MMR2-FP32-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
-; MMR2-FP32-NEXT:    # <MCOperand Reg:[[#MCREG4:]]>
-; MMR2-FP32-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:V0>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; MMR2-FP64-LABEL: test1:
 ; MMR2-FP64:       # %bb.0: # %entry
 ; MMR2-FP64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #[[#MCINST11:]] TRUNC_W_S_MM
-; MMR2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG1:]]>
-; MMR2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG2:]]>>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:F0>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:F12>>
 ; MMR2-FP64-NEXT:    jr $ra # <MCInst #[[#MCINST12:]] JR_MM
-; MMR2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG3:]]>>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:RA>>
 ; MMR2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
-; MMR2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG4:]]>
-; MMR2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:V0>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; MMR2-SF-LABEL: test1:
 ; MMR2-SF:       # %bb.0: # %entry
@@ -164,63 +164,63 @@ define i32 @test1(float %t) {
 ; MMR2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; MMR2-SF-NEXT:    # <MCInst #[[#MCINST15:]] SWSP_MM
-; MMR2-SF-NEXT:    # <MCOperand Reg:[[#MCREG3:]]>
-; MMR2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5:]]>
+; MMR2-SF-NEXT:    # <MCOperand Reg:RA>
+; MMR2-SF-NEXT:    # <MCOperand Reg:SP>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR2-SF-NEXT:    .cfi_offset 31, -4
 ; MMR2-SF-NEXT:    jal __fixsfsi # <MCInst #[[#MCINST16:]] JAL_MM
 ; MMR2-SF-NEXT:    # <MCOperand Expr:__fixsfsi>>
 ; MMR2-SF-NEXT:    nop # <MCInst #[[#MCINST17:]] SLL_MM
-; MMR2-SF-NEXT:    # <MCOperand Reg:[[#MCREG6:]]>
-; MMR2-SF-NEXT:    # <MCOperand Reg:[[#MCREG6]]>
+; MMR2-SF-NEXT:    # <MCOperand Reg:ZERO>
+; MMR2-SF-NEXT:    # <MCOperand Reg:ZERO>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:0>>
 ; MMR2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; MMR2-SF-NEXT:    # <MCInst #[[#MCINST18:]] LWSP_MM
-; MMR2-SF-NEXT:    # <MCOperand Reg:[[#MCREG3]]>
-; MMR2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; MMR2-SF-NEXT:    # <MCOperand Reg:RA>
+; MMR2-SF-NEXT:    # <MCOperand Reg:SP>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR2-SF-NEXT:    addiusp 24 # <MCInst #[[#MCINST14]] ADDIUSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Imm:24>>
 ; MMR2-SF-NEXT:    jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
-; MMR2-SF-NEXT:    # <MCOperand Reg:[[#MCREG3]]>>
+; MMR2-SF-NEXT:    # <MCOperand Reg:RA>>
 ;
 ; MMR6-LABEL: test1:
 ; MMR6:       # %bb.0: # %entry
 ; MMR6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #[[#MCINST20:]] TRUNC_W_S_MMR6
-; MMR6-NEXT:    # <MCOperand Reg:[[#MCREG1:]]>
-; MMR6-NEXT:    # <MCOperand Reg:[[#MCREG2:]]>>
+; MMR6-NEXT:    # <MCOperand Reg:F0>
+; MMR6-NEXT:    # <MCOperand Reg:F12>>
 ; MMR6-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
-; MMR6-NEXT:    # <MCOperand Reg:[[#MCREG4:]]>
-; MMR6-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; MMR6-NEXT:    # <MCOperand Reg:V0>
+; MMR6-NEXT:    # <MCOperand Reg:F0>>
 ; MMR6-NEXT:    jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
-; MMR6-NEXT:    # <MCOperand Reg:[[#MCREG3:]]>>
+; MMR6-NEXT:    # <MCOperand Reg:RA>>
 ;
 ; MMR6-SF-LABEL: test1:
 ; MMR6-SF:       # %bb.0: # %entry
 ; MMR6-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #[[#MCINST4:]] ADDiu
-; MMR6-SF-NEXT:    # <MCOperand Reg:[[#MCREG5:]]>
-; MMR6-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; MMR6-SF-NEXT:    # <MCOperand Reg:SP>
+; MMR6-SF-NEXT:    # <MCOperand Reg:SP>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR6-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR6-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; MMR6-SF-NEXT:    # <MCInst #[[#MCINST5:]] SW
-; MMR6-SF-NEXT:    # <MCOperand Reg:[[#MCREG3:]]>
-; MMR6-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; MMR6-SF-NEXT:    # <MCOperand Reg:RA>
+; MMR6-SF-NEXT:    # <MCOperand Reg:SP>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    .cfi_offset 31, -4
 ; MMR6-SF-NEXT:    balc __fixsfsi # <MCInst #[[#MCINST21:]] BALC_MMR6
 ; MMR6-SF-NEXT:    # <MCOperand Expr:__fixsfsi>>
 ; MMR6-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; MMR6-SF-NEXT:    # <MCInst #[[#MCINST8:]] LW
-; MMR6-SF-NEXT:    # <MCOperand Reg:[[#MCREG3]]>
-; MMR6-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; MMR6-SF-NEXT:    # <MCOperand Reg:RA>
+; MMR6-SF-NEXT:    # <MCOperand Reg:SP>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
-; MMR6-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
-; MMR6-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; MMR6-SF-NEXT:    # <MCOperand Reg:SP>
+; MMR6-SF-NEXT:    # <MCOperand Reg:SP>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:24>>
 ; MMR6-SF-NEXT:    jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
-; MMR6-SF-NEXT:    # <MCOperand Reg:[[#MCREG3]]>>
+; MMR6-SF-NEXT:    # <MCOperand Reg:RA>>
 entry:
   %conv = fptosi float %t to i32
   ret i32 %conv
@@ -230,123 +230,123 @@ define i32 @test2(double %t) {
 ; M32-LABEL: test2:
 ; M32:       # %bb.0: # %entry
 ; M32-NEXT:    trunc.w.d $f0, $f12 # <MCInst #[[#MCINST22:]] TRUNC_W_D32
-; M32-NEXT:    # <MCOperand Reg:[[#MCREG1]]>
-; M32-NEXT:    # <MCOperand Reg:[[#MCREG9:]]>>
+; M32-NEXT:    # <MCOperand Reg:F0>
+; M32-NEXT:    # <MCOperand Reg:D6>>
 ; M32-NEXT:    jr $ra # <MCInst #[[#MCINST2]] JR
-; M32-NEXT:    # <MCOperand Reg:[[#MCREG3]]>>
+; M32-NEXT:    # <MCOperand Reg:RA>>
 ; M32-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M32-NEXT:    # <MCOperand Reg:[[#MCREG4]]>
-; M32-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; M32-NEXT:    # <MCOperand Reg:V0>
+; M32-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; M32R2-FP64-LABEL: test2:
 ; M32R2-FP64:       # %bb.0: # %entry
 ; M32R2-FP64-NEXT:    trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64
-; M32R2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG1]]>
-; M32R2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG10:]]>>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:F0>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:D12_64>>
 ; M32R2-FP64-NEXT:    jr $ra # <MCInst #[[#MCINST2]] JR
-; M32R2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG3]]>>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:RA>>
 ; M32R2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M32R2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG4]]>
-; M32R2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:V0>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; M32R2-SF-LABEL: test2:
 ; M32R2-SF:       # %bb.0: # %entry
 ; M32R2-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #[[#MCINST4]] ADDiu
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; M32R2-SF-NEXT:    # <MCOperand Reg:SP>
+; M32R2-SF-NEXT:    # <MCOperand Reg:SP>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:-24>>
 ; M32R2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; M32R2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; M32R2-SF-NEXT:    # <MCInst #[[#MCINST5]] SW
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG3]]>
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; M32R2-SF-NEXT:    # <MCOperand Reg:RA>
+; M32R2-SF-NEXT:    # <MCOperand Reg:SP>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
 ; M32R2-SF-NEXT:    .cfi_offset 31, -4
 ; M32R2-SF-NEXT:    jal __fixdfsi # <MCInst #[[#MCINST6]] JAL
 ; M32R2-SF-NEXT:    # <MCOperand Expr:__fixdfsi>>
 ; M32R2-SF-NEXT:    nop # <MCInst #[[#MCINST7]] SLL
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG6]]>
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG6]]>
+; M32R2-SF-NEXT:    # <MCOperand Reg:ZERO>
+; M32R2-SF-NEXT:    # <MCOperand Reg:ZERO>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:0>>
 ; M32R2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; M32R2-SF-NEXT:    # <MCInst #[[#MCINST8]] LW
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG3]]>
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; M32R2-SF-NEXT:    # <MCOperand Reg:RA>
+; M32R2-SF-NEXT:    # <MCOperand Reg:SP>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
 ; M32R2-SF-NEXT:    jr $ra # <MCInst #[[#MCINST2]] JR
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG3]]>>
+; M32R2-SF-NEXT:    # <MCOperand Reg:RA>>
 ; M32R2-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
-; M32R2-SF-NEXT:    # <MCOperand Reg:[[#MCREG5]]>
+; M32R2-SF-NEXT:    # <MCOperand Reg:SP>
+; M32R2-SF-NEXT:    # <MCOperand Reg:SP>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:24>>
 ;
 ; M32R3R5-LABEL: test2:
 ; M32R3R5:       # %bb.0: # %entry
 ; M32R3R5-NEXT:    trunc.w.d $f0, $f12 # <MCInst #[[#MCINST22:]] TRUNC_W_D32
-; M32R3R5-NEXT:    # <MCOperand Reg:[[#MCREG1]]>
-; M32R3R5-NEXT:    # <MCOperand Reg:[[#MCREG9:]]>>
+; M32R3R5-NEXT:    # <MCOperand Reg:F0>
+; M32R3R5-NEXT:    # <MCOperand Reg:D6>>
 ; M32R3R5-NEXT:    jr $ra # <MCInst #[[#MCINST2]] JR
-; M32R3R5-NEXT:    # <MCOperand Reg:[[#MCREG3]]>>
+; M32R3R5-NEXT:    # <MCOperand Reg:RA>>
 ; M32R3R5-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M32R3R5-NEXT:    # <MCOperand Reg:[[#MCREG4]]>
-; M32R3R5-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; M32R3R5-NEXT:    # <MCOperand Reg:V0>
+; M32R3R5-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; M32R6-LABEL: test2:
 ; M32R6:       # %bb.0: # %entry
 ; M32R6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64
-; M32R6-NEXT:    # <MCOperand Reg:[[#MCREG1]]>
-; M32R6-NEXT:    # <MCOperand Reg:[[#MCREG10:]]>>
+; M32R6-NEXT:    # <MCOperand Reg:F0>
+; M32R6-NEXT:    # <MCOperand Reg:D12_64>>
 ; M32R6-NEXT:    jr $ra # <MCInst #[[#MCINST9]] JALR
-; M32R6-NEXT:    # <MCOperand Reg:[[#MCREG6]]>
-; M32R6-NEXT:    # <MCOperand Reg:[[#MCREG3]]>>
+; M32R6-NEXT:    # <MCOperand Reg:ZERO>
+; M32R6-NEXT:    # <MCOperand Reg:RA>>
 ; M32R6-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M32R6-NEXT:    # <MCOperand Reg:[[#MCREG4]]>
-; M32R6-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; M32R6-NEXT:    # <MCOperand Reg:V0>
+; M32R6-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; M64-LABEL: test2:
 ; M64:       # %bb.0: # %entry
 ; M64-NEXT:    trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64
-; M64-NEXT:    # <MCOperand Reg:[[#MCREG1]]>
-; M64-NEXT:    # <MCOperand Reg:[[#MCREG10:]]>>
+; M64-NEXT:    # <MCOperand Reg:F0>
+; M64-NEXT:    # <MCOperand Reg:D12_64>>
 ; M64-NEXT:    jr $ra # <MCInst #[[#MCINST2]] JR
-; M64-NEXT:    # <MCOperand Reg:[[#MCREG7]]>>
+; M64-NEXT:    # <MCOperand Reg:RA_64>>
 ; M64-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M64-NEXT:    # <MCOperand Reg:[[#MCREG4]]>
-; M64-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; M64-NEXT:    # <MCOperand Reg:V0>
+; M64-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; M64R6-LABEL: test2:
 ; M64R6:       # %bb.0: # %entry
 ; M64R6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64
-; M64R6-NEXT:    # <MCOperand Reg:[[#MCREG1]]>
-; M64R6-NEXT:    # <MCOperand Reg:[[#MCREG10:]]>>
+; M64R6-NEXT:    # <MCOperand Reg:F0>
+; M64R6-NEXT:    # <MCOperand Reg:D12_64>>
 ; M64R6-NEXT:    jr $ra # <MCInst #[[#MCINST10]] JALR64
-; M64R6-NEXT:    # <MCOperand Reg:[[#MCREG8]]>
-; M64R6-NEXT:    # <MCOperand Reg:[[#MCREG7]]>>
+; M64R6-NEXT:    # <MCOperand Reg:ZERO_64>
+; M64R6-NEXT:    # <MCOperand Reg:RA_64>>
 ; M64R6-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
-; M64R6-NEXT:    # <MCOperand Reg:[[#MCREG4]]>
-; M64R6-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; M64R6-NEXT:    # <MCOperand Reg:V0>
+; M64R6-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; MMR2-FP32-LABEL: test2:
 ; MMR2-FP32:       # %bb.0: # %entry
 ; MMR2-FP32-NEXT:    trunc.w.d $f0, $f12 # <MCInst #[[#MCINST24:]] TRUNC_W_MM
-; MMR2-FP32-NEXT:    # <MCOperand Reg:[[#MCREG1]]>
-; MMR2-FP32-NEXT:    # <MCOperand Reg:[[#MCREG9:]]>>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:F0>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:D6>>
 ; MMR2-FP32-NEXT:    jr $ra # <MCInst #[[#MCINST12]] JR_MM
-; MMR2-FP32-NEXT:    # <MCOperand Reg:[[#MCREG3]]>>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:RA>>
 ; MMR2-FP32-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
-; MMR2-FP32-NEXT:    # <MCOperand Reg:[[#MCREG4]]>
-; MMR2-FP32-NEXT:    # <MCOperand Reg:[[#MCREG1]]>>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:V0>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:F0>>
 ;
 ; MMR2-FP64-LABEL: test2:
 ; MMR2-FP64:       # %bb.0: # %entry
 ; MMR2-FP64-NEXT:    cvt.w.d $f0, $f12 # <MCInst #[[#MCINST25:]] CVT_W_D64_MM
-; MMR2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG1]]>
-; MMR2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG10:]]>>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:F0>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:D12_64>>
 ; MMR2-FP64-NEXT:    jr $ra # <MCInst #[[#MCINST12]] JR_MM
-; MMR2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG3]]>>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:RA>>
 ; MMR2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
-; MMR2-FP64-NEXT:    # <MCOperand Reg:[[#MCREG4]]>
-; MMR2-FP64-...
[truncated]

arichardson
arichardson commented Dec 9, 2025
View reviewed changes
llvm/test/MC/Disassembler/ARM/sub-sp-imm-thumb2.txt
# CHECK-NEXT: <MCOperand Imm:14>
# CHECK-NEXT: <MCOperand Reg:0>
# CHECK-NEXT: <MCOperand Reg:0>>
# CHECK-NEXT: <MCOperand Reg:>
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@arichardson arichardson Dec 9, 2025

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Should I add extra logic to print NoRegister here? Or is the empty value fine?

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@lenary lenary Dec 9, 2025

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This could be a follow-up.

lenary
lenary approved these changes Dec 9, 2025
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LGTM. This is debug output, and it's easy to make it better so we should.

@arichardson arichardson merged commit 9baf76a into main Dec 9, 2025
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@arichardson arichardson deleted the users/arichardson/spr/mcasmstreamer-print-register-names-in-show-inst-mode branch December 9, 2025 05:53
llvm-sync bot pushed a commit to arm/arm-toolchain that referenced this pull request Dec 9, 2025
@arichardson @github-actions
Automerge: [MCAsmStreamer] Print register names in --show-inst mode
de53ff9 
Passing the context to `Inst.dump_pretty()` allows printing symbolic
register names instead of `<MCOperand Reg:1234>` in the output.
I plan to use this in a future RVY test cases where we have register
class with the same name in assembly syntax, but different underlying
register enum values. Printing the name of the enum value makes it
easier to test that we selected the correct register.

Reviewed By: lenary

Pull Request: llvm/llvm-project#171252
@MaskRay
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MaskRay commented Dec 9, 2025

Nice!

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@lenary lenary lenary approved these changes

@MaskRay MaskRay Awaiting requested review from MaskRay

@jrbyrnes jrbyrnes Awaiting requested review from jrbyrnes

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@arichardson @llvmbot @MaskRay @lenary