From 0835d709475db3a964b9cc12f33634cd322d0c00 Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Mon, 8 Dec 2025 20:47:59 -0800 Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20change?= =?UTF-8?q?s=20to=20main=20this=20commit=20is=20based=20on?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.8-beta.1 [skip ci] --- llvm/lib/MC/MCAsmStreamer.cpp | 2 +- llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll | 296 +-- llvm/test/CodeGen/Mips/llvm-ir/load.ll | 1590 ++++++++--------- llvm/test/CodeGen/Mips/llvm-ir/store.ll | 900 +++++----- .../Mips/micromips-pseudo-mtlohi-expand.ll | 80 +- llvm/test/CodeGen/Mips/setcc-se.ll | 314 ++-- llvm/test/MC/AMDGPU/buffer-op-swz-operand.s | 24 +- .../MC/Disassembler/ARM/sub-sp-imm-thumb2.txt | 22 +- llvm/test/MC/Lanai/conditional_inst.s | 20 +- llvm/test/MC/Lanai/memory.s | 132 +- .../TableGen/Common/RegClassByHwModeCommon.td | 44 + llvm/test/TableGen/RegClassByHwMode.td | 64 +- llvm/test/TableGen/RegClassByHwModeErrors.td | 88 + .../Inputs/asm-show-inst.ll.expected | 24 +- .../TableGen/Common/CodeGenInstAlias.cpp | 21 +- .../TableGen/Common/CodeGenRegisters.cpp | 12 +- llvm/utils/TableGen/Common/CodeGenRegisters.h | 3 +- llvm/utils/TableGen/Common/CodeGenTarget.cpp | 4 +- llvm/utils/TableGen/Common/CodeGenTarget.h | 3 +- llvm/utils/TableGen/CompressInstEmitter.cpp | 14 +- 20 files changed, 1877 insertions(+), 1780 deletions(-) create mode 100644 llvm/test/TableGen/Common/RegClassByHwModeCommon.td create mode 100644 llvm/test/TableGen/RegClassByHwModeErrors.td diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp index 885fa55b65d50..e2543058394a2 100644 --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -2452,7 +2452,7 @@ void MCAsmStreamer::emitInstruction(const MCInst &Inst, // Show the MCInst if enabled. if (ShowInst) { - Inst.dump_pretty(getCommentOS(), InstPrinter.get(), "\n "); + Inst.dump_pretty(getCommentOS(), InstPrinter.get(), "\n ", &getContext()); getCommentOS() << "\n"; } diff --git a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll index 79fe2fd26a6e2..a5be8ca28bf00 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll @@ -39,123 +39,123 @@ define i32 @test1(float %t) { ; M32-LABEL: test1: ; M32: # %bb.0: # %entry ; M32-NEXT: trunc.w.s $f0, $f12 # -; M32-NEXT: # > +; M32-NEXT: # +; M32-NEXT: # > ; M32-NEXT: jr $ra # > +; M32-NEXT: # > ; M32-NEXT: mfc1 $2, $f0 # -; M32-NEXT: # > +; M32-NEXT: # +; M32-NEXT: # > ; ; M32R2-FP64-LABEL: test1: ; M32R2-FP64: # %bb.0: # %entry ; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # -; M32R2-FP64-NEXT: # > +; M32R2-FP64-NEXT: # +; M32R2-FP64-NEXT: # > ; M32R2-FP64-NEXT: jr $ra # > +; M32R2-FP64-NEXT: # > ; M32R2-FP64-NEXT: mfc1 $2, $f0 # -; M32R2-FP64-NEXT: # > +; M32R2-FP64-NEXT: # +; M32R2-FP64-NEXT: # > ; ; M32R2-SF-LABEL: test1: ; M32R2-SF: # %bb.0: # %entry ; M32R2-SF-NEXT: addiu $sp, $sp, -24 # -; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: .cfi_def_cfa_offset 24 ; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; M32R2-SF-NEXT: # -; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: .cfi_offset 31, -4 ; M32R2-SF-NEXT: jal __fixsfsi # > ; M32R2-SF-NEXT: nop # -; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; M32R2-SF-NEXT: # -; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: jr $ra # > +; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: addiu $sp, $sp, 24 # -; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; ; M32R3R5-LABEL: test1: ; M32R3R5: # %bb.0: # %entry ; M32R3R5-NEXT: trunc.w.s $f0, $f12 # -; M32R3R5-NEXT: # > +; M32R3R5-NEXT: # +; M32R3R5-NEXT: # > ; M32R3R5-NEXT: jr $ra # > +; M32R3R5-NEXT: # > ; M32R3R5-NEXT: mfc1 $2, $f0 # -; M32R3R5-NEXT: # > +; M32R3R5-NEXT: # +; M32R3R5-NEXT: # > ; ; M32R6-LABEL: test1: ; M32R6: # %bb.0: # %entry ; M32R6-NEXT: trunc.w.s $f0, $f12 # -; M32R6-NEXT: # > +; M32R6-NEXT: # +; M32R6-NEXT: # > ; M32R6-NEXT: jr $ra # -; M32R6-NEXT: # > +; M32R6-NEXT: # +; M32R6-NEXT: # > ; M32R6-NEXT: mfc1 $2, $f0 # -; M32R6-NEXT: # > +; M32R6-NEXT: # +; M32R6-NEXT: # > ; ; M64-LABEL: test1: ; M64: # %bb.0: # %entry ; M64-NEXT: trunc.w.s $f0, $f12 # -; M64-NEXT: # > +; M64-NEXT: # +; M64-NEXT: # > ; M64-NEXT: jr $ra # > +; M64-NEXT: # > ; M64-NEXT: mfc1 $2, $f0 # -; M64-NEXT: # > +; M64-NEXT: # +; M64-NEXT: # > ; ; M64R6-LABEL: test1: ; M64R6: # %bb.0: # %entry ; M64R6-NEXT: trunc.w.s $f0, $f12 # -; M64R6-NEXT: # > +; M64R6-NEXT: # +; M64R6-NEXT: # > ; M64R6-NEXT: jr $ra # -; M64R6-NEXT: # > +; M64R6-NEXT: # +; M64R6-NEXT: # > ; M64R6-NEXT: mfc1 $2, $f0 # -; M64R6-NEXT: # > +; M64R6-NEXT: # +; M64R6-NEXT: # > ; ; MMR2-FP32-LABEL: test1: ; MMR2-FP32: # %bb.0: # %entry ; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # -; MMR2-FP32-NEXT: # > +; MMR2-FP32-NEXT: # +; MMR2-FP32-NEXT: # > ; MMR2-FP32-NEXT: jr $ra # > +; MMR2-FP32-NEXT: # > ; MMR2-FP32-NEXT: mfc1 $2, $f0 # -; MMR2-FP32-NEXT: # > +; MMR2-FP32-NEXT: # +; MMR2-FP32-NEXT: # > ; ; MMR2-FP64-LABEL: test1: ; MMR2-FP64: # %bb.0: # %entry ; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # -; MMR2-FP64-NEXT: # > +; MMR2-FP64-NEXT: # +; MMR2-FP64-NEXT: # > ; MMR2-FP64-NEXT: jr $ra # > +; MMR2-FP64-NEXT: # > ; MMR2-FP64-NEXT: mfc1 $2, $f0 # -; MMR2-FP64-NEXT: # > +; MMR2-FP64-NEXT: # +; MMR2-FP64-NEXT: # > ; ; MMR2-SF-LABEL: test1: ; MMR2-SF: # %bb.0: # %entry @@ -164,63 +164,63 @@ define i32 @test1(float %t) { ; MMR2-SF-NEXT: .cfi_def_cfa_offset 24 ; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; MMR2-SF-NEXT: # -; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: .cfi_offset 31, -4 ; MMR2-SF-NEXT: jal __fixsfsi # > ; MMR2-SF-NEXT: nop # -; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR2-SF-NEXT: # -; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: addiusp 24 # > ; MMR2-SF-NEXT: jrc $ra # > +; MMR2-SF-NEXT: # > ; ; MMR6-LABEL: test1: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: trunc.w.s $f0, $f12 # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: mfc1 $2, $f0 # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MMR6-SF-LABEL: test1: ; MMR6-SF: # %bb.0: # %entry ; MMR6-SF-NEXT: addiu $sp, $sp, -24 # -; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: .cfi_def_cfa_offset 24 ; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; MMR6-SF-NEXT: # -; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: .cfi_offset 31, -4 ; MMR6-SF-NEXT: balc __fixsfsi # > ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR6-SF-NEXT: # -; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: addiu $sp, $sp, 24 # -; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: jrc $ra # > +; MMR6-SF-NEXT: # > entry: %conv = fptosi float %t to i32 ret i32 %conv @@ -230,123 +230,123 @@ define i32 @test2(double %t) { ; M32-LABEL: test2: ; M32: # %bb.0: # %entry ; M32-NEXT: trunc.w.d $f0, $f12 # -; M32-NEXT: # > +; M32-NEXT: # +; M32-NEXT: # > ; M32-NEXT: jr $ra # > +; M32-NEXT: # > ; M32-NEXT: mfc1 $2, $f0 # -; M32-NEXT: # > +; M32-NEXT: # +; M32-NEXT: # > ; ; M32R2-FP64-LABEL: test2: ; M32R2-FP64: # %bb.0: # %entry ; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # -; M32R2-FP64-NEXT: # > +; M32R2-FP64-NEXT: # +; M32R2-FP64-NEXT: # > ; M32R2-FP64-NEXT: jr $ra # > +; M32R2-FP64-NEXT: # > ; M32R2-FP64-NEXT: mfc1 $2, $f0 # -; M32R2-FP64-NEXT: # > +; M32R2-FP64-NEXT: # +; M32R2-FP64-NEXT: # > ; ; M32R2-SF-LABEL: test2: ; M32R2-SF: # %bb.0: # %entry ; M32R2-SF-NEXT: addiu $sp, $sp, -24 # -; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: .cfi_def_cfa_offset 24 ; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; M32R2-SF-NEXT: # -; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: .cfi_offset 31, -4 ; M32R2-SF-NEXT: jal __fixdfsi # > ; M32R2-SF-NEXT: nop # -; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; M32R2-SF-NEXT: # -; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: jr $ra # > +; M32R2-SF-NEXT: # > ; M32R2-SF-NEXT: addiu $sp, $sp, 24 # -; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # ; M32R2-SF-NEXT: # > ; ; M32R3R5-LABEL: test2: ; M32R3R5: # %bb.0: # %entry ; M32R3R5-NEXT: trunc.w.d $f0, $f12 # -; M32R3R5-NEXT: # > +; M32R3R5-NEXT: # +; M32R3R5-NEXT: # > ; M32R3R5-NEXT: jr $ra # > +; M32R3R5-NEXT: # > ; M32R3R5-NEXT: mfc1 $2, $f0 # -; M32R3R5-NEXT: # > +; M32R3R5-NEXT: # +; M32R3R5-NEXT: # > ; ; M32R6-LABEL: test2: ; M32R6: # %bb.0: # %entry ; M32R6-NEXT: trunc.w.d $f0, $f12 # -; M32R6-NEXT: # > +; M32R6-NEXT: # +; M32R6-NEXT: # > ; M32R6-NEXT: jr $ra # -; M32R6-NEXT: # > +; M32R6-NEXT: # +; M32R6-NEXT: # > ; M32R6-NEXT: mfc1 $2, $f0 # -; M32R6-NEXT: # > +; M32R6-NEXT: # +; M32R6-NEXT: # > ; ; M64-LABEL: test2: ; M64: # %bb.0: # %entry ; M64-NEXT: trunc.w.d $f0, $f12 # -; M64-NEXT: # > +; M64-NEXT: # +; M64-NEXT: # > ; M64-NEXT: jr $ra # > +; M64-NEXT: # > ; M64-NEXT: mfc1 $2, $f0 # -; M64-NEXT: # > +; M64-NEXT: # +; M64-NEXT: # > ; ; M64R6-LABEL: test2: ; M64R6: # %bb.0: # %entry ; M64R6-NEXT: trunc.w.d $f0, $f12 # -; M64R6-NEXT: # > +; M64R6-NEXT: # +; M64R6-NEXT: # > ; M64R6-NEXT: jr $ra # -; M64R6-NEXT: # > +; M64R6-NEXT: # +; M64R6-NEXT: # > ; M64R6-NEXT: mfc1 $2, $f0 # -; M64R6-NEXT: # > +; M64R6-NEXT: # +; M64R6-NEXT: # > ; ; MMR2-FP32-LABEL: test2: ; MMR2-FP32: # %bb.0: # %entry ; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # -; MMR2-FP32-NEXT: # > +; MMR2-FP32-NEXT: # +; MMR2-FP32-NEXT: # > ; MMR2-FP32-NEXT: jr $ra # > +; MMR2-FP32-NEXT: # > ; MMR2-FP32-NEXT: mfc1 $2, $f0 # -; MMR2-FP32-NEXT: # > +; MMR2-FP32-NEXT: # +; MMR2-FP32-NEXT: # > ; ; MMR2-FP64-LABEL: test2: ; MMR2-FP64: # %bb.0: # %entry ; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # -; MMR2-FP64-NEXT: # > +; MMR2-FP64-NEXT: # +; MMR2-FP64-NEXT: # > ; MMR2-FP64-NEXT: jr $ra # > +; MMR2-FP64-NEXT: # > ; MMR2-FP64-NEXT: mfc1 $2, $f0 # -; MMR2-FP64-NEXT: # > +; MMR2-FP64-NEXT: # +; MMR2-FP64-NEXT: # > ; ; MMR2-SF-LABEL: test2: ; MMR2-SF: # %bb.0: # %entry @@ -355,63 +355,63 @@ define i32 @test2(double %t) { ; MMR2-SF-NEXT: .cfi_def_cfa_offset 24 ; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; MMR2-SF-NEXT: # -; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: .cfi_offset 31, -4 ; MMR2-SF-NEXT: jal __fixdfsi # > ; MMR2-SF-NEXT: nop # -; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR2-SF-NEXT: # -; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # ; MMR2-SF-NEXT: # > ; MMR2-SF-NEXT: addiusp 24 # > ; MMR2-SF-NEXT: jrc $ra # > +; MMR2-SF-NEXT: # > ; ; MMR6-LABEL: test2: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: trunc.w.d $f0, $f12 # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: mfc1 $2, $f0 # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MMR6-SF-LABEL: test2: ; MMR6-SF: # %bb.0: # %entry ; MMR6-SF-NEXT: addiu $sp, $sp, -24 # -; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: .cfi_def_cfa_offset 24 ; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; MMR6-SF-NEXT: # -; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: .cfi_offset 31, -4 ; MMR6-SF-NEXT: balc __fixdfsi # > ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR6-SF-NEXT: # -; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: addiu $sp, $sp, 24 # -; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: jrc $ra # > +; MMR6-SF-NEXT: # > entry: %conv = fptosi double %t to i32 ret i32 %conv diff --git a/llvm/test/CodeGen/Mips/llvm-ir/load.ll b/llvm/test/CodeGen/Mips/llvm-ir/load.ll index 4f29fd848aed5..f81e1a742e44c 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/load.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/load.ll @@ -26,160 +26,160 @@ define i8 @f1() { ; MIPS32-LABEL: f1: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lui $1, %hi(a) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: lbu $2, %lo(a)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; ; MMR3-LABEL: f1: ; MMR3: # %bb.0: # %entry ; MMR3-NEXT: lui $1, %hi(a) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: lbu $2, %lo(a)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f1: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: lui $1, %hi(a) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: lbu $2, %lo(a)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f1: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $1, %hi(a) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: lbu $2, %lo(a)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS3-LABEL: f1: ; MIPS3: # %bb.0: # %entry ; MIPS3-NEXT: lui $1, %highest(a) # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %higher(a) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %hi(a) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: # > ; MIPS3-NEXT: lbu $2, %lo(a)($1) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; ; MIPS64-LABEL: f1: ; MIPS64: # %bb.0: # %entry ; MIPS64-NEXT: lui $1, %highest(a) # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %higher(a) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %hi(a) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: # > ; MIPS64-NEXT: lbu $2, %lo(a)($1) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; ; MIPS64R6-LABEL: f1: ; MIPS64R6: # %bb.0: # %entry ; MIPS64R6-NEXT: lui $1, %highest(a) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: lbu $2, %lo(a)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f1: ; MMR5FP64: # %bb.0: # %entry ; MMR5FP64-NEXT: lui $1, %hi(a) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: lbu $2, %lo(a)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f1: ; MIPS32R5FP643: # %bb.0: # %entry ; MIPS32R5FP643-NEXT: lui $1, %hi(a) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: lbu $2, %lo(a)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > entry: %0 = load i8, ptr @a ret i8 %0 @@ -189,160 +189,160 @@ define i32 @f2() { ; MIPS32-LABEL: f2: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lui $1, %hi(a) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: lb $2, %lo(a)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; ; MMR3-LABEL: f2: ; MMR3: # %bb.0: # %entry ; MMR3-NEXT: lui $1, %hi(a) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: lb $2, %lo(a)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f2: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: lui $1, %hi(a) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: lb $2, %lo(a)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f2: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $1, %hi(a) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: lb $2, %lo(a)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS3-LABEL: f2: ; MIPS3: # %bb.0: # %entry ; MIPS3-NEXT: lui $1, %highest(a) # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %higher(a) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %hi(a) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: # > ; MIPS3-NEXT: lb $2, %lo(a)($1) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; ; MIPS64-LABEL: f2: ; MIPS64: # %bb.0: # %entry ; MIPS64-NEXT: lui $1, %highest(a) # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %higher(a) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %hi(a) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: # > ; MIPS64-NEXT: lb $2, %lo(a)($1) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; ; MIPS64R6-LABEL: f2: ; MIPS64R6: # %bb.0: # %entry ; MIPS64R6-NEXT: lui $1, %highest(a) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: lb $2, %lo(a)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f2: ; MMR5FP64: # %bb.0: # %entry ; MMR5FP64-NEXT: lui $1, %hi(a) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: lb $2, %lo(a)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f2: ; MIPS32R5FP643: # %bb.0: # %entry ; MIPS32R5FP643-NEXT: lui $1, %hi(a) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: lb $2, %lo(a)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > entry: %0 = load i8, ptr @a %1 = sext i8 %0 to i32 @@ -353,160 +353,160 @@ define i16 @f3() { ; MIPS32-LABEL: f3: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lui $1, %hi(b) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: lhu $2, %lo(b)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; ; MMR3-LABEL: f3: ; MMR3: # %bb.0: # %entry ; MMR3-NEXT: lui $1, %hi(b) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: lhu $2, %lo(b)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f3: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: lui $1, %hi(b) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: lhu $2, %lo(b)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f3: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $1, %hi(b) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: lhu $2, %lo(b)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS3-LABEL: f3: ; MIPS3: # %bb.0: # %entry ; MIPS3-NEXT: lui $1, %highest(b) # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %higher(b) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %hi(b) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: # > ; MIPS3-NEXT: lhu $2, %lo(b)($1) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; ; MIPS64-LABEL: f3: ; MIPS64: # %bb.0: # %entry ; MIPS64-NEXT: lui $1, %highest(b) # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %higher(b) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %hi(b) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: # > ; MIPS64-NEXT: lhu $2, %lo(b)($1) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; ; MIPS64R6-LABEL: f3: ; MIPS64R6: # %bb.0: # %entry ; MIPS64R6-NEXT: lui $1, %highest(b) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: lhu $2, %lo(b)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f3: ; MMR5FP64: # %bb.0: # %entry ; MMR5FP64-NEXT: lui $1, %hi(b) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: lhu $2, %lo(b)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f3: ; MIPS32R5FP643: # %bb.0: # %entry ; MIPS32R5FP643-NEXT: lui $1, %hi(b) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: lhu $2, %lo(b)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > entry: %0 = load i16, ptr @b ret i16 %0 @@ -516,160 +516,160 @@ define i32 @f4() { ; MIPS32-LABEL: f4: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lui $1, %hi(b) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: lh $2, %lo(b)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; ; MMR3-LABEL: f4: ; MMR3: # %bb.0: # %entry ; MMR3-NEXT: lui $1, %hi(b) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: lh $2, %lo(b)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f4: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: lui $1, %hi(b) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: lh $2, %lo(b)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f4: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $1, %hi(b) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: lh $2, %lo(b)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS3-LABEL: f4: ; MIPS3: # %bb.0: # %entry ; MIPS3-NEXT: lui $1, %highest(b) # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %higher(b) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %hi(b) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: # > ; MIPS3-NEXT: lh $2, %lo(b)($1) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; ; MIPS64-LABEL: f4: ; MIPS64: # %bb.0: # %entry ; MIPS64-NEXT: lui $1, %highest(b) # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %higher(b) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %hi(b) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: # > ; MIPS64-NEXT: lh $2, %lo(b)($1) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; ; MIPS64R6-LABEL: f4: ; MIPS64R6: # %bb.0: # %entry ; MIPS64R6-NEXT: lui $1, %highest(b) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: lh $2, %lo(b)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f4: ; MMR5FP64: # %bb.0: # %entry ; MMR5FP64-NEXT: lui $1, %hi(b) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: lh $2, %lo(b)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f4: ; MIPS32R5FP643: # %bb.0: # %entry ; MIPS32R5FP643-NEXT: lui $1, %hi(b) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: lh $2, %lo(b)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > entry: %0 = load i16, ptr @b %1 = sext i16 %0 to i32 @@ -680,160 +680,160 @@ define i32 @f5() { ; MIPS32-LABEL: f5: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lui $1, %hi(c) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: lw $2, %lo(c)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; ; MMR3-LABEL: f5: ; MMR3: # %bb.0: # %entry ; MMR3-NEXT: lui $1, %hi(c) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: lw $2, %lo(c)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f5: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: lui $1, %hi(c) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: lw $2, %lo(c)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f5: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $1, %hi(c) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: lw $2, %lo(c)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS3-LABEL: f5: ; MIPS3: # %bb.0: # %entry ; MIPS3-NEXT: lui $1, %highest(c) # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %higher(c) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %hi(c) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: # > ; MIPS3-NEXT: lw $2, %lo(c)($1) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; ; MIPS64-LABEL: f5: ; MIPS64: # %bb.0: # %entry ; MIPS64-NEXT: lui $1, %highest(c) # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %higher(c) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %hi(c) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: # > ; MIPS64-NEXT: lw $2, %lo(c)($1) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; ; MIPS64R6-LABEL: f5: ; MIPS64R6: # %bb.0: # %entry ; MIPS64R6-NEXT: lui $1, %highest(c) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: lw $2, %lo(c)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f5: ; MMR5FP64: # %bb.0: # %entry ; MMR5FP64-NEXT: lui $1, %hi(c) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: lw $2, %lo(c)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f5: ; MIPS32R5FP643: # %bb.0: # %entry ; MIPS32R5FP643-NEXT: lui $1, %hi(c) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: lw $2, %lo(c)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > entry: %0 = load i32, ptr @c ret i32 %0 @@ -843,180 +843,180 @@ define i64 @f6() { ; MIPS32-LABEL: f6: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lui $1, %hi(c) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: lw $3, %lo(c)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: addiu $2, $zero, 0 # -; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # ; MIPS32-NEXT: # > ; ; MMR3-LABEL: f6: ; MMR3: # %bb.0: # %entry ; MMR3-NEXT: lui $1, %hi(c) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: li16 $2, 0 # +; MMR3-NEXT: # ; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: lw $3, %lo(c)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f6: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: lui $1, %hi(c) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: lw $3, %lo(c)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: addiu $2, $zero, 0 # -; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # ; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f6: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $1, %hi(c) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: lw $3, %lo(c)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: li16 $2, 0 # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS3-LABEL: f6: ; MIPS3: # %bb.0: # %entry ; MIPS3-NEXT: lui $1, %highest(c) # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %higher(c) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %hi(c) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: # > ; MIPS3-NEXT: lwu $2, %lo(c)($1) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; ; MIPS64-LABEL: f6: ; MIPS64: # %bb.0: # %entry ; MIPS64-NEXT: lui $1, %highest(c) # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %higher(c) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %hi(c) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: # > ; MIPS64-NEXT: lwu $2, %lo(c)($1) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; ; MIPS64R6-LABEL: f6: ; MIPS64R6: # %bb.0: # %entry ; MIPS64R6-NEXT: lui $1, %highest(c) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: lwu $2, %lo(c)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f6: ; MMR5FP64: # %bb.0: # %entry ; MMR5FP64-NEXT: lui $1, %hi(c) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: li16 $2, 0 # +; MMR5FP64-NEXT: # ; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: lw $3, %lo(c)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f6: ; MIPS32R5FP643: # %bb.0: # %entry ; MIPS32R5FP643-NEXT: lui $1, %hi(c) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: addiu $2, $zero, 0 # -; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # ; MIPS32R5FP643-NEXT: # > entry: %0 = load i32, ptr @c @@ -1028,183 +1028,183 @@ define i64 @f7() { ; MIPS32-LABEL: f7: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lui $1, %hi(c) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: lw $3, %lo(c)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: sra $2, $3, 31 # -; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # ; MIPS32-NEXT: # > ; ; MMR3-LABEL: f7: ; MMR3: # %bb.0: # %entry ; MMR3-NEXT: lui $1, %hi(c) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: lw $3, %lo(c)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: sra $2, $3, 31 # -; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # ; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f7: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: lui $1, %hi(c) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: lw $3, %lo(c)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: sra $2, $3, 31 # -; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # ; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f7: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $1, %hi(c) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: lw $3, %lo(c)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sra $2, $3, 31 # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS3-LABEL: f7: ; MIPS3: # %bb.0: # %entry ; MIPS3-NEXT: lui $1, %highest(c) # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %higher(c) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %hi(c) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: # > ; MIPS3-NEXT: lw $2, %lo(c)($1) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; ; MIPS64-LABEL: f7: ; MIPS64: # %bb.0: # %entry ; MIPS64-NEXT: lui $1, %highest(c) # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %higher(c) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %hi(c) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: # > ; MIPS64-NEXT: lw $2, %lo(c)($1) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; ; MIPS64R6-LABEL: f7: ; MIPS64R6: # %bb.0: # %entry ; MIPS64R6-NEXT: lui $1, %highest(c) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: lw $2, %lo(c)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f7: ; MMR5FP64: # %bb.0: # %entry ; MMR5FP64-NEXT: lui $1, %hi(c) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: lw $3, %lo(c)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: sra $2, $3, 31 # -; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # ; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f7: ; MIPS32R5FP643: # %bb.0: # %entry ; MIPS32R5FP643-NEXT: lui $1, %hi(c) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: sra $2, $3, 31 # -; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # ; MIPS32R5FP643-NEXT: # > entry: %0 = load i32, ptr @c @@ -1216,160 +1216,160 @@ define float @f8() { ; MIPS32-LABEL: f8: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lui $1, %hi(e) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: lwc1 $f0, %lo(e)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; ; MMR3-LABEL: f8: ; MMR3: # %bb.0: # %entry ; MMR3-NEXT: lui $1, %hi(e) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: lwc1 $f0, %lo(e)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f8: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: lui $1, %hi(e) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: lwc1 $f0, %lo(e)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f8: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $1, %hi(e) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: lwc1 $f0, %lo(e)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS3-LABEL: f8: ; MIPS3: # %bb.0: # %entry ; MIPS3-NEXT: lui $1, %highest(e) # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %higher(e) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %hi(e) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: # > ; MIPS3-NEXT: lwc1 $f0, %lo(e)($1) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; ; MIPS64-LABEL: f8: ; MIPS64: # %bb.0: # %entry ; MIPS64-NEXT: lui $1, %highest(e) # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %higher(e) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %hi(e) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: # > ; MIPS64-NEXT: lwc1 $f0, %lo(e)($1) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; ; MIPS64R6-LABEL: f8: ; MIPS64R6: # %bb.0: # %entry ; MIPS64R6-NEXT: lui $1, %highest(e) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(e) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(e) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: lwc1 $f0, %lo(e)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f8: ; MMR5FP64: # %bb.0: # %entry ; MMR5FP64-NEXT: lui $1, %hi(e) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: lwc1 $f0, %lo(e)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f8: ; MIPS32R5FP643: # %bb.0: # %entry ; MIPS32R5FP643-NEXT: lui $1, %hi(e) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: lwc1 $f0, %lo(e)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > entry: %0 = load float, ptr @e ret float %0 @@ -1379,160 +1379,160 @@ define double @f9() { ; MIPS32-LABEL: f9: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: lui $1, %hi(f) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: ldc1 $f0, %lo(f)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; ; MMR3-LABEL: f9: ; MMR3: # %bb.0: # %entry ; MMR3-NEXT: lui $1, %hi(f) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: ldc1 $f0, %lo(f)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f9: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: lui $1, %hi(f) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: ldc1 $f0, %lo(f)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f9: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $1, %hi(f) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: ldc1 $f0, %lo(f)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS3-LABEL: f9: ; MIPS3: # %bb.0: # %entry ; MIPS3-NEXT: lui $1, %highest(f) # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %higher(f) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: daddiu $1, $1, %hi(f) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; MIPS3-NEXT: dsll $1, $1, 16 # -; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # ; MIPS3-NEXT: # > ; MIPS3-NEXT: jr $ra # > +; MIPS3-NEXT: # > ; MIPS3-NEXT: ldc1 $f0, %lo(f)($1) # -; MIPS3-NEXT: # -; MIPS3-NEXT: # > +; MIPS3-NEXT: # +; MIPS3-NEXT: # +; MIPS3-NEXT: # > ; ; MIPS64-LABEL: f9: ; MIPS64: # %bb.0: # %entry ; MIPS64-NEXT: lui $1, %highest(f) # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %higher(f) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: daddiu $1, $1, %hi(f) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; MIPS64-NEXT: dsll $1, $1, 16 # -; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # ; MIPS64-NEXT: # > ; MIPS64-NEXT: jr $ra # > +; MIPS64-NEXT: # > ; MIPS64-NEXT: ldc1 $f0, %lo(f)($1) # -; MIPS64-NEXT: # -; MIPS64-NEXT: # > +; MIPS64-NEXT: # +; MIPS64-NEXT: # +; MIPS64-NEXT: # > ; ; MIPS64R6-LABEL: f9: ; MIPS64R6: # %bb.0: # %entry ; MIPS64R6-NEXT: lui $1, %highest(f) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(f) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(f) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: ldc1 $f0, %lo(f)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f9: ; MMR5FP64: # %bb.0: # %entry ; MMR5FP64-NEXT: lui $1, %hi(f) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: ldc1 $f0, %lo(f)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f9: ; MIPS32R5FP643: # %bb.0: # %entry ; MIPS32R5FP643-NEXT: lui $1, %hi(f) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: ldc1 $f0, %lo(f)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > entry: %0 = load double, ptr @f ret double %0 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/store.ll b/llvm/test/CodeGen/Mips/llvm-ir/store.ll index 8b51c0939b8d4..bd3bb5099c733 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/store.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/store.ll @@ -25,132 +25,132 @@ define void @f1(i8 %a) { ; MIPS32-LABEL: f1: ; MIPS32: # %bb.0: ; MIPS32-NEXT: lui $1, %hi(a) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: sb $4, %lo(a)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; ; MMR3-LABEL: f1: ; MMR3: # %bb.0: ; MMR3-NEXT: lui $1, %hi(a) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: sb $4, %lo(a)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f1: ; MIPS32R6: # %bb.0: ; MIPS32R6-NEXT: lui $1, %hi(a) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: sb $4, %lo(a)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f1: ; MMR6: # %bb.0: ; MMR6-NEXT: lui $1, %hi(a) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sb $4, %lo(a)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS4-LABEL: f1: ; MIPS4: # %bb.0: ; MIPS4-NEXT: lui $1, %highest(a) # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: daddiu $1, $1, %higher(a) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: dsll $1, $1, 16 # -; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # ; MIPS4-NEXT: # > ; MIPS4-NEXT: daddiu $1, $1, %hi(a) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: dsll $1, $1, 16 # -; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # ; MIPS4-NEXT: # > ; MIPS4-NEXT: jr $ra # > +; MIPS4-NEXT: # > ; MIPS4-NEXT: sb $4, %lo(a)($1) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; ; MIPS64R6-LABEL: f1: ; MIPS64R6: # %bb.0: ; MIPS64R6-NEXT: lui $1, %highest(a) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: sb $4, %lo(a)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f1: ; MMR5FP64: # %bb.0: ; MMR5FP64-NEXT: lui $1, %hi(a) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: sb $4, %lo(a)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f1: ; MIPS32R5FP643: # %bb.0: ; MIPS32R5FP643-NEXT: lui $1, %hi(a) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: sb $4, %lo(a)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > store i8 %a, ptr @a ret void } @@ -159,132 +159,132 @@ define void @f2(i16 %a) { ; MIPS32-LABEL: f2: ; MIPS32: # %bb.0: ; MIPS32-NEXT: lui $1, %hi(b) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: sh $4, %lo(b)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; ; MMR3-LABEL: f2: ; MMR3: # %bb.0: ; MMR3-NEXT: lui $1, %hi(b) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: sh $4, %lo(b)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f2: ; MIPS32R6: # %bb.0: ; MIPS32R6-NEXT: lui $1, %hi(b) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: sh $4, %lo(b)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f2: ; MMR6: # %bb.0: ; MMR6-NEXT: lui $1, %hi(b) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sh $4, %lo(b)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS4-LABEL: f2: ; MIPS4: # %bb.0: ; MIPS4-NEXT: lui $1, %highest(b) # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: daddiu $1, $1, %higher(b) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: dsll $1, $1, 16 # -; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # ; MIPS4-NEXT: # > ; MIPS4-NEXT: daddiu $1, $1, %hi(b) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: dsll $1, $1, 16 # -; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # ; MIPS4-NEXT: # > ; MIPS4-NEXT: jr $ra # > +; MIPS4-NEXT: # > ; MIPS4-NEXT: sh $4, %lo(b)($1) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; ; MIPS64R6-LABEL: f2: ; MIPS64R6: # %bb.0: ; MIPS64R6-NEXT: lui $1, %highest(b) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: sh $4, %lo(b)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f2: ; MMR5FP64: # %bb.0: ; MMR5FP64-NEXT: lui $1, %hi(b) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: sh $4, %lo(b)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f2: ; MIPS32R5FP643: # %bb.0: ; MIPS32R5FP643-NEXT: lui $1, %hi(b) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: sh $4, %lo(b)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > store i16 %a, ptr @b ret void } @@ -293,132 +293,132 @@ define void @f3(i32 %a) { ; MIPS32-LABEL: f3: ; MIPS32: # %bb.0: ; MIPS32-NEXT: lui $1, %hi(c) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: sw $4, %lo(c)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; ; MMR3-LABEL: f3: ; MMR3: # %bb.0: ; MMR3-NEXT: lui $1, %hi(c) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: sw $4, %lo(c)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f3: ; MIPS32R6: # %bb.0: ; MIPS32R6-NEXT: lui $1, %hi(c) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: sw $4, %lo(c)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f3: ; MMR6: # %bb.0: ; MMR6-NEXT: lui $1, %hi(c) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sw $4, %lo(c)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS4-LABEL: f3: ; MIPS4: # %bb.0: ; MIPS4-NEXT: lui $1, %highest(c) # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: daddiu $1, $1, %higher(c) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: dsll $1, $1, 16 # -; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # ; MIPS4-NEXT: # > ; MIPS4-NEXT: daddiu $1, $1, %hi(c) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: dsll $1, $1, 16 # -; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # ; MIPS4-NEXT: # > ; MIPS4-NEXT: jr $ra # > +; MIPS4-NEXT: # > ; MIPS4-NEXT: sw $4, %lo(c)($1) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; ; MIPS64R6-LABEL: f3: ; MIPS64R6: # %bb.0: ; MIPS64R6-NEXT: lui $1, %highest(c) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: sw $4, %lo(c)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f3: ; MMR5FP64: # %bb.0: ; MMR5FP64-NEXT: lui $1, %hi(c) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: sw $4, %lo(c)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f3: ; MIPS32R5FP643: # %bb.0: ; MIPS32R5FP643-NEXT: lui $1, %hi(c) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: sw $4, %lo(c)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > store i32 %a, ptr @c ret void } @@ -427,179 +427,179 @@ define void @f4(i64 %a) { ; MIPS32-LABEL: f4: ; MIPS32: # %bb.0: ; MIPS32-NEXT: lui $1, %hi(d) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: sw $4, %lo(d)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: addiu $1, $1, %lo(d) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: sw $5, 4($1) # -; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # ; MIPS32-NEXT: # > ; ; MMR3-LABEL: f4: ; MMR3: # %bb.0: ; MMR3-NEXT: lui $1, %hi(d) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: sw $4, %lo(d)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: addiu $2, $1, %lo(d) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: sw16 $5, 4($2) # -; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # ; MMR3-NEXT: # > ; MMR3-NEXT: jrc $ra # > +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f4: ; MIPS32R6: # %bb.0: ; MIPS32R6-NEXT: lui $1, %hi(d) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: sw $4, %lo(d)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: addiu $1, $1, %lo(d) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: sw $5, 4($1) # -; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # ; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f4: ; MMR6: # %bb.0: ; MMR6-NEXT: lui $1, %hi(d) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sw $4, %lo(d)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addiu $2, $1, %lo(d) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sw16 $5, 4($2) # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS4-LABEL: f4: ; MIPS4: # %bb.0: ; MIPS4-NEXT: lui $1, %highest(d) # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: daddiu $1, $1, %higher(d) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: dsll $1, $1, 16 # -; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # ; MIPS4-NEXT: # > ; MIPS4-NEXT: daddiu $1, $1, %hi(d) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: dsll $1, $1, 16 # -; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # ; MIPS4-NEXT: # > ; MIPS4-NEXT: jr $ra # > +; MIPS4-NEXT: # > ; MIPS4-NEXT: sd $4, %lo(d)($1) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; ; MIPS64R6-LABEL: f4: ; MIPS64R6: # %bb.0: ; MIPS64R6-NEXT: lui $1, %highest(d) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(d) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(d) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: sd $4, %lo(d)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f4: ; MMR5FP64: # %bb.0: ; MMR5FP64-NEXT: lui $1, %hi(d) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: sw $4, %lo(d)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: addiu $2, $1, %lo(d) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: sw16 $5, 4($2) # -; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # ; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jrc $ra # > +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f4: ; MIPS32R5FP643: # %bb.0: ; MIPS32R5FP643-NEXT: lui $1, %hi(d) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: sw $4, %lo(d)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: addiu $1, $1, %lo(d) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: sw $5, 4($1) # -; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # ; MIPS32R5FP643-NEXT: # > store i64 %a, ptr @d ret void @@ -609,132 +609,132 @@ define void @f5(float %e) { ; MIPS32-LABEL: f5: ; MIPS32: # %bb.0: ; MIPS32-NEXT: lui $1, %hi(e) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: swc1 $f12, %lo(e)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; ; MMR3-LABEL: f5: ; MMR3: # %bb.0: ; MMR3-NEXT: lui $1, %hi(e) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: swc1 $f12, %lo(e)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f5: ; MIPS32R6: # %bb.0: ; MIPS32R6-NEXT: lui $1, %hi(e) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: swc1 $f12, %lo(e)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f5: ; MMR6: # %bb.0: ; MMR6-NEXT: lui $1, %hi(e) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: swc1 $f12, %lo(e)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS4-LABEL: f5: ; MIPS4: # %bb.0: ; MIPS4-NEXT: lui $1, %highest(e) # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: daddiu $1, $1, %higher(e) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: dsll $1, $1, 16 # -; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # ; MIPS4-NEXT: # > ; MIPS4-NEXT: daddiu $1, $1, %hi(e) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: dsll $1, $1, 16 # -; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # ; MIPS4-NEXT: # > ; MIPS4-NEXT: jr $ra # > +; MIPS4-NEXT: # > ; MIPS4-NEXT: swc1 $f12, %lo(e)($1) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; ; MIPS64R6-LABEL: f5: ; MIPS64R6: # %bb.0: ; MIPS64R6-NEXT: lui $1, %highest(e) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(e) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(e) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: swc1 $f12, %lo(e)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f5: ; MMR5FP64: # %bb.0: ; MMR5FP64-NEXT: lui $1, %hi(e) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: swc1 $f12, %lo(e)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f5: ; MIPS32R5FP643: # %bb.0: ; MIPS32R5FP643-NEXT: lui $1, %hi(e) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: swc1 $f12, %lo(e)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > store float %e, ptr @e ret void } @@ -743,132 +743,132 @@ define void @f6(double %f) { ; MIPS32-LABEL: f6: ; MIPS32: # %bb.0: ; MIPS32-NEXT: lui $1, %hi(f) # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; MIPS32-NEXT: jr $ra # > +; MIPS32-NEXT: # > ; MIPS32-NEXT: sdc1 $f12, %lo(f)($1) # -; MIPS32-NEXT: # -; MIPS32-NEXT: # > +; MIPS32-NEXT: # +; MIPS32-NEXT: # +; MIPS32-NEXT: # > ; ; MMR3-LABEL: f6: ; MMR3: # %bb.0: ; MMR3-NEXT: lui $1, %hi(f) # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # > ; MMR3-NEXT: jr $ra # > +; MMR3-NEXT: # > ; MMR3-NEXT: sdc1 $f12, %lo(f)($1) # -; MMR3-NEXT: # -; MMR3-NEXT: # > +; MMR3-NEXT: # +; MMR3-NEXT: # +; MMR3-NEXT: # > ; ; MIPS32R6-LABEL: f6: ; MIPS32R6: # %bb.0: ; MIPS32R6-NEXT: lui $1, %hi(f) # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: jr $ra # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; MIPS32R6-NEXT: sdc1 $f12, %lo(f)($1) # -; MIPS32R6-NEXT: # -; MIPS32R6-NEXT: # > +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # +; MIPS32R6-NEXT: # > ; ; MMR6-LABEL: f6: ; MMR6: # %bb.0: ; MMR6-NEXT: lui $1, %hi(f) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sdc1 $f12, %lo(f)($1) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > ; ; MIPS4-LABEL: f6: ; MIPS4: # %bb.0: ; MIPS4-NEXT: lui $1, %highest(f) # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: daddiu $1, $1, %higher(f) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: dsll $1, $1, 16 # -; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # ; MIPS4-NEXT: # > ; MIPS4-NEXT: daddiu $1, $1, %hi(f) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; MIPS4-NEXT: dsll $1, $1, 16 # -; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # ; MIPS4-NEXT: # > ; MIPS4-NEXT: jr $ra # > +; MIPS4-NEXT: # > ; MIPS4-NEXT: sdc1 $f12, %lo(f)($1) # -; MIPS4-NEXT: # -; MIPS4-NEXT: # > +; MIPS4-NEXT: # +; MIPS4-NEXT: # +; MIPS4-NEXT: # > ; ; MIPS64R6-LABEL: f6: ; MIPS64R6: # %bb.0: ; MIPS64R6-NEXT: lui $1, %highest(f) # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %higher(f) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: daddiu $1, $1, %hi(f) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: dsll $1, $1, 16 # -; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # ; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: jr $ra # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; MIPS64R6-NEXT: sdc1 $f12, %lo(f)($1) # -; MIPS64R6-NEXT: # -; MIPS64R6-NEXT: # > +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # +; MIPS64R6-NEXT: # > ; ; MMR5FP64-LABEL: f6: ; MMR5FP64: # %bb.0: ; MMR5FP64-NEXT: lui $1, %hi(f) # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: jr $ra # > +; MMR5FP64-NEXT: # > ; MMR5FP64-NEXT: sdc1 $f12, %lo(f)($1) # -; MMR5FP64-NEXT: # -; MMR5FP64-NEXT: # > +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # +; MMR5FP64-NEXT: # > ; ; MIPS32R5FP643-LABEL: f6: ; MIPS32R5FP643: # %bb.0: ; MIPS32R5FP643-NEXT: lui $1, %hi(f) # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: jr $ra # > +; MIPS32R5FP643-NEXT: # > ; MIPS32R5FP643-NEXT: sdc1 $f12, %lo(f)($1) # -; MIPS32R5FP643-NEXT: # -; MIPS32R5FP643-NEXT: # > +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # +; MIPS32R5FP643-NEXT: # > store double %f, ptr @f ret void } diff --git a/llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll b/llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll index faf37e8a020e3..3519f019dd554 100644 --- a/llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll +++ b/llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll @@ -7,53 +7,53 @@ define i64 @test(i32 signext %a, i32 signext %b) { ; MMR2-LABEL: test: ; MMR2: # %bb.0: # %entry -; MMR2-NEXT: li16 $2, 0 # +; MMR2-NEXT: li16 $2, 0 # ; MMR2-NEXT: # > -; MMR2-NEXT: li16 $3, 1 # +; MMR2-NEXT: li16 $3, 1 # ; MMR2-NEXT: # > -; MMR2-NEXT: mtlo $3 # > -; MMR2-NEXT: mthi $2 # > -; MMR2-NEXT: madd $4, $5 # -; MMR2-NEXT: # > -; MMR2-NEXT: mflo16 $2 # > -; MMR2-NEXT: mfhi16 $3 # > -; MMR2-NEXT: jrc $ra # > +; MMR2-NEXT: mtlo $3 # > +; MMR2-NEXT: mthi $2 # > +; MMR2-NEXT: madd $4, $5 # +; MMR2-NEXT: # > +; MMR2-NEXT: mflo16 $2 # > +; MMR2-NEXT: mfhi16 $3 # > +; MMR2-NEXT: jrc $ra # > ; ; MMR2-DSP-LABEL: test: ; MMR2-DSP: # %bb.0: # %entry -; MMR2-DSP-NEXT: li16 $2, 0 # +; MMR2-DSP-NEXT: li16 $2, 0 # ; MMR2-DSP-NEXT: # > -; MMR2-DSP-NEXT: li16 $3, 1 # +; MMR2-DSP-NEXT: li16 $3, 1 # ; MMR2-DSP-NEXT: # > -; MMR2-DSP-NEXT: mtlo $3, $ac0 # -; MMR2-DSP-NEXT: # > -; MMR2-DSP-NEXT: mthi $2, $ac0 # -; MMR2-DSP-NEXT: # > -; MMR2-DSP-NEXT: madd $ac0, $4, $5 # -; MMR2-DSP-NEXT: # -; MMR2-DSP-NEXT: # -; MMR2-DSP-NEXT: # > -; MMR2-DSP-NEXT: mflo $2, $ac0 # -; MMR2-DSP-NEXT: # > -; MMR2-DSP-NEXT: jr $ra # > -; MMR2-DSP-NEXT: mfhi $3, $ac0 # -; MMR2-DSP-NEXT: # > +; MMR2-DSP-NEXT: mtlo $3, $ac0 # +; MMR2-DSP-NEXT: # > +; MMR2-DSP-NEXT: mthi $2, $ac0 # +; MMR2-DSP-NEXT: # > +; MMR2-DSP-NEXT: madd $ac0, $4, $5 # +; MMR2-DSP-NEXT: # +; MMR2-DSP-NEXT: # +; MMR2-DSP-NEXT: # > +; MMR2-DSP-NEXT: mflo $2, $ac0 # +; MMR2-DSP-NEXT: # > +; MMR2-DSP-NEXT: jr $ra # > +; MMR2-DSP-NEXT: mfhi $3, $ac0 # +; MMR2-DSP-NEXT: # > entry: %conv = sext i32 %a to i64 %conv1 = sext i32 %b to i64 diff --git a/llvm/test/CodeGen/Mips/setcc-se.ll b/llvm/test/CodeGen/Mips/setcc-se.ll index c1054607d5e91..00358135c42be 100644 --- a/llvm/test/CodeGen/Mips/setcc-se.ll +++ b/llvm/test/CodeGen/Mips/setcc-se.ll @@ -13,11 +13,11 @@ define i32 @seteq0(i32 %a) { ; MMR6-LABEL: seteq0: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: sltiu $2, $4, 1 # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > entry: %cmp = icmp eq i32 %a, 0 %conv = zext i1 %cmp to i32 @@ -33,11 +33,11 @@ define i32 @setne0(i32 %a) { ; MMR6-LABEL: setne0: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: sltu $2, $zero, $4 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > entry: %cmp = icmp ne i32 %a, 0 %conv = zext i1 %cmp to i32 @@ -60,35 +60,35 @@ define void @slti_beq0(i32 %a) { ; MMR6-LABEL: slti_beq0: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $2, %hi(_gp_disp) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addu $2, $2, $25 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: slti $1, $4, -32768 # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: beqzc $1, $BB2_2 # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: # %bb.1: # %if.then ; MMR6-NEXT: lw $2, %got(g1)($2) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sw16 $4, 0($2) # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: $BB2_2: # %if.end ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > entry: %cmp = icmp slt i32 %a, -32768 br i1 %cmp, label %if.then, label %if.end @@ -119,42 +119,42 @@ define void @slti_beq1(i32 %a) { ; MMR6-LABEL: slti_beq1: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $2, %hi(_gp_disp) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addu $2, $2, $25 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: lui $1, 65535 # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: ori $1, $1, 32766 # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: slt $1, $1, $4 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: bnezc $1, $BB3_2 # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: # %bb.1: # %if.then ; MMR6-NEXT: lw $2, %got(g1)($2) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sw16 $4, 0($2) # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: $BB3_2: # %if.end ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > entry: %cmp = icmp slt i32 %a, -32769 br i1 %cmp, label %if.then, label %if.end @@ -183,35 +183,35 @@ define void @slti_beq2(i32 %a) { ; MMR6-LABEL: slti_beq2: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $2, %hi(_gp_disp) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addu $2, $2, $25 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: slti $1, $4, 32767 # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: beqzc $1, $BB4_2 # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: # %bb.1: # %if.then ; MMR6-NEXT: lw $2, %got(g1)($2) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sw16 $4, 0($2) # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: $BB4_2: # %if.end ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > entry: %cmp = icmp slt i32 %a, 32767 br i1 %cmp, label %if.then, label %if.end @@ -241,39 +241,39 @@ define void @slti_beq3(i32 %a) { ; MMR6-LABEL: slti_beq3: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $2, %hi(_gp_disp) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addu $2, $2, $25 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addiu $1, $zero, 32767 # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: slt $1, $1, $4 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: bnezc $1, $BB5_2 # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: # %bb.1: # %if.then ; MMR6-NEXT: lw $2, %got(g1)($2) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sw16 $4, 0($2) # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: $BB5_2: # %if.end ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > entry: %cmp = icmp slt i32 %a, 32768 br i1 %cmp, label %if.then, label %if.end @@ -302,35 +302,35 @@ define void @sltiu_beq0(i32 %a) { ; MMR6-LABEL: sltiu_beq0: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $2, %hi(_gp_disp) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addu $2, $2, $25 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sltiu $1, $4, 32767 # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: beqzc $1, $BB6_2 # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: # %bb.1: # %if.then ; MMR6-NEXT: lw $2, %got(g1)($2) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sw16 $4, 0($2) # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: $BB6_2: # %if.end ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > entry: %cmp = icmp ult i32 %a, 32767 br i1 %cmp, label %if.then, label %if.end @@ -360,39 +360,39 @@ define void @sltiu_beq1(i32 %a) { ; MMR6-LABEL: sltiu_beq1: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $2, %hi(_gp_disp) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addu $2, $2, $25 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addiu $1, $zero, 32767 # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: sltu $1, $1, $4 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: bnezc $1, $BB7_2 # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: # %bb.1: # %if.then ; MMR6-NEXT: lw $2, %got(g1)($2) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sw16 $4, 0($2) # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: $BB7_2: # %if.end ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > entry: %cmp = icmp ult i32 %a, 32768 br i1 %cmp, label %if.then, label %if.end @@ -421,35 +421,35 @@ define void @sltiu_beq2(i32 %a) { ; MMR6-LABEL: sltiu_beq2: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $2, %hi(_gp_disp) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addu $2, $2, $25 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sltiu $1, $4, -32768 # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: beqzc $1, $BB8_2 # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: # %bb.1: # %if.then ; MMR6-NEXT: lw $2, %got(g1)($2) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sw16 $4, 0($2) # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: $BB8_2: # %if.end ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > entry: %cmp = icmp ult i32 %a, -32768 br i1 %cmp, label %if.then, label %if.end @@ -480,42 +480,42 @@ define void @sltiu_beq3(i32 %a) { ; MMR6-LABEL: sltiu_beq3: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: lui $2, %hi(_gp_disp) # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: addu $2, $2, $25 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: lui $1, 65535 # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: ori $1, $1, 32766 # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: sltu $1, $1, $4 # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: bnezc $1, $BB9_2 # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: # %bb.1: # %if.then ; MMR6-NEXT: lw $2, %got(g1)($2) # -; MMR6-NEXT: # -; MMR6-NEXT: # > +; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # > ; MMR6-NEXT: sw16 $4, 0($2) # -; MMR6-NEXT: # +; MMR6-NEXT: # +; MMR6-NEXT: # ; MMR6-NEXT: # > ; MMR6-NEXT: $BB9_2: # %if.end ; MMR6-NEXT: jrc $ra # > +; MMR6-NEXT: # > entry: %cmp = icmp ult i32 %a, -32769 br i1 %cmp, label %if.then, label %if.end diff --git a/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s b/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s index 4542027b0df90..bf5a30e0f209e 100644 --- a/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s +++ b/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s @@ -3,18 +3,18 @@ // CHECK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" buffer_load_dwordx4 v[0:3], v0, s[0:3], 0, offen offset:4092 slc // CHECK: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4092 slc ; -// CHECK-NEXT: ; -// CHECK-NEXT: ; +// CHECK-NEXT: ; +// CHECK-NEXT: ; +// CHECK-NEXT: ; // CHECK-NEXT: ; // CHECK-NEXT: ; // CHECK-NEXT: ; // CHECK-NEXT: ; > buffer_store_dword v0, v1, s[0:3], 0 offen slc // CHECK: buffer_store_b32 v0, v1, s[0:3], 0 offen slc ; -// CHECK-NEXT: ; -// CHECK-NEXT: ; +// CHECK-NEXT: ; +// CHECK-NEXT: ; +// CHECK-NEXT: ; // CHECK-NEXT: ; // CHECK-NEXT: ; // CHECK-NEXT: ; @@ -23,9 +23,9 @@ buffer_store_dword v0, v1, s[0:3], 0 offen slc ; tbuffer ops use autogenerate asm parsers tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_FMT_32_32_SINT] offen offset:4092 slc // CHECK: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_FMT_32_32_SINT] offen offset:4092 slc ; -// CHECK-NEXT: ; -// CHECK-NEXT: ; +// CHECK-NEXT: ; +// CHECK-NEXT: ; +// CHECK-NEXT: ; // CHECK-NEXT: ; // CHECK-NEXT: ; // CHECK-NEXT: ; @@ -33,9 +33,9 @@ tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_FMT_32_32_SINT] offen // CHECK-NEXT: ; > tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] offen slc // CHECK: tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] offen slc ; -// CHECK-NEXT: ; -// CHECK-NEXT: ; +// CHECK-NEXT: ; +// CHECK-NEXT: ; +// CHECK-NEXT: ; // CHECK-NEXT: ; // CHECK-NEXT: ; // CHECK-NEXT: ; diff --git a/llvm/test/MC/Disassembler/ARM/sub-sp-imm-thumb2.txt b/llvm/test/MC/Disassembler/ARM/sub-sp-imm-thumb2.txt index 5c798f6acac85..9c2871a2c7d0a 100644 --- a/llvm/test/MC/Disassembler/ARM/sub-sp-imm-thumb2.txt +++ b/llvm/test/MC/Disassembler/ARM/sub-sp-imm-thumb2.txt @@ -6,32 +6,32 @@ # CHECK: subw sp, sp, #1148 # CHECK-SAME: -# CHECK-NEXT: +# CHECK-NEXT: +# CHECK-NEXT: # CHECK-NEXT: # CHECK-NEXT: -# CHECK-NEXT: > +# CHECK-NEXT: > 0xad 0xf2 0x7c 0x4d # CHECK: sub.w sp, sp, #1024 # CHECK-SAME: -# CHECK-NEXT: +# CHECK-NEXT: +# CHECK-NEXT: # CHECK-NEXT: # CHECK-NEXT: -# CHECK-NEXT: -# CHECK-NEXT: > +# CHECK-NEXT: +# CHECK-NEXT: > 0xad,0xf5,0x80,0x6d # CHECK: subs.w sp, sp, #1024 # CHECK-SAME: -# CHECK-NEXT: +# CHECK-NEXT: +# CHECK-NEXT: # CHECK-NEXT: # CHECK-NEXT: -# CHECK-NEXT: -# CHECK-NEXT: > +# CHECK-NEXT: +# CHECK-NEXT: > 0xbd,0xf5,0x80,0x6d diff --git a/llvm/test/MC/Lanai/conditional_inst.s b/llvm/test/MC/Lanai/conditional_inst.s index a0a8caf269fe8..1598a50681a36 100644 --- a/llvm/test/MC/Lanai/conditional_inst.s +++ b/llvm/test/MC/Lanai/conditional_inst.s @@ -7,7 +7,7 @@ bt %r5 ! CHECK: encoding: [0xc1,0x00,0x2d,0x00] ! CHECK-NEXT: > +! CHECK-NEXT: > ! BR classes bt 0x1234 @@ -27,14 +27,14 @@ jump2: ! CHECK: encoding: [0b1110110A,A,A,0x01'A'] ! CHECK-NEXT: fixup A - offset: 0, value: jump1, kind: FIXUP_LANAI_25 ! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: bpl jump2 ! CHECK: encoding: [0b1110101A,A,A,A] ! CHECK-NEXT: fixup A - offset: 0, value: jump2, kind: FIXUP_LANAI_25 ! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: bt . @@ -49,7 +49,7 @@ jump2: spl %r19 ! CHECK: encoding: [0xea,0x4c,0x00,0x02] ! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! BRR @@ -63,15 +63,15 @@ jump2: add.ge %r13, %r14, %r18 ! CHECK: encoding: [0xc9,0x34,0x70,0x06] ! CHECK-NEXT: -! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: > add.f %r13, %r14, %r18 ! CHECK: encoding: [0xc9,0x36,0x70,0x00] ! CHECK-NEXT: -! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: > diff --git a/llvm/test/MC/Lanai/memory.s b/llvm/test/MC/Lanai/memory.s index 0e6234645a80d..54c274e03ba92 100644 --- a/llvm/test/MC/Lanai/memory.s +++ b/llvm/test/MC/Lanai/memory.s @@ -7,88 +7,88 @@ ld [%r7], %r6 ! CHECK: encoding: [0x83,0x1c,0x00,0x00] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: ld [%r6], %r6 ! CHECK: encoding: [0x83,0x18,0x00,0x00] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: st %r6, [%r7] ! CHECK: encoding: [0x93,0x1c,0x00,0x00] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: ld 0x123[%r7*], %r6 ! CHECK: encoding: [0x83,0x1d,0x01,0x23] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: ld [%r7--], %r6 ! CHECK: encoding: [0x83,0x1d,0xff,0xfc] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: ld 0x123[%r7], %r6 ! CHECK: encoding: [0x83,0x1e,0x01,0x23] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: ld 0x123[*%r7], %r6 ! CHECK: encoding: [0x83,0x1f,0x01,0x23] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: ld [--%r7], %r6 ! CHECK: encoding: [0x83,0x1f,0xff,0xfc] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: st %r6, [%r7++] ! CHECK: encoding: [0x93,0x1d,0x00,0x04] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: st.h %r6, [%r7++] ! CHECK: encoding: [0xf3,0x1f,0x24,0x02] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: > ld.b [--%r7], %r6 ! CHECK: encoding: [0xf3,0x1f,0x4f,0xff] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: > @@ -96,31 +96,31 @@ ld [0x7fff], %r7 ! CHECK: encoding: [0x83,0x82,0x7f,0xff] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: ld [0x8000], %r7 ! CHECK: encoding: [0xf3,0x80,0x80,0x00] ! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! Negative RM value ld [0xfffffe8c], %pc ! CHECK: encoding: [0x81,0x02,0xfe,0x8c] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: ld [-372], %pc ! CHECK: encoding: [0x81,0x02,0xfe,0x8c] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: @@ -128,57 +128,57 @@ ld %r9[%r12*], %r20 ! CHECK: encoding: [0xaa,0x31,0x48,0x02] ! CHECK-NEXT: -! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ld %r9[%r12], %r20 ! CHECK: encoding: [0xaa,0x32,0x48,0x02] ! CHECK-NEXT: -! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ld [%r12 sub %r9], %r20 ! CHECK: encoding: [0xaa,0x32,0x4a,0x02] ! CHECK-NEXT: -! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ld %r9[*%r12], %r20 ! CHECK: encoding: [0xaa,0x33,0x48,0x02] ! CHECK-NEXT: -! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: st %r20, %r9[*%r12] ! CHECK: encoding: [0xba,0x33,0x48,0x02] ! CHECK-NEXT: -! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ld.b [%r12 sub %r9], %r20 ! CHECK: encoding: [0xaa,0x32,0x4a,0x04] ! CHECK-NEXT: -! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: uld.h [%r12 sub %r9], %r20 ! CHECK: encoding: [0xaa,0x32,0x4a,0x01] ! CHECK-NEXT: -! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: @@ -186,32 +186,32 @@ st.b %r3, [%r6] ! CHECK: encoding: [0xf1,0x9b,0x60,0x00] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: st.b %r3, 1[%r6*] ! CHECK: encoding: [0xf1,0x9b,0x64,0x01] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: st.b %r3, 1[%r6] ! CHECK: encoding: [0xf1,0x9b,0x68,0x01] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: st.b %r3, 1[*%r6] ! CHECK: encoding: [0xf1,0x9b,0x6c,0x01] ! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! CHECK-NEXT: @@ -219,13 +219,13 @@ st %r30, [0x1234] ! CHECK: encoding: [0xff,0x01,0x12,0x34] ! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ld [0xfe8c], %pc ! CHECK: encoding: [0xf1,0x00,0xfe,0x8c] ! CHECK-NEXT: +! CHECK-NEXT: ! CHECK-NEXT: ! SLI class @@ -233,15 +233,15 @@ ! CHECK: encoding: [0x02,0x01,A,A] ! CHECK-NEXT: fixup A - offset: 0, value: hi(x), kind: FIXUP_LANAI_HI16{{$}} ! CHECK-NEXT: -! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: mov hi(l+4), %r7 ! CHECK: encoding: [0x03,0x81,A,A] ! CHECK-NEXT: fixup A - offset: 0, value: hi(l)+4, kind: FIXUP_LANAI_HI16{{$}} ! CHECK-NEXT: -! CHECK-NEXT: -! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: +! CHECK-NEXT: diff --git a/llvm/test/TableGen/Common/RegClassByHwModeCommon.td b/llvm/test/TableGen/Common/RegClassByHwModeCommon.td new file mode 100644 index 0000000000000..8732a983470ed --- /dev/null +++ b/llvm/test/TableGen/Common/RegClassByHwModeCommon.td @@ -0,0 +1,44 @@ +include "llvm/Target/Target.td" + +class MyReg : Register { + let Namespace = "MyTarget"; +} + +class MyClass types, dag registers> + : RegisterClass<"MyTarget", types, size, registers> { + let Size = size; +} + +def X0 : MyReg<"x0">; +def X1 : MyReg<"x1">; +def X2 : MyReg<"x2">; +def X3 : MyReg<"x3">; +def X4 : MyReg<"x4">; +def X5 : MyReg<"x5">; +def X6 : MyReg<"x6">; +def XRegs : RegisterClass<"MyTarget", [i64], 64, (add X0, X1, X2, X3, X4, X5, X6)>; +def Y0 : MyReg<"y0">; +def Y1 : MyReg<"y1">; +def Y2 : MyReg<"y2">; +def Y3 : MyReg<"y3">; +def Y4 : MyReg<"y4">; +def Y5 : MyReg<"y5">; +def Y6 : MyReg<"y6">; +def YRegs : RegisterClass<"MyTarget", [i64], 64, (add Y0, Y1, Y2, Y3, Y4, Y5, Y6)>; + +class TestInstruction : Instruction { + let Size = 2; + let Namespace = "MyTarget"; + let hasSideEffects = false; + let hasExtraSrcRegAllocReq = false; + let hasExtraDefRegAllocReq = false; + + field bits<16> Inst; + bits<3> dst; + bits<3> src; + bits<3> opcode; + + let Inst{2-0} = dst; + let Inst{5-3} = src; + let Inst{7-5} = opcode; +} diff --git a/llvm/test/TableGen/RegClassByHwMode.td b/llvm/test/TableGen/RegClassByHwMode.td index ec723f8b70478..56a61eec3732f 100644 --- a/llvm/test/TableGen/RegClassByHwMode.td +++ b/llvm/test/TableGen/RegClassByHwMode.td @@ -1,10 +1,10 @@ -// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s -o - | FileCheck -check-prefix=INSTRINFO %s -// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s -o - | FileCheck -check-prefix=ASMMATCHER %s -// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s -o - | FileCheck -check-prefix=DISASM %s -// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s -o - | FileCheck -check-prefix=ISEL-SDAG %s -// RUN: llvm-tblgen -gen-global-isel -I %p/../../include %s -o - | FileCheck -check-prefix=ISEL-GISEL %s +// RUN: llvm-tblgen -gen-instr-info -I %S -I %p/../../include %s -o - | FileCheck -check-prefix=INSTRINFO %s +// RUN: llvm-tblgen -gen-asm-matcher -I %S -I %p/../../include %s -o - | FileCheck -check-prefix=ASMMATCHER %s +// RUN: llvm-tblgen -gen-disassembler -I %S -I %p/../../include %s -o - | FileCheck -check-prefix=DISASM %s +// RUN: llvm-tblgen -gen-dag-isel -I %S -I %p/../../include %s -o - | FileCheck -check-prefix=ISEL-SDAG %s +// RUN: llvm-tblgen -gen-global-isel -I %S -I %p/../../include %s -o - | FileCheck -check-prefix=ISEL-GISEL %s -include "llvm/Target/Target.td" +include "Common/RegClassByHwModeCommon.td" // INSTRINFO: #ifdef GET_INSTRINFO_ENUM // INSTRINFO-NEXT: #undef GET_INSTRINFO_ENUM @@ -302,8 +302,6 @@ include "llvm/Target/Target.td" // ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE), // ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, - - def HasAlignedRegisters : Predicate<"Subtarget->hasAlignedRegisters()">; def HasUnalignedRegisters : Predicate<"Subtarget->hasUnalignedRegisters()">; def IsPtr64 : Predicate<"Subtarget->isPtr64()">; @@ -317,34 +315,6 @@ def EvenMode : HwMode<[HasAlignedRegisters]>; def OddMode : HwMode<[HasUnalignedRegisters]>; def Ptr64 : HwMode<[IsPtr64]>; -class MyReg - : Register { - let Namespace = "MyTarget"; -} - -class MyClass types, dag registers> - : RegisterClass<"MyTarget", types, size, registers> { - let Size = size; -} - -def X0 : MyReg<"x0">; -def X1 : MyReg<"x1">; -def X2 : MyReg<"x2">; -def X3 : MyReg<"x3">; -def X4 : MyReg<"x4">; -def X5 : MyReg<"x5">; -def X6 : MyReg<"x6">; - -def Y0 : MyReg<"y0">; -def Y1 : MyReg<"y1">; -def Y2 : MyReg<"y2">; -def Y3 : MyReg<"y3">; -def Y4 : MyReg<"y4">; -def Y5 : MyReg<"y5">; -def Y6 : MyReg<"y6">; - - - def P0_32 : MyReg<"p0">; def P1_32 : MyReg<"p1">; def P2_32 : MyReg<"p2">; @@ -356,15 +326,12 @@ def P2_64 : MyReg<"p2_64">; def P3_64 : MyReg<"p3_64">; - -def XRegs : RegisterClass<"MyTarget", [i64], 64, (add X0, X1, X2, X3, X4, X5, X6)>; def XRegs_Odd : RegisterClass<"MyTarget", [i64], 64, (add X1, X3, X5)>; def XRegs_Even : RegisterClass<"MyTarget", [i64], 64, (add X0, X2, X4, X6)>; def XRegs_EvenIfRequired : RegClassByHwMode<[DefaultMode, EvenMode, OddMode], - [XRegs, XRegs_Even, XRegs_Odd]>; + [XRegs, XRegs_Even, XRegs_Odd]>; -def YRegs : RegisterClass<"MyTarget", [i64], 64, (add Y0, Y1, Y2, Y3, Y4, Y5, Y6)>; def YRegs_Even : RegisterClass<"MyTarget", [i64], 64, (add Y0, Y2, Y4, Y6)>; def YRegs_EvenIfRequired : RegClassByHwMode<[DefaultMode, EvenMode], @@ -385,23 +352,6 @@ def CustomDecodeYEvenIfRequired : RegisterOperand { let DecoderMethod = "YEvenIfRequiredCustomDecoder"; } -class TestInstruction : Instruction { - let Size = 2; - let Namespace = "MyTarget"; - let hasSideEffects = false; - let hasExtraSrcRegAllocReq = false; - let hasExtraDefRegAllocReq = false; - - field bits<16> Inst; - bits<3> dst; - bits<3> src; - bits<3> opcode; - - let Inst{2-0} = dst; - let Inst{5-3} = src; - let Inst{7-5} = opcode; -} - def SpecialOperand : RegisterOperand; def MY_MOV : TestInstruction { diff --git a/llvm/test/TableGen/RegClassByHwModeErrors.td b/llvm/test/TableGen/RegClassByHwModeErrors.td new file mode 100644 index 0000000000000..5d91b6e70410b --- /dev/null +++ b/llvm/test/TableGen/RegClassByHwModeErrors.td @@ -0,0 +1,88 @@ +// RUN: rm -rf %t && split-file %s %t +// RUN: not llvm-tblgen --gen-asm-matcher -I %p/../../include -I %t -I %S \ +// RUN: %t/inst-alias-bad-reg.td -o /dev/null 2>&1 | FileCheck %t/inst-alias-bad-reg.td --implicit-check-not="error:" +// RUN: not llvm-tblgen --gen-asm-matcher -I %p/../../include -I %t -I %S \ +// RUN: %t/inst-alias-static-predicates.td -o /dev/null 2>&1 | FileCheck %t/inst-alias-static-predicates.td --implicit-check-not="error:" +// RUN: not llvm-tblgen --gen-compress-inst-emitter -I %p/../../include -I %t -I %S \ +// RUN: %t/compress-regclass-by-hwmode.td -o /dev/null 2>&1 | FileCheck %t/compress-regclass-by-hwmode.td --implicit-check-not="error:" +// RUN: not llvm-tblgen --gen-compress-inst-emitter -I %p/../../include -I %t -I %S \ +// RUN: %t/compress-regclass-by-hwmode-2.td -o /dev/null 2>&1 | FileCheck %t/compress-regclass-by-hwmode-2.td --implicit-check-not="error:" + +//--- Common.td +include "Common/RegClassByHwModeCommon.td" + +def IsPtr64 : Predicate<"Subtarget->isPtr64()">; +def IsPtr32 : Predicate<"!Subtarget->isPtr64()">; +defvar Ptr32 = DefaultMode; +def Ptr64 : HwMode<[IsPtr64]>; +def PtrRC : RegClassByHwMode<[Ptr32, Ptr64], [XRegs, YRegs]>; + +def PTR_MOV : TestInstruction { + let OutOperandList = (outs PtrRC:$dst); + let InOperandList = (ins PtrRC:$src); + let AsmString = "ptr_mov $dst, $src"; + let opcode = 0; +} + + +//--- inst-alias-bad-reg.td +include "Common.td" +/// This should fail since X0 is not necessarily part of PtrRC. +def BAD_REG : InstAlias<"ptr_zero $rd", (PTR_MOV PtrRC:$dst, X0)>; +// CHECK: [[#@LINE-1]]:5: error: cannot resolve HwMode for PtrRC +// CHECK: Common.td:7:5: note: PtrRC defined here +def MyTargetISA : InstrInfo; +def MyTarget : Target { let InstructionSet = MyTargetISA; } + + +//--- inst-alias-static-predicates.td +include "Common.td" +/// In theory we could allow the following code since the predicates statically +/// resolve to the correct register class, but since this is non-trivial, check +// that we get a sensible-ish error instead. +let Predicates = [IsPtr32] in +def MOV_X0 : InstAlias<"mov_x0 $dst", (PTR_MOV PtrRC:$dst, X0)>; +// CHECK: [[#@LINE-1]]:5: error: cannot resolve HwMode for PtrRC +// CHECK: Common.td:7:5: note: PtrRC defined here +let Predicates = [IsPtr64] in +def MOV_Y0 : InstAlias<"mov_y0 $dst", (PTR_MOV PtrRC:$dst, Y0)>; + +def MyTargetISA : InstrInfo; +def MyTarget : Target { let InstructionSet = MyTargetISA; } + +//--- compress-regclass-by-hwmode.td +include "Common.td" +def PTR_ZERO_SMALL : TestInstruction { + let OutOperandList = (outs PtrRC:$dst); + let InOperandList = (ins); + let AsmString = "ptr_zero $dst"; + let opcode = 1; + let Size = 1; +} +/// This should fail since X0 is not necessarily part of PtrRC. +def : CompressPat<(PTR_MOV PtrRC:$dst, X0), + (PTR_ZERO_SMALL PtrRC:$dst)>; +// CHECK: [[#@LINE-2]]:1: error: cannot resolve HwMode for PtrRC +// CHECK: Common.td:7:5: note: PtrRC defined here +def MyTargetISA : InstrInfo; +def MyTarget : Target { let InstructionSet = MyTargetISA; } + + +//--- compress-regclass-by-hwmode-2.td +include "Common.td" +def X_MOV_BIG : TestInstruction { + let OutOperandList = (outs XRegs:$dst); + let InOperandList = (ins XRegs:$src); + let AsmString = "x_mov $dst, $src"; + let opcode = 1; + let Size = 4; +} +/// This should fail since PtrRC is not necessarily part of XRegs. +/// In theory, this could be resolved depending on the Predicates but +/// for not we should just always emit an error. +let Predicates = [IsPtr32] in +def : CompressPat<(X_MOV_BIG XRegs:$dst, XRegs:$src), + (PTR_MOV PtrRC:$dst, PtrRC:$src)>; +// CHECK: [[#@LINE-2]]:1: error: Type mismatch between Input and Output Dag operand 'dst' +def MyTargetISA : InstrInfo; +def MyTarget : Target { let InstructionSet = MyTargetISA; } diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/asm-show-inst.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/asm-show-inst.ll.expected index 0c579ed5eb4cb..0923d7c036076 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/asm-show-inst.ll.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/asm-show-inst.ll.expected @@ -7,16 +7,16 @@ define i8 @add_i8(i8 %a) nounwind { ; VERBOSE-LABEL: add_i8: ; VERBOSE: # %bb.0: ; VERBOSE-NEXT: movzbl {{[0-9]+}}(%esp), %eax # -; VERBOSE-NEXT: # +; VERBOSE-NEXT: # +; VERBOSE-NEXT: # ; VERBOSE-NEXT: # -; VERBOSE-NEXT: # +; VERBOSE-NEXT: # ; VERBOSE-NEXT: # -; VERBOSE-NEXT: # > +; VERBOSE-NEXT: # > ; VERBOSE-NEXT: addb $2, %al # > ; VERBOSE-NEXT: retl # > +; VERBOSE-NEXT: # > ; ; CHECK-LABEL: add_i8: ; CHECK: # %bb.0: @@ -31,18 +31,18 @@ define i32 @add_i32(i32 %a) nounwind { ; VERBOSE-LABEL: add_i32: ; VERBOSE: # %bb.0: ; VERBOSE-NEXT: movl {{[0-9]+}}(%esp), %eax # -; VERBOSE-NEXT: # +; VERBOSE-NEXT: # +; VERBOSE-NEXT: # ; VERBOSE-NEXT: # -; VERBOSE-NEXT: # +; VERBOSE-NEXT: # ; VERBOSE-NEXT: # -; VERBOSE-NEXT: # > +; VERBOSE-NEXT: # > ; VERBOSE-NEXT: addl $2, %eax # -; VERBOSE-NEXT: # +; VERBOSE-NEXT: # +; VERBOSE-NEXT: # ; VERBOSE-NEXT: # > ; VERBOSE-NEXT: retl # > +; VERBOSE-NEXT: # > ; ; CHECK-LABEL: add_i32: ; CHECK: # %bb.0: diff --git a/llvm/utils/TableGen/Common/CodeGenInstAlias.cpp b/llvm/utils/TableGen/Common/CodeGenInstAlias.cpp index 04d4855b81d3b..d3050c0553114 100644 --- a/llvm/utils/TableGen/Common/CodeGenInstAlias.cpp +++ b/llvm/utils/TableGen/Common/CodeGenInstAlias.cpp @@ -40,10 +40,9 @@ unsigned CodeGenInstAlias::ResultOperand::getMINumOperands() const { using ResultOperand = CodeGenInstAlias::ResultOperand; -static Expected matchSimpleOperand(const Init *Arg, - const StringInit *ArgName, - const Record *Op, - const CodeGenTarget &T) { +static Expected +matchSimpleOperand(const Init *Arg, const StringInit *ArgName, const Record *Op, + const CodeGenTarget &T, ArrayRef Loc) { if (const Record *OpRC = T.getAsRegClassLike(Op)) { if (const auto *ArgDef = dyn_cast(Arg)) { const Record *ArgRec = ArgDef->getDef(); @@ -52,7 +51,8 @@ static Expected matchSimpleOperand(const Init *Arg, if (const Record *ArgRC = T.getInitValueAsRegClassLike(Arg)) { if (ArgRC->isSubClassOf("RegisterClass")) { if (!OpRC->isSubClassOf("RegisterClass") || - !T.getRegisterClass(OpRC).hasSubClass(&T.getRegisterClass(ArgRC))) + !T.getRegisterClass(OpRC, Loc).hasSubClass( + &T.getRegisterClass(ArgRC, Loc))) return createStringError( "argument register class " + ArgRC->getName() + " is not a subclass of operand register class " + @@ -70,7 +70,8 @@ static Expected matchSimpleOperand(const Init *Arg, // Match 'Reg'. if (ArgRec->isSubClassOf("Register")) { - if (!T.getRegisterClass(OpRC).contains(T.getRegBank().getReg(ArgRec))) + if (!T.getRegisterClass(OpRC, Loc).contains( + T.getRegBank().getReg(ArgRec))) return createStringError( "register argument " + ArgRec->getName() + " is not a member of operand register class " + OpRC->getName()); @@ -199,7 +200,8 @@ CodeGenInstAlias::CodeGenInstAlias(const Record *R, const CodeGenTarget &T) const Record *SubOp = cast(OpInfo.MIOperandInfo->getArg(SubOpIdx))->getDef(); Expected ResOpOrErr = matchSimpleOperand( - ArgDag->getArg(SubOpIdx), ArgDag->getArgName(SubOpIdx), SubOp, T); + ArgDag->getArg(SubOpIdx), ArgDag->getArgName(SubOpIdx), SubOp, T, + R->getLoc()); if (!ResOpOrErr) PrintFatalError(R, "in argument #" + Twine(ArgIdx) + "." + Twine(SubOpIdx) + ": " + @@ -220,8 +222,9 @@ CodeGenInstAlias::CodeGenInstAlias(const Record *R, const CodeGenTarget &T) } else { // Simple operand (RegisterClass, RegisterOperand or Operand with empty // MIOperandInfo). - Expected ResOpOrErr = matchSimpleOperand( - Result->getArg(ArgIdx), Result->getArgName(ArgIdx), Op, T); + Expected ResOpOrErr = + matchSimpleOperand(Result->getArg(ArgIdx), Result->getArgName(ArgIdx), + Op, T, R->getLoc()); if (!ResOpOrErr) PrintFatalError(R, "in argument #" + Twine(ArgIdx) + ": " + toString(ResOpOrErr.takeError())); diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp index e853303c37aff..65a2594859e69 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp @@ -1316,11 +1316,19 @@ CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, return {&RegClasses.back(), true}; } -CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const { +CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def, + ArrayRef Loc) const { + assert(Def->isSubClassOf("RegisterClassLike")); if (CodeGenRegisterClass *RC = Def2RC.lookup(Def)) return RC; - PrintFatalError(Def->getLoc(), "Not a known RegisterClass!"); + ArrayRef DiagLoc = Loc.empty() ? Def->getLoc() : Loc; + // TODO: Ideally we should update the API to allow resolving HwMode. + if (Def->isSubClassOf("RegClassByHwMode")) + PrintError(DiagLoc, "cannot resolve HwMode for " + Def->getName()); + else + PrintError(DiagLoc, Def->getName() + " is not a known RegisterClass!"); + PrintFatalNote(Def->getLoc(), Def->getName() + " defined here"); } CodeGenSubRegIndex * diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h index c02d04b648534..a3ad0b797a704 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.h +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h @@ -815,7 +815,8 @@ class CodeGenRegBank { } // Find a register class from its def. - CodeGenRegisterClass *getRegClass(const Record *) const; + CodeGenRegisterClass *getRegClass(const Record *, + ArrayRef Loc = {}) const; /// getRegisterClassForRegister - Find the register class that contains the /// specified physical register. If the register is not in a register diff --git a/llvm/utils/TableGen/Common/CodeGenTarget.cpp b/llvm/utils/TableGen/Common/CodeGenTarget.cpp index f093a61e5a6f6..cca318a6e2047 100644 --- a/llvm/utils/TableGen/Common/CodeGenTarget.cpp +++ b/llvm/utils/TableGen/Common/CodeGenTarget.cpp @@ -173,8 +173,8 @@ const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { } const CodeGenRegisterClass & -CodeGenTarget::getRegisterClass(const Record *R) const { - return *getRegBank().getRegClass(R); +CodeGenTarget::getRegisterClass(const Record *R, ArrayRef Loc) const { + return *getRegBank().getRegClass(R, Loc); } std::vector diff --git a/llvm/utils/TableGen/Common/CodeGenTarget.h b/llvm/utils/TableGen/Common/CodeGenTarget.h index d7390c72ea352..dc1740b174148 100644 --- a/llvm/utils/TableGen/Common/CodeGenTarget.h +++ b/llvm/utils/TableGen/Common/CodeGenTarget.h @@ -131,7 +131,8 @@ class CodeGenTarget { return RegAltNameIndices; } - const CodeGenRegisterClass &getRegisterClass(const Record *R) const; + const CodeGenRegisterClass &getRegisterClass(const Record *R, + ArrayRef Loc = {}) const; /// Convenience wrapper to avoid hardcoding the name of RegClassByHwMode /// everywhere. This is here instead of CodeGenRegBank to avoid the fatal diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp index d8c5ca7c1e1a3..94fe3823fae22 100644 --- a/llvm/utils/TableGen/CompressInstEmitter.cpp +++ b/llvm/utils/TableGen/CompressInstEmitter.cpp @@ -142,7 +142,8 @@ class CompressInstEmitter { void emitCompressInstEmitter(raw_ostream &OS, EmitterType EType); bool validateTypes(const Record *DagOpType, const Record *InstOpType, bool IsSourceInst); - bool validateRegister(const Record *Reg, const Record *RegClass); + bool validateRegister(const Record *Reg, const Record *RegClass, + ArrayRef Loc); void checkDagOperandMapping(const Record *Rec, const StringMap &DestOperands, const DagInit *SourceDag, const DagInit *DestDag); @@ -162,11 +163,12 @@ class CompressInstEmitter { } // End anonymous namespace. bool CompressInstEmitter::validateRegister(const Record *Reg, - const Record *RegClass) { + const Record *RegClass, + ArrayRef Loc) { assert(Reg->isSubClassOf("Register") && "Reg record should be a Register"); - assert(RegClass->isSubClassOf("RegisterClass") && - "RegClass record should be a RegisterClass"); - const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass); + assert(RegClass->isSubClassOf("RegisterClassLike") && + "RegClass record should be RegisterClassLike"); + const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass, Loc); const CodeGenRegister *R = Target.getRegBank().getReg(Reg); assert(R != nullptr && "Register not defined!!"); return RC.contains(R); @@ -255,7 +257,7 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec, if (const auto *DI = dyn_cast(Dag->getArg(DAGOpNo))) { if (DI->getDef()->isSubClassOf("Register")) { // Check if the fixed register belongs to the Register class. - if (!validateRegister(DI->getDef(), OpndRec)) + if (!validateRegister(DI->getDef(), OpndRec, Rec->getLoc())) PrintFatalError(Rec->getLoc(), "Error in Dag '" + Dag->getAsString() + "'Register: '" + DI->getDef()->getName() +