From f4dc6bf7923e3f22076bc5bfc2b57074580deb95 Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Wed, 10 Dec 2025 14:01:07 -0800 Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?= =?UTF-8?q?l=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.8-beta.1 --- llvm/test/TableGen/RegClassByHwMode.td | 48 +++++++++++------------ llvm/utils/TableGen/AsmMatcherEmitter.cpp | 5 ++- llvm/utils/TableGen/InstrInfoEmitter.cpp | 6 ++- 3 files changed, 31 insertions(+), 28 deletions(-) diff --git a/llvm/test/TableGen/RegClassByHwMode.td b/llvm/test/TableGen/RegClassByHwMode.td index a29c8747a7c20..0be22be560bea 100644 --- a/llvm/test/TableGen/RegClassByHwMode.td +++ b/llvm/test/TableGen/RegClassByHwMode.td @@ -42,24 +42,24 @@ include "Common/RegClassByHwModeCommon.td" // INSTRINFO: extern const int16_t MyTargetRegClassByHwModeTables[4][3] = { // INSTRINFO-NEXT: { // DefaultMode -// INSTRINFO-NEXT: MyTarget::PtrRegs32RegClassID, -// INSTRINFO-NEXT: MyTarget::XRegsRegClassID, -// INSTRINFO-NEXT: MyTarget::YRegsRegClassID, +// INSTRINFO-NEXT: MyTarget::PtrRegs32RegClassID, // MyPtrRC +// INSTRINFO-NEXT: MyTarget::XRegsRegClassID, // XRegs_EvenIfRequired +// INSTRINFO-NEXT: MyTarget::YRegsRegClassID, // YRegs_EvenIfRequired // INSTRINFO-NEXT: }, // INSTRINFO-NEXT: { // EvenMode -// INSTRINFO-NEXT: -1, // Missing mode entry -// INSTRINFO-NEXT: MyTarget::XRegs_EvenRegClassID, -// INSTRINFO-NEXT: MyTarget::YRegs_EvenRegClassID, +// INSTRINFO-NEXT: -1, // Missing mode entry for MyPtrRC +// INSTRINFO-NEXT: MyTarget::XRegs_EvenRegClassID, // XRegs_EvenIfRequired +// INSTRINFO-NEXT: MyTarget::YRegs_EvenRegClassID, // YRegs_EvenIfRequired // INSTRINFO-NEXT: }, // INSTRINFO-NEXT: { // OddMode -// INSTRINFO-NEXT: -1, // Missing mode entry -// INSTRINFO-NEXT: MyTarget::XRegs_OddRegClassID, -// INSTRINFO-NEXT: -1, // Missing mode entry +// INSTRINFO-NEXT: -1, // Missing mode entry for MyPtrRC +// INSTRINFO-NEXT: MyTarget::XRegs_OddRegClassID, // XRegs_EvenIfRequired +// INSTRINFO-NEXT: -1, // Missing mode entry for YRegs_EvenIfRequired // INSTRINFO-NEXT: }, // INSTRINFO-NEXT: { // Ptr64 -// INSTRINFO-NEXT: MyTarget::PtrRegs64RegClassID, -// INSTRINFO-NEXT: -1, // Missing mode entry -// INSTRINFO-NEXT: -1, // Missing mode entry +// INSTRINFO-NEXT: MyTarget::PtrRegs64RegClassID, // MyPtrRC +// INSTRINFO-NEXT: -1, // Missing mode entry for XRegs_EvenIfRequired +// INSTRINFO-NEXT: -1, // Missing mode entry for YRegs_EvenIfRequired // INSTRINFO-NEXT: }, // INSTRINFO-NEXT: }; @@ -92,24 +92,24 @@ include "Common/RegClassByHwModeCommon.td" // ASMMATCHER: if (Operand.isReg() && Kind > MCK_LAST_REGISTER && Kind <= MCK_LAST_REGCLASS_BY_HWMODE) { // ASMMATCHER-NEXT: static constexpr MatchClassKind RegClassByHwModeMatchTable[4][3] = { // ASMMATCHER-NEXT: { // DefaultMode -// ASMMATCHER-NEXT: MCK_PtrRegs32, -// ASMMATCHER-NEXT: MCK_XRegs, -// ASMMATCHER-NEXT: MCK_YRegs, +// ASMMATCHER-NEXT: MCK_PtrRegs32, // MyPtrRC +// ASMMATCHER-NEXT: MCK_XRegs, // XRegs_EvenIfRequired +// ASMMATCHER-NEXT: MCK_YRegs, // YRegs_EvenIfRequired // ASMMATCHER-NEXT: }, // ASMMATCHER-NEXT: { // EvenMode -// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode -// ASMMATCHER-NEXT: MCK_XRegs_Even, -// ASMMATCHER-NEXT: MCK_YRegs_Even, +// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode entry for MyPtrRC +// ASMMATCHER-NEXT: MCK_XRegs_Even, // XRegs_EvenIfRequired +// ASMMATCHER-NEXT: MCK_YRegs_Even, // YRegs_EvenIfRequired // ASMMATCHER-NEXT: }, // ASMMATCHER-NEXT: { // OddMode -// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode -// ASMMATCHER-NEXT: MCK_XRegs_Odd, -// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode +// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode entry for MyPtrRC +// ASMMATCHER-NEXT: MCK_XRegs_Odd, // XRegs_EvenIfRequired +// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode entry for YRegs_EvenIfRequired // ASMMATCHER-NEXT: }, // ASMMATCHER-NEXT: { // Ptr64 -// ASMMATCHER-NEXT: MCK_PtrRegs64, -// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode -// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode +// ASMMATCHER-NEXT: MCK_PtrRegs64, // MyPtrRC +// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode entry for XRegs_EvenIfRequired +// ASMMATCHER-NEXT: InvalidMatchClass, // Missing mode entry for YRegs_EvenIfRequired // ASMMATCHER-NEXT: }, // ASMMATCHER-NEXT: }; // ASMMATCHER-EMPTY: diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp index 63c9c3bfff169..e6085af5aa91e 100644 --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -2581,13 +2581,14 @@ static void emitValidateOperandClass(const CodeGenTarget &Target, }); if (FoundMode == ModeSelect.Items.end()) { - OS << indent(8) << "InvalidMatchClass, // Missing mode\n"; + OS << indent(8) << "InvalidMatchClass, // Missing mode entry for " + << Class->getName() << "\n"; } else { const CodeGenRegisterClass *RegClass = RegBank.getRegClass(FoundMode->second); const ClassInfo *CI = Info.RegisterClassClasses.at(RegClass->getDef()); - OS << indent(8) << CI->Name << ",\n"; + OS << indent(8) << CI->Name << ", // " << Class->getName() << "\n"; } } diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index 0faef33a386e7..db3ac698411fd 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -1116,11 +1116,13 @@ void InstrInfoEmitter::run(raw_ostream &OS) { if (FoundMode == ModeSelect.Items.end()) { // If a RegClassByHwMode doesn't have an entry corresponding to a // mode, pad with default register class. - OS << indent(4) << "-1, // Missing mode entry\n"; + OS << indent(4) << "-1, // Missing mode entry for " << Class->getName() + << "\n"; } else { const CodeGenRegisterClass *RegClass = RegBank.getRegClass(FoundMode->second); - OS << indent(4) << RegClass->getQualifiedIdName() << ",\n"; + OS << indent(4) << RegClass->getQualifiedIdName() << ", // " + << Class->getName() << "\n"; } }