From 38fa134100d0d015cc03a99d27647ac87805d8ed Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Wed, 10 Dec 2025 15:33:21 -0800 Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?= =?UTF-8?q?l=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.8-beta.1 --- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 9bb3724c96c11..483d0a36966fe 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -128,6 +128,8 @@ class RISCVAsmParser : public MCTargetAsmParser { // Helper to actually emit an instruction to the MCStreamer. Also, when // possible, compression of the instruction is performed. void emitToStreamer(MCStreamer &S, const MCInst &Inst); + void validateInstructionPreEmit(const MCInst &Inst, + const MCSubtargetInfo &STI); // Helper to emit a combination of LUI, ADDI(W), and SLLI instructions that // synthesize the desired immediate value into the destination register. @@ -3471,6 +3473,34 @@ bool RISCVAsmParser::parseDirectiveVariantCC() { return false; } +void RISCVAsmParser::validateInstructionPreEmit(const MCInst &Inst, const MCSubtargetInfo &STI) { + // Ensure that we don't emit instructions with missing predicates or invalid + // register classes. + // TODO: ideally this code should be shared between targets. + RISCV_MC::verifyInstructionPredicates(Inst.getOpcode(), STI.getFeatureBits()); + const MCRegisterInfo *MRI = getContext().getRegisterInfo(); + unsigned HwMode = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo); + const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); + for (auto [I, Op] : enumerate(Inst.getOperands())) { + if (Op.isReg() && Op.getReg().isValid()) { + auto RCID = MII.getOpRegClassID(Desc.operands()[I], HwMode); + // Some instructions don't have a valid regclass, e.g. .insn_* + if (RCID == -1) + continue; + const MCRegisterClass &RegClass = MRI->getRegClass(RCID); + if (!RegClass.contains(Op.getReg())) { + getParser().printError(getLoc(), MII.getName(Inst.getOpcode()) + " operand " + + Twine(I + 1) + " register " + + MRI->getName(Op.getReg()) + + " is not a member of register class " + + MRI->getRegClassName(&RegClass)); + reportFatalInternalError("Attempting to emit invalid instruction. " + "Incorrect pseudo expansion?"); + } + } + } +} + void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) { MCInst CInst; bool Res = false; @@ -3479,6 +3509,7 @@ void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) { Res = RISCVRVC::compress(CInst, Inst, STI); if (Res) ++RISCVNumInstrsCompressed; + validateInstructionPreEmit((Res ? CInst : Inst), STI); S.emitInstruction((Res ? CInst : Inst), STI); }