diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
index 4f754021f5544..d129e8f963178 100644
--- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
@@ -361,16 +361,20 @@ static void emitAssignName(Instruction *I, IRBuilder<> &B) {
       expectIgnoredInIRTranslation(I))
     return;
 
-  if (isa<CallBase>(I)) {
-    // TODO: this is a temporary workaround meant to prevent inserting internal
-    //       noise into the generated binary; remove once we rework the entire
-    //       aggregate removal machinery.
-    StringRef Name = I->getName();
-    if (Name.starts_with("spv.mutated_callsite"))
-      return;
-    if (Name.starts_with("spv.named_mutated_callsite"))
-      I->setName(Name.substr(Name.rfind('.') + 1));
-  }
+  // We want to be conservative when adding the names because they can interfere
+  // with later optimizations.
+  bool KeepName = false;
+  if (isa<AllocaInst>(I)) {
+    KeepName = true;
+  } else if (auto *CI = dyn_cast<CallBase>(I)) {
+    Function *F = CI->getCalledFunction();
+    if (F && F->getName().starts_with("llvm.spv.alloca"))
+      KeepName = true;
+  }
+
+  if (!KeepName)
+    return;
+
   reportFatalOnTokenType(I);
   setInsertPointAfterDef(B, I);
   LLVMContext &Ctx = I->getContext();
diff --git a/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll b/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll
index 86581a5468405..79ca18bb70a20 100644
--- a/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll
+++ b/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll
@@ -5,9 +5,10 @@
 
 ;; LLVM IR was generated with -cl-std=c++ option
 
-define spir_kernel void @test(float %op1, float %op2) {
+define spir_kernel void @test(float %op1, float %op2, i32 addrspace(1)* %out) {
 entry:
   %call = call spir_func i32 @_Z14isgreaterequalff(float %op1, float %op2)
+  store i32 %call, i32 addrspace(1)* %out
   ret void
 }
 
diff --git a/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-addrspacecast.ll b/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-addrspacecast.ll
index 58638578bb3f0..0c6f6c9a53b1d 100644
--- a/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-addrspacecast.ll
+++ b/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-addrspacecast.ll
@@ -4,5 +4,6 @@ target triple = "spirv64"
 define void @addrspacecast(ptr addrspace(9) %a) {
 ; CHECK: unable to legalize instruction: %{{.*}}:pid(p4) = G_ADDRSPACE_CAST %{{.*}}:pid(p9)
   %res1 = addrspacecast ptr addrspace(9) %a to ptr addrspace(4)
+  store i8 0, ptr addrspace(4) %res1
   ret void
 }
diff --git a/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-load.ll b/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-load.ll
index 229f2234220ab..e7a9decf0c327 100644
--- a/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-load.ll
+++ b/llvm/test/CodeGen/SPIRV/GlobalISel/fn-ptr-load.ll
@@ -1,8 +1,9 @@
 ; RUN: not llc --global-isel %s -filetype=null 2>&1 | FileCheck %s
 target triple = "spirv64"
 
-define void @do_load(ptr addrspace(9) %a) {
+define void @do_load(ptr addrspace(9) %a, ptr addrspace(1) %out) {
 ; CHECK: unable to legalize instruction: %{{.*}}:iid(s32) = G_LOAD %{{.*}}:pid(p9) 
   %val = load i32, ptr addrspace(9) %a
+  store i32 %val, ptr addrspace(1) %out
   ret void
 }
diff --git a/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll b/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll
index 6e414f79bdde5..125cc6137e78b 100644
--- a/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll
+++ b/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll
@@ -24,6 +24,7 @@ entry:
   %selected = select i1 %3, i8 0, i8 1
   %frombool.i = zext i1 %3 to i8
   %sum = add i8 %frombool.i, %selected
+  store volatile i8 %sum, i8 addrspace(4)* %ptridx.ascast.i.i, align 1
   store i8 %selected, i8 addrspace(4)* %ptridx.ascast.i.i, align 1
   ret void
 }
diff --git a/llvm/test/CodeGen/SPIRV/TruncToBool.ll b/llvm/test/CodeGen/SPIRV/TruncToBool.ll
index 6682c23f34e96..8e23f4eb06914 100644
--- a/llvm/test/CodeGen/SPIRV/TruncToBool.ll
+++ b/llvm/test/CodeGen/SPIRV/TruncToBool.ll
@@ -3,10 +3,11 @@
 ; CHECK-SPIRV:      OpBitwiseAnd
 ; CHECK-SPIRV-NEXT: OpINotEqual
 
-define spir_kernel void @test(i32 %op1, i32 %op2, i8 %op3) {
+define spir_kernel void @test(i32 %op1, i32 %op2, i8 %op3, i32 addrspace(1)* %out) {
 entry:
   %0 = trunc i8 %op3 to i1
   %call = call spir_func i32 @_Z14__spirv_Selectbii(i1 zeroext %0, i32 %op1, i32 %op2)
+  store i32 %call, i32 addrspace(1)* %out
   ret void
 }
 
diff --git a/llvm/test/CodeGen/SPIRV/debug-info/opname-filtering.ll b/llvm/test/CodeGen/SPIRV/debug-info/opname-filtering.ll
new file mode 100644
index 0000000000000..bfe25188662f4
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/debug-info/opname-filtering.ll
@@ -0,0 +1,46 @@
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; Verify that OpName is generated for Global Variables, Functions, Parameters,
+; Local Variables (Alloca), and Basic Blocks (Labels).
+; We preserve these names because they significantly improve the readability of
+; the generated SPIR-V binary and are unlikely to inhibit optimizations (like
+; Dead Code Elimination) since they define the interface or storage of the program.
+
+; 1. Global variables ("GlobalVar")
+; CHECK-DAG: OpName %[[#GlobalVar:]] "GlobalVar"
+
+; 2. Functions ("test_names")
+; CHECK-DAG: OpName %[[#Func:]] "test_names"
+
+; 3. Function parameters ("param")
+; CHECK-DAG: OpName %[[#Param:]] "param"
+
+; 4. Local variables (AllocaInst) ("localVar")
+; CHECK-DAG: OpName %[[#LocalVar:]] "localVar"
+
+; 5. Basic Blocks ("entry", "body")
+; CHECK-DAG: OpName %[[#Entry:]] "entry"
+; CHECK-DAG: OpName %[[#Body:]] "body"
+
+; Verify that OpName is NOT generated for intermediate instructions
+; (arithmetic, etc.). This reduces file size and noise, and prevents
+; potential interference with optimizations where the presence of a Name
+; (user) might incorrectly keep a dead instruction alive in some test scenarios.
+
+; CHECK-NOT: OpName %{{.*}} "add"
+; CHECK-NOT: OpName %{{.*}} "sub"
+
+@GlobalVar = global i32 0
+
+define spir_func void @test_names(i32 %param) {
+entry:
+  %localVar = alloca i32
+  br label %body
+
+body:
+  %add = add i32 %param, 1
+  %sub = sub i32 %add, 1
+  store i32 %sub, i32* %localVar
+  ret void
+}
diff --git a/llvm/test/CodeGen/SPIRV/entry-point-interfaces.ll b/llvm/test/CodeGen/SPIRV/entry-point-interfaces.ll
index f1e092732558e..019e60dad41ae 100644
--- a/llvm/test/CodeGen/SPIRV/entry-point-interfaces.ll
+++ b/llvm/test/CodeGen/SPIRV/entry-point-interfaces.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK: OpEntryPoint Kernel %[[#Func:]] "test" %[[#Interface1:]] %[[#Interface2:]] %[[#Interface3:]] %[[#Interface4:]]
+; CHECK: OpEntryPoint Kernel %[[#Func:]] "test" %[[#Interface3:]] %[[#Interface4:]] %[[#Interface1:]] %[[#Interface2:]]
 ; CHECK-DAG: OpName %[[#Func]] "test"
 ; CHECK-DAG: OpName %[[#Interface1]] "var"
 ; CHECK-DAG: OpName %[[#Interface3]] "var2"
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll
index 4428a2049f9ce..0b39ee853b057 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll
@@ -1,17 +1,14 @@
 ; Adapted from https://github.com/KhronosGroup/SPIRV-LLVM-Translator/tree/main/test/extensions/INTEL/SPV_INTEL_cache_controls
 
 ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_cache_controls %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV
-; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_cache_controls %s -o - -filetype=obj | spirv-val %}
+; RUN: %if spirv-tools %{ llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_cache_controls %s -o - -filetype=obj | spirv-val %}
 
 ; CHECK-SPIRV: Capability CacheControlsINTEL
 ; CHECK-SPIRV: Extension "SPV_INTEL_cache_controls"
 
-; CHECK-SPIRV-DAG: OpName %[[#Ptr1:]] "ptr1"
-; CHECK-SPIRV-DAG: OpName %[[#Ptr2:]] "ptr2"
-; CHECK-SPIRV-DAG: OpName %[[#Ptr3:]] "ptr3"
-; CHECK-SPIRV-DAG: OpDecorate %[[#Ptr1]] CacheControlLoadINTEL 0 1
-; CHECK-SPIRV-DAG: OpDecorate %[[#Ptr2]] CacheControlLoadINTEL 1 1
-; CHECK-SPIRV-DAG: OpDecorate %[[#Ptr3]] CacheControlStoreINTEL 2 3
+; CHECK-SPIRV-DAG: OpDecorate %[[#Ptr1:]] CacheControlLoadINTEL 0 1
+; CHECK-SPIRV-DAG: OpDecorate %[[#Ptr2:]] CacheControlLoadINTEL 1 1
+; CHECK-SPIRV-DAG: OpDecorate %[[#Ptr3:]] CacheControlStoreINTEL 2 3
 ; CHECK-SPIRV: OpExtInst %[[#]] %[[#]] prefetch %[[#Ptr1]] %[[#]]
 ; CHECK-SPIRV: OpExtInst %[[#]] %[[#]] prefetch %[[#Ptr2]] %[[#]]
 ; CHECK-SPIRV: OpExtInst %[[#]] %[[#]] prefetch %[[#Ptr3]] %[[#]]
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_max_error/IntelFPMaxErrorFPMath.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_max_error/IntelFPMaxErrorFPMath.ll
index 635015c970d3e..34c3741cfc6ef 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_max_error/IntelFPMaxErrorFPMath.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fp_max_error/IntelFPMaxErrorFPMath.ll
@@ -9,22 +9,25 @@
 ; CHECK: OpExtension "SPV_INTEL_fp_max_error"
 
 ; CHECK: OpName %[[#CalleeName:]] "callee"
-; CHECK: OpName %[[#F3:]] "f3"
-; CHECK: OpDecorate %[[#F3]] FPMaxErrorDecorationINTEL 1075838976
+; CHECK: OpDecorate %[[#F3:]] FPMaxErrorDecorationINTEL 1075838976
 ; CHECK: OpDecorate %[[#Callee:]] FPMaxErrorDecorationINTEL 1065353216
 
 ; CHECK: %[[#FloatTy:]] = OpTypeFloat 32
-; CHECK: %[[#Callee]] = OpFunctionCall %[[#FloatTy]] %[[#CalleeName]]
 
 define float @callee(float %f1, float %f2) {
 entry:
 ret float %f1
 }
 
-define void @test_fp_max_error_decoration(float %f1, float %f2) {
+; CHECK: %[[#F3]] = OpFDiv %[[#FloatTy]]
+; CHECK: %[[#Callee]] = OpFunctionCall %[[#FloatTy]] %[[#CalleeName]]
+
+define void @test_fp_max_error_decoration(float %f1, float %f2, float* %out) {
 entry:
 %f3 = fdiv float %f1, %f2, !fpmath !0
-call float @callee(float %f1, float %f2), !fpmath !1
+store volatile float %f3, float* %out
+%call = call float @callee(float %f1, float %f2), !fpmath !1
+store volatile float %call, float* %out
 ret void
 }
 
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/decoration.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/decoration.ll
index 81497f26f1aef..c7326cd7b4cfa 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/decoration.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/decoration.ll
@@ -4,80 +4,34 @@
 ; CHECK-DAG: Capability FloatControls2
 ; CHECK: Extension "SPV_KHR_float_controls2"
 
-; CHECK: OpName %[[#addRes:]] "addRes"
-; CHECK: OpName %[[#subRes:]] "subRes"
-; CHECK: OpName %[[#mulRes:]] "mulRes"
-; CHECK: OpName %[[#divRes:]] "divRes"
-; CHECK: OpName %[[#remRes:]] "remRes"
-; CHECK: OpName %[[#negRes:]] "negRes"
-; CHECK: OpName %[[#oeqRes:]] "oeqRes"
-; CHECK: OpName %[[#oneRes:]] "oneRes"
-; CHECK: OpName %[[#oltRes:]] "oltRes"
-; CHECK: OpName %[[#ogtRes:]] "ogtRes"
-; CHECK: OpName %[[#oleRes:]] "oleRes"
-; CHECK: OpName %[[#ogeRes:]] "ogeRes"
-; CHECK: OpName %[[#ordRes:]] "ordRes"
-; CHECK: OpName %[[#ueqRes:]] "ueqRes"
-; CHECK: OpName %[[#uneRes:]] "uneRes"
-; CHECK: OpName %[[#ultRes:]] "ultRes"
-; CHECK: OpName %[[#ugtRes:]] "ugtRes"
-; CHECK: OpName %[[#uleRes:]] "uleRes"
-; CHECK: OpName %[[#ugeRes:]] "ugeRes"
-; CHECK: OpName %[[#unoRes:]] "unoRes"
-; CHECK: OpName %[[#modRes:]] "modRes"
-; CHECK: OpName %[[#maxRes:]] "maxRes"
-; CHECK: OpName %[[#maxCommonRes:]] "maxCommonRes"
-; CHECK: OpName %[[#addResV:]] "addResV"
-; CHECK: OpName %[[#subResV:]] "subResV"
-; CHECK: OpName %[[#mulResV:]] "mulResV"
-; CHECK: OpName %[[#divResV:]] "divResV"
-; CHECK: OpName %[[#remResV:]] "remResV"
-; CHECK: OpName %[[#negResV:]] "negResV"
-; CHECK: OpName %[[#oeqResV:]] "oeqResV"
-; CHECK: OpName %[[#oneResV:]] "oneResV"
-; CHECK: OpName %[[#oltResV:]] "oltResV"
-; CHECK: OpName %[[#ogtResV:]] "ogtResV"
-; CHECK: OpName %[[#oleResV:]] "oleResV"
-; CHECK: OpName %[[#ogeResV:]] "ogeResV"
-; CHECK: OpName %[[#ordResV:]] "ordResV"
-; CHECK: OpName %[[#ueqResV:]] "ueqResV"
-; CHECK: OpName %[[#uneResV:]] "uneResV"
-; CHECK: OpName %[[#ultResV:]] "ultResV"
-; CHECK: OpName %[[#ugtResV:]] "ugtResV"
-; CHECK: OpName %[[#uleResV:]] "uleResV"
-; CHECK: OpName %[[#ugeResV:]] "ugeResV"
-; CHECK: OpName %[[#unoResV:]] "unoResV"
-; CHECK: OpName %[[#modResV:]] "modResV"
-; CHECK: OpName %[[#maxResV:]] "maxResV"
-; CHECK: OpName %[[#maxCommonResV:]] "maxCommonResV"
-; CHECK: OpDecorate %[[#subRes]] FPFastMathMode NotNaN
-; CHECK: OpDecorate %[[#mulRes]] FPFastMathMode NotInf
-; CHECK: OpDecorate %[[#divRes]] FPFastMathMode NSZ
-; CHECK: OpDecorate %[[#remRes]] FPFastMathMode AllowRecip
-; CHECK: OpDecorate %[[#negRes]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#oeqRes]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#oltRes]] FPFastMathMode NotNaN
-; CHECK: OpDecorate %[[#ogtRes]] FPFastMathMode NotInf
-; CHECK: OpDecorate %[[#oleRes]] FPFastMathMode NSZ
-; CHECK: OpDecorate %[[#ogeRes]] FPFastMathMode AllowRecip
-; CHECK: OpDecorate %[[#ordRes]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#ueqRes]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#maxRes]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#maxCommonRes]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#subResV]] FPFastMathMode NotNaN
-; CHECK: OpDecorate %[[#mulResV]] FPFastMathMode NotInf
-; CHECK: OpDecorate %[[#divResV]] FPFastMathMode NSZ
-; CHECK: OpDecorate %[[#remResV]] FPFastMathMode AllowRecip
-; CHECK: OpDecorate %[[#negResV]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#oeqResV]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#oltResV]] FPFastMathMode NotNaN
-; CHECK: OpDecorate %[[#ogtResV]] FPFastMathMode NotInf
-; CHECK: OpDecorate %[[#oleResV]] FPFastMathMode NSZ
-; CHECK: OpDecorate %[[#ogeResV]] FPFastMathMode AllowRecip
-; CHECK: OpDecorate %[[#ordResV]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#ueqResV]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#maxResV]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#maxCommonResV]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#subRes:]] FPFastMathMode NotNaN
+; CHECK: OpDecorate %[[#mulRes:]] FPFastMathMode NotInf
+; CHECK: OpDecorate %[[#divRes:]] FPFastMathMode NSZ
+; CHECK: OpDecorate %[[#remRes:]] FPFastMathMode AllowRecip
+; CHECK: OpDecorate %[[#negRes:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#oeqRes:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#oltRes:]] FPFastMathMode NotNaN
+; CHECK: OpDecorate %[[#ogtRes:]] FPFastMathMode NotInf
+; CHECK: OpDecorate %[[#oleRes:]] FPFastMathMode NSZ
+; CHECK: OpDecorate %[[#ogeRes:]] FPFastMathMode AllowRecip
+; CHECK: OpDecorate %[[#ordRes:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#ueqRes:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#maxRes:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#maxCommonRes:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#subResV:]] FPFastMathMode NotNaN
+; CHECK: OpDecorate %[[#mulResV:]] FPFastMathMode NotInf
+; CHECK: OpDecorate %[[#divResV:]] FPFastMathMode NSZ
+; CHECK: OpDecorate %[[#remResV:]] FPFastMathMode AllowRecip
+; CHECK: OpDecorate %[[#negResV:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#oeqResV:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#oltResV:]] FPFastMathMode NotNaN
+; CHECK: OpDecorate %[[#ogtResV:]] FPFastMathMode NotInf
+; CHECK: OpDecorate %[[#oleResV:]] FPFastMathMode NSZ
+; CHECK: OpDecorate %[[#ogeResV:]] FPFastMathMode AllowRecip
+; CHECK: OpDecorate %[[#ordResV:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#ueqResV:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#maxResV:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#maxCommonResV:]] FPFastMathMode NotNaN|NotInf
 
 @G_addRes = global float 0.0
 @G_subRes = global float 0.0
@@ -139,101 +93,115 @@ declare dso_local spir_func noundef nofpclass(nan inf) <2 x float> @_Z23__spirv_
 define weak_odr dso_local spir_kernel void @foo(float %1, float %2) {
 entry:
   %addRes = fadd float %1,  %2
-  store float %addRes, float* @G_addRes
+  store volatile float %addRes, float* @G_addRes
+  ; CHECK: %[[#subRes]] = OpFSub
   %subRes = fsub nnan float %1,  %2
-  store float %subRes, float* @G_subRes
+  store volatile float %subRes, float* @G_subRes
+  ; CHECK: %[[#mulRes]] = OpFMul
   %mulRes = fmul ninf float %1,  %2
-  store float %mulRes, float* @G_mulRes
+  store volatile float %mulRes, float* @G_mulRes
+  ; CHECK: %[[#divRes]] = OpFDiv
   %divRes = fdiv nsz float %1,  %2
-  store float %divRes, float* @G_divRes
+  store volatile float %divRes, float* @G_divRes
+  ; CHECK: %[[#remRes]] = OpFRem
   %remRes = frem arcp float %1,  %2
-  store float %remRes, float* @G_remRes
+  store volatile float %remRes, float* @G_remRes
+  ; CHECK: %[[#negRes]] = OpFNegate
   %negRes = fneg fast float %1
-  store float %negRes, float* @G_negRes
+  store volatile float %negRes, float* @G_negRes
+  ; CHECK: %[[#oeqRes]] = OpFOrdEqual
   %oeqRes = fcmp nnan ninf oeq float %1,  %2
-  store i1 %oeqRes, i1* @G_oeqRes
+  store volatile i1 %oeqRes, i1* @G_oeqRes
   %oneRes = fcmp one float %1,  %2, !spirv.Decorations !3
-  store i1 %oneRes, i1* @G_oneRes
+  store volatile i1 %oneRes, i1* @G_oneRes
+  ; CHECK: %[[#oltRes]] = OpFOrdLessThan
   %oltRes = fcmp nnan olt float %1,  %2, !spirv.Decorations !3
-  store i1 %oltRes, i1* @G_oltRes
+  store volatile i1 %oltRes, i1* @G_oltRes
+  ; CHECK: %[[#ogtRes]] = OpFOrdGreaterThan
   %ogtRes = fcmp ninf ogt float %1,  %2, !spirv.Decorations !3
-  store i1 %ogtRes, i1* @G_ogtRes
+  store volatile i1 %ogtRes, i1* @G_ogtRes
+  ; CHECK: %[[#oleRes]] = OpFOrdLessThanEqual
   %oleRes = fcmp nsz ole float %1,  %2, !spirv.Decorations !3
-  store i1 %oleRes, i1* @G_oleRes
+  store volatile i1 %oleRes, i1* @G_oleRes
+  ; CHECK: %[[#ogeRes]] = OpFOrdGreaterThanEqual
   %ogeRes = fcmp arcp oge float %1,  %2, !spirv.Decorations !3
-  store i1 %ogeRes, i1* @G_ogeRes
+  store volatile i1 %ogeRes, i1* @G_ogeRes
+  ; CHECK: %[[#ordRes]] = OpOrdered
   %ordRes = fcmp fast ord float %1,  %2, !spirv.Decorations !3
-  store i1 %ordRes, i1* @G_ordRes
+  store volatile i1 %ordRes, i1* @G_ordRes
+  ; CHECK: %[[#ueqRes]] = OpFUnordEqual
   %ueqRes = fcmp nnan ninf ueq float %1,  %2, !spirv.Decorations !3
-  store i1 %ueqRes, i1* @G_ueqRes
+  store volatile i1 %ueqRes, i1* @G_ueqRes
   %uneRes = fcmp une float %1,  %2, !spirv.Decorations !3
-  store i1 %uneRes, i1* @G_uneRes
+  store volatile i1 %uneRes, i1* @G_uneRes
   %ultRes = fcmp ult float %1,  %2, !spirv.Decorations !3
-  store i1 %ultRes, i1* @G_ultRes
+  store volatile i1 %ultRes, i1* @G_ultRes
   %ugtRes = fcmp ugt float %1,  %2, !spirv.Decorations !3
-  store i1 %ugtRes, i1* @G_ugtRes
+  store volatile i1 %ugtRes, i1* @G_ugtRes
   %uleRes = fcmp ule float %1,  %2, !spirv.Decorations !3
-  store i1 %uleRes, i1* @G_uleRes
+  store volatile i1 %uleRes, i1* @G_uleRes
   %ugeRes = fcmp uge float %1,  %2, !spirv.Decorations !3
-  store i1 %ugeRes, i1* @G_ugeRes
+  store volatile i1 %ugeRes, i1* @G_ugeRes
   %unoRes = fcmp uno float %1,  %2, !spirv.Decorations !3
-  store i1 %unoRes, i1* @G_unoRes
+  store volatile i1 %unoRes, i1* @G_unoRes
   %modRes = call spir_func float @_Z4fmodff(float %1, float %2)
-  store float %modRes, float* @G_modRes
+  store volatile float %modRes, float* @G_modRes
+  ; CHECK: %[[#maxRes]] = OpExtInst %[[#]] %[[#]] fmax
   %maxRes = tail call fast spir_func noundef nofpclass(nan inf) float @_Z16__spirv_ocl_fmaxff(float noundef nofpclass(nan inf) %1, float noundef nofpclass(nan inf) %2)
-  store float %maxRes, float* @G_maxRes
+  store volatile float %maxRes, float* @G_maxRes
+   ; CHECK: %[[#maxCommonRes]] = OpExtInst %[[#]] %[[#]] fmax
    %maxCommonRes = tail call spir_func noundef float @_Z23__spirv_ocl_fmax_commonff(float noundef nofpclass(nan inf) %1, float noundef nofpclass(nan inf) %2)
-  store float %maxCommonRes, float* @G_maxCommonRes
+  store volatile float %maxCommonRes, float* @G_maxCommonRes
   ret void
 }
 
 define weak_odr dso_local spir_kernel void @fooV(<2 x float> %v1, <2 x float> %v2) {
   %addResV = fadd <2 x float> %v1,  %v2
-  store <2 x float> %addResV, <2 x float>* @G_addResV
+  store volatile <2 x float> %addResV, <2 x float>* @G_addResV
   %subResV = fsub nnan <2 x float> %v1,  %v2
-  store <2 x float> %subResV, <2 x float>* @G_subResV
+  store volatile <2 x float> %subResV, <2 x float>* @G_subResV
   %mulResV = fmul ninf <2 x float> %v1,  %v2
-  store <2 x float> %mulResV, <2 x float>* @G_mulResV
+  store volatile <2 x float> %mulResV, <2 x float>* @G_mulResV
   %divResV = fdiv nsz <2 x float> %v1,  %v2
-  store <2 x float> %divResV, <2 x float>* @G_divResV
+  store volatile <2 x float> %divResV, <2 x float>* @G_divResV
   %remResV = frem arcp <2 x float> %v1,  %v2
-  store <2 x float> %remResV, <2 x float>* @G_remResV
+  store volatile <2 x float> %remResV, <2 x float>* @G_remResV
   %negResV = fneg fast <2 x float> %v1
-  store <2 x float> %negResV, <2 x float>* @G_negResV
+  store volatile <2 x float> %negResV, <2 x float>* @G_negResV
   %oeqResV = fcmp nnan ninf oeq <2 x float> %v1,  %v2
-  store <2 x i1> %oeqResV, <2 x i1>* @G_oeqResV
+  store volatile <2 x i1> %oeqResV, <2 x i1>* @G_oeqResV
   %oneResV = fcmp one <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %oneResV, <2 x i1>* @G_oneResV
+  store volatile <2 x i1> %oneResV, <2 x i1>* @G_oneResV
   %oltResV = fcmp nnan olt <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %oltResV, <2 x i1>* @G_oltResV
+  store volatile <2 x i1> %oltResV, <2 x i1>* @G_oltResV
   %ogtResV = fcmp ninf ogt <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %ogtResV, <2 x i1>* @G_ogtResV
+  store volatile <2 x i1> %ogtResV, <2 x i1>* @G_ogtResV
   %oleResV = fcmp nsz ole <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %oleResV, <2 x i1>* @G_oleResV
+  store volatile <2 x i1> %oleResV, <2 x i1>* @G_oleResV
   %ogeResV = fcmp arcp oge <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %ogeResV, <2 x i1>* @G_ogeResV
+  store volatile <2 x i1> %ogeResV, <2 x i1>* @G_ogeResV
   %ordResV = fcmp fast ord <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %ordResV, <2 x i1>* @G_ordResV
+  store volatile <2 x i1> %ordResV, <2 x i1>* @G_ordResV
   %ueqResV = fcmp nnan ninf ueq <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %ueqResV, <2 x i1>* @G_ueqResV
+  store volatile <2 x i1> %ueqResV, <2 x i1>* @G_ueqResV
   %uneResV = fcmp une <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %uneResV, <2 x i1>* @G_uneResV
+  store volatile <2 x i1> %uneResV, <2 x i1>* @G_uneResV
   %ultResV = fcmp ult <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %ultResV, <2 x i1>* @G_ultResV
+  store volatile <2 x i1> %ultResV, <2 x i1>* @G_ultResV
   %ugtResV = fcmp ugt <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %ugtResV, <2 x i1>* @G_ugtResV
+  store volatile <2 x i1> %ugtResV, <2 x i1>* @G_ugtResV
   %uleResV = fcmp ule <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %uleResV, <2 x i1>* @G_uleResV
+  store volatile <2 x i1> %uleResV, <2 x i1>* @G_uleResV
   %ugeResV = fcmp uge <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %ugeResV, <2 x i1>* @G_ugeResV
+  store volatile <2 x i1> %ugeResV, <2 x i1>* @G_ugeResV
   %unoResV = fcmp uno <2 x float> %v1,  %v2, !spirv.Decorations !3
-  store <2 x i1> %unoResV, <2 x i1>* @G_unoResV
+  store volatile <2 x i1> %unoResV, <2 x i1>* @G_unoResV
   %modResV = call spir_func <2 x float> @_Z4fmodDv2_fDv2_f(<2 x float> %v1, <2 x float> %v2)
-  store <2 x float> %modResV, <2 x float>* @G_modResV
+  store volatile <2 x float> %modResV, <2 x float>* @G_modResV
   %maxResV = tail call fast spir_func noundef nofpclass(nan inf) <2 x float> @_Z16__spirv_ocl_fmaxDv2_fDv2_f(<2 x float> noundef nofpclass(nan inf) %v1, <2 x float> noundef nofpclass(nan inf) %v2)
-  store <2 x float> %maxResV, <2 x float>* @G_maxResV
+  store volatile <2 x float> %maxResV, <2 x float>* @G_maxResV
    %maxCommonResV = tail call spir_func noundef <2 x float> @_Z23__spirv_ocl_fmax_commonDv2_fDv2_f(<2 x float> noundef nofpclass(nan inf) %v1, <2 x float> noundef nofpclass(nan inf) %v2)
-  store <2 x float> %maxCommonResV, <2 x float>* @G_maxCommonResV
+  store volatile <2 x float> %maxCommonResV, <2 x float>* @G_maxCommonResV
   ret void
 }
 
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/disabled-on-amd.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/disabled-on-amd.ll
index 879aab4de4808..8619ee9881300 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/disabled-on-amd.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/disabled-on-amd.ll
@@ -14,9 +14,10 @@
 ; CHECK: SPV_KHR_float_controls2
 ; CHECK-AMD-NOT: SPV_KHR_float_controls2
 
-define spir_kernel void @foo(float %a, float %b) {
+define spir_kernel void @foo(float %a, float %b, float addrspace(1)* %out) {
 entry:
   ; Use contract to trigger a use of SPV_KHR_float_controls2
   %r1 = fadd contract float %a, %b
+  store volatile float %r1, float addrspace(1)* %out
   ret void
 }
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/exec_mode3.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/exec_mode3.ll
index 1d09187b7f6a1..9cc9870c2cfe1 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/exec_mode3.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/exec_mode3.ll
@@ -19,8 +19,8 @@
 ; CHECK-DAG: OpExecutionModeId %[[#KERNEL_FLOAT_V]] FPFastMathDefault %[[#FLOAT_TYPE:]] %[[#CONST131079]]
 ; CHECK-DAG: OpExecutionModeId %[[#KERNEL_ALL_V]] FPFastMathDefault %[[#FLOAT_TYPE:]] %[[#CONST131079]]
 ; We expect 0 for the rest of types because it's SignedZeroInfNanPreserve.
-; CHECK-DAG: OpExecutionModeId %[[#KERNEL_ALL_V]] FPFastMathDefault %[[#HALF_TYPE:]] %[[#CONST0]]
 ; CHECK-DAG: OpExecutionModeId %[[#KERNEL_ALL_V]] FPFastMathDefault %[[#DOUBLE_TYPE:]] %[[#CONST0]]
+; CHECK-DAG: OpExecutionModeId %[[#KERNEL_ALL_V]] FPFastMathDefault %[[#HALF_TYPE:]] %[[#CONST0]]
 
 ; CHECK-DAG: OpDecorate %[[#addRes:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowReassoc
 ; CHECK-DAG: OpDecorate %[[#addResH:]] FPFastMathMode None
@@ -42,10 +42,20 @@
 ; CHECK-DAG: %[[#FLOAT_V_TYPE:]] = OpTypeVector %[[#FLOAT_TYPE]]
 ; CHECK-DAG: %[[#DOUBLE_V_TYPE:]] = OpTypeVector %[[#DOUBLE_TYPE]]
 
+@G_addRes = global float 0.0
+@G_addResH = global half 0.0
+@G_addResF = global float 0.0
+@G_addResD = global double 0.0
+@G_addResV = global <2 x float> zeroinitializer
+@G_addResH_V = global <2 x half> zeroinitializer
+@G_addResF_V = global <2 x float> zeroinitializer
+@G_addResD_V = global <2 x double> zeroinitializer
+
 define dso_local dllexport spir_kernel void @k_float_controls_float(float %f) {
 entry:
 ; CHECK-DAG: %[[#addRes]] = OpFAdd %[[#FLOAT_TYPE]]
   %addRes = fadd float %f,  %f
+  store volatile float %addRes, ptr @G_addRes
   ret void
 }
 
@@ -55,8 +65,11 @@ entry:
 ; CHECK-DAG: %[[#addResF]] = OpFAdd %[[#FLOAT_TYPE]]
 ; CHECK-DAG: %[[#addResD]] = OpFAdd %[[#DOUBLE_TYPE]]
   %addResH = fadd half %h,  %h
+  store volatile half %addResH, ptr @G_addResH
   %addResF = fadd float %f,  %f
+  store volatile float %addResF, ptr @G_addResF
   %addResD = fadd double %d,  %d
+  store volatile double %addResD, ptr @G_addResD
   ret void
 }
 
@@ -64,6 +77,7 @@ define dso_local dllexport spir_kernel void @k_float_controls_float_v(<2 x float
 entry:
 ; CHECK-DAG: %[[#addRes_V]] = OpFAdd %[[#FLOAT_V_TYPE]]
   %addRes = fadd <2 x float> %f,  %f
+  store volatile <2 x float> %addRes, ptr @G_addResV
   ret void
 }
 
@@ -73,8 +87,11 @@ entry:
 ; CHECK-DAG: %[[#addResF_V]] = OpFAdd %[[#FLOAT_V_TYPE]]
 ; CHECK-DAG: %[[#addResD_V]] = OpFAdd %[[#DOUBLE_V_TYPE]]
   %addResH = fadd <2 x half> %h,  %h
+  store volatile <2 x half> %addResH, ptr @G_addResH_V
   %addResF = fadd <2 x float> %f,  %f
+  store volatile <2 x float> %addResF, ptr @G_addResF_V
   %addResD = fadd <2 x double> %d,  %d
+  store volatile <2 x double> %addResD, ptr @G_addResD_V
   ret void
 }
 
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/replacements.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/replacements.ll
index bba1c93a7e78d..e7929b2f7f3d8 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/replacements.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/replacements.ll
@@ -1,27 +1,19 @@
 ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_float_controls2 %s -o - | FileCheck %s
-; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_float_controls2 %s -o - -filetype=obj | spirv-val %}
+; RUN: %if spirv-tools %{ llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_float_controls2 %s -o - -filetype=obj | spirv-val %}
 
 ;; This test checks that the OpenCL.std instructions fmin_common, fmax_common are replaced with fmin, fmax with NInf and NNaN instead.
 
 ; CHECK-DAG: Capability FloatControls2
 ; CHECK: Extension "SPV_KHR_float_controls2"
 
-; CHECK: OpName %[[#maxRes:]] "maxRes"
-; CHECK: OpName %[[#maxCommonRes:]] "maxCommonRes"
-; CHECK: OpName %[[#minRes:]] "minRes"
-; CHECK: OpName %[[#minCommonRes:]] "minCommonRes"
-; CHECK: OpName %[[#maxResV:]] "maxResV"
-; CHECK: OpName %[[#maxCommonResV:]] "maxCommonResV"
-; CHECK: OpName %[[#minResV:]] "minResV"
-; CHECK: OpName %[[#minCommonResV:]] "minCommonResV"
-; CHECK: OpDecorate %[[#maxRes]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#maxCommonRes]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#minRes]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#minCommonRes]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#maxResV]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#maxCommonResV]] FPFastMathMode NotNaN|NotInf
-; CHECK: OpDecorate %[[#minResV]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
-; CHECK: OpDecorate %[[#minCommonResV]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#maxRes:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#maxCommonRes:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#minRes:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#minCommonRes:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#maxResV:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#maxCommonResV:]] FPFastMathMode NotNaN|NotInf
+; CHECK: OpDecorate %[[#minResV:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|AllowContract|AllowReassoc|AllowTransform
+; CHECK: OpDecorate %[[#minCommonResV:]] FPFastMathMode NotNaN|NotInf
 ; CHECK: %[[#maxRes]] = OpExtInst {{.*}} fmax
 ; CHECK: %[[#maxCommonRes]] = OpExtInst {{.*}} fmax
 ; CHECK: %[[#minRes]] = OpExtInst {{.*}} fmin
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll
index dac22c0d84c2e..e52a750466d98 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll
@@ -4,18 +4,11 @@
 
 ; CHECK-NOT: DAG-FENCE
 
-; CHECK-DAG: OpName %[[#NO_WRAP_TEST:]] "no_wrap_test"
-; CHECK-DAG: OpName %[[#A:]] "a"
-; CHECK-DAG: OpName %[[#B:]] "b"
-; CHECK-DAG: OpName %[[#C:]] "c"
-; CHECK-DAG: OpName %[[#D:]] "d"
-; CHECK-DAG: OpName %[[#E:]] "e"
-
 ; CHECK-NOT: DAG-FENCE
 
-; CHECK-DAG: OpDecorate %[[#C]] NoUnsignedWrap
-; CHECK-DAG: OpDecorate %[[#D]] NoSignedWrap
-; CHECK-DAG: OpDecorate %[[#E]] NoUnsignedWrap
+; CHECK-DAG: OpDecorate %[[#C:]] NoUnsignedWrap
+; CHECK-DAG: OpDecorate %[[#D:]] NoSignedWrap
+; CHECK-DAG: OpDecorate %[[#E:]] NoUnsignedWrap
 ; CHECK-DAG: OpDecorate %[[#E]] NoSignedWrap
 
 ; CHECK-NOT: DAG-FENCE
@@ -32,9 +25,9 @@ define i32 @no_wrap_test(i32 %a, i32 %b) {
     ret i32 %e
 }
 
-; CHECK:      %[[#NO_WRAP_TEST]] = OpFunction %[[#I32]] None %[[#FN]]
-; CHECK-NEXT: %[[#A]] = OpFunctionParameter %[[#I32]]
-; CHECK-NEXT: %[[#B]] = OpFunctionParameter %[[#I32]]
+; CHECK:      OpFunction %[[#I32]] None %[[#FN]]
+; CHECK-NEXT: %[[#A:]] = OpFunctionParameter %[[#I32]]
+; CHECK-NEXT: %[[#B:]] = OpFunctionParameter %[[#I32]]
 ; CHECK:      OpLabel
 ; CHECK:      %[[#C]] = OpIMul %[[#I32]] %[[#A]] %[[#B]]
 ; CHECK:      %[[#D]] = OpIMul %[[#I32]] %[[#A]] %[[#B]]
diff --git a/llvm/test/CodeGen/SPIRV/freeze.ll b/llvm/test/CodeGen/SPIRV/freeze.ll
index 4f7e7794ed03b..762dcbd803e05 100644
--- a/llvm/test/CodeGen/SPIRV/freeze.ll
+++ b/llvm/test/CodeGen/SPIRV/freeze.ll
@@ -1,27 +1,19 @@
 ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK-DAG: OpName %[[Arg1:.*]] "arg1"
-; CHECK-DAG: OpName %[[Arg2:.*]] "arg2"
-; CHECK-DAG: OpName %[[NotAStaticPoison:.*]] "poison1"
-; CHECK-DAG: OpName %[[NotAStaticPoison]] "nil0"
-; CHECK-DAG: OpName %[[StaticPoisonIntFreeze:.*]] "nil1"
-; CHECK-DAG: OpName %[[StaticPoisonFloatFreeze:.*]] "nil2"
-; CHECK-DAG: OpName %[[Arg1]] "val1"
-; CHECK-DAG: OpName %[[Const100:.*]] "val2"
-; CHECK-DAG: OpName %[[Const100]] "val3"
-; CHECK: OpDecorate
 ; CHECK-DAG: %[[FloatTy:.*]] = OpTypeFloat 32
 ; CHECK-DAG: %[[ShortTy:.*]] = OpTypeInt 16 0
 ; CHECK-DAG: %[[IntTy:.*]] = OpTypeInt 32 0
 ; CHECK-DAG: %[[Undef16:.*]] = OpUndef %[[ShortTy]]
 ; CHECK-DAG: %[[Undef32:.*]] = OpUndef %[[IntTy]]
 ; CHECK-DAG: %[[UndefFloat:.*]] = OpUndef %[[FloatTy]]
-; CHECK-DAG: %[[Const100]] = OpConstant %[[IntTy]] 100
+; CHECK-DAG: %[[Const100:.*]] = OpConstant %[[IntTy]] 100
 
 define spir_func i16 @test_nil0(i16 %arg2) {
 entry:
-; CHECK: %[[NotAStaticPoison]] = OpIAdd %[[ShortTy]] %[[Arg2]] %[[Undef16]]
+; CHECK: %[[Arg2:.*]] = OpFunctionParameter
+; CHECK: %[[NotAStaticPoison:.*]] = OpIAdd %[[ShortTy]] %[[Arg2]] %[[Undef16]]
+; CHECK: OpReturnValue %[[NotAStaticPoison]]
   %poison1 = add i16 %arg2, undef
   %nil0 = freeze i16 %poison1
   ret i16 %nil0
@@ -41,7 +33,7 @@ entry:
 
 define spir_func float @freeze_float(float %arg1) {
 entry:
-; CHECK: %[[Arg1]] = OpFunctionParameter %[[FloatTy]]
+; CHECK: %[[Arg1:.*]] = OpFunctionParameter %[[FloatTy]]
   %val1 = freeze float %arg1
   ret float %val1
 }
diff --git a/llvm/test/CodeGen/SPIRV/instructions/bitwise-i1.ll b/llvm/test/CodeGen/SPIRV/instructions/bitwise-i1.ll
index 8d3657b36454b..792f7b9c194ba 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/bitwise-i1.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/bitwise-i1.ll
@@ -25,17 +25,23 @@
 ; CHECK: OpLogicalOr %[[#Vec2Bool]]
 ; CHECK: OpLogicalNotEqual %[[#Vec2Bool]]
 
-define void @test1(i8 noundef %arg1, i8 noundef %arg2) {
+define void @test1(i8 noundef %arg1, i8 noundef %arg2, i8 addrspace(1)* %out) {
   %cond1 = and i8 %arg1, %arg2
+  store volatile i8 %cond1, i8 addrspace(1)* %out
   %cond2 = or i8 %arg1, %arg2
+  store volatile i8 %cond2, i8 addrspace(1)* %out
   %cond3 = xor i8 %arg1, %arg2
+  store volatile i8 %cond3, i8 addrspace(1)* %out
   ret void
 }
 
-define void @test1v(<2 x i8> noundef %arg1, <2 x i8> noundef %arg2) {
+define void @test1v(<2 x i8> noundef %arg1, <2 x i8> noundef %arg2, <2 x i8> addrspace(1)* %out) {
   %cond1 = and <2 x i8> %arg1, %arg2
+  store volatile <2 x i8> %cond1, <2 x i8> addrspace(1)* %out
   %cond2 = or <2 x i8> %arg1, %arg2
+  store volatile <2 x i8> %cond2, <2 x i8> addrspace(1)* %out
   %cond3 = xor <2 x i8> %arg1, %arg2
+  store volatile <2 x i8> %cond3, <2 x i8> addrspace(1)* %out
   ret void
 }
 
@@ -52,17 +58,23 @@ cleanup:
   ret void
 }
 
-define void @test3(i1 noundef %arg1, i1 noundef %arg2) {
+define void @test3(i1 noundef %arg1, i1 noundef %arg2, i1 addrspace(1)* %out) {
   %cond1 = and i1 %arg1, %arg2
+  store volatile i1 %cond1, i1 addrspace(1)* %out
   %cond2 = or i1 %arg1, %arg2
+  store volatile i1 %cond2, i1 addrspace(1)* %out
   %cond3 = xor i1 %arg1, %arg2
+  store volatile i1 %cond3, i1 addrspace(1)* %out
   ret void
 }
 
-define void @test3v(<2 x i1> noundef %arg1, <2 x i1> noundef %arg2) {
+define void @test3v(<2 x i1> noundef %arg1, <2 x i1> noundef %arg2, <2 x i1> addrspace(1)* %out) {
   %cond1 = and <2 x i1> %arg1, %arg2
+  store volatile <2 x i1> %cond1, <2 x i1> addrspace(1)* %out
   %cond2 = or <2 x i1> %arg1, %arg2
+  store volatile <2 x i1> %cond2, <2 x i1> addrspace(1)* %out
   %cond3 = xor <2 x i1> %arg1, %arg2
+  store volatile <2 x i1> %cond3, <2 x i1> addrspace(1)* %out
   ret void
 }
 
diff --git a/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll b/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
index 5fe2cc883ceb9..52246ca8eaba8 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
@@ -14,12 +14,6 @@
 ; CHECK-DAG: OpName [[ZEXT8_16:%.*]] "u8tou16"
 ; CHECK-DAG: OpName [[ZEXT16_32:%.*]] "u16tou32"
 
-; CHECK-DAG: OpName %[[#R16:]] "r16"
-; CHECK-DAG: OpName %[[#R17:]] "r17"
-; CHECK-DAG: OpName %[[#R18:]] "r18"
-; CHECK-DAG: OpName %[[#R19:]] "r19"
-; CHECK-DAG: OpName %[[#R20:]] "r20"
-
 ; CHECK-DAG: OpName [[TRUNC32_16v4:%.*]] "i32toi16v4"
 ; CHECK-DAG: OpName [[TRUNC32_8v4:%.*]] "i32toi8v4"
 ; CHECK-DAG: OpName [[TRUNC16_8v4:%.*]] "i16toi8v4"
@@ -30,11 +24,13 @@
 ; CHECK-DAG: OpName [[ZEXT8_16v4:%.*]] "u8tou16v4"
 ; CHECK-DAG: OpName [[ZEXT16_32v4:%.*]] "u16tou32v4"
 
-; CHECK-DAG: OpDecorate %[[#R16]] FPRoundingMode RTZ
-; CHECK-DAG: OpDecorate %[[#R17]] FPRoundingMode RTE
-; CHECK-DAG: OpDecorate %[[#R18]] FPRoundingMode RTP
-; CHECK-DAG: OpDecorate %[[#R19]] FPRoundingMode RTN
-; CHECK-DAG: OpDecorate %[[#R20]] SaturatedConversion
+; CHECK-DAG: OpDecorate %[[#R14:]] FPRoundingMode RTZ
+; CHECK-DAG: OpDecorate %[[#R15:]] FPRoundingMode RTZ
+; CHECK-DAG: OpDecorate %[[#R16:]] FPRoundingMode RTZ
+; CHECK-DAG: OpDecorate %[[#R17:]] FPRoundingMode RTE
+; CHECK-DAG: OpDecorate %[[#R18:]] FPRoundingMode RTP
+; CHECK-DAG: OpDecorate %[[#R19:]] FPRoundingMode RTN
+; CHECK-DAG: OpDecorate %[[#R20:]] SaturatedConversion
 
 ; CHECK-DAG: [[F32:%.*]] = OpTypeFloat 32
 ; CHECK-DAG: [[F16:%.*]] = OpTypeFloat 16
@@ -264,35 +260,55 @@ define <4 x i32>  @u16tou32v4(<4 x i16> %a) {
 ; CHECK: %[[#]] = OpConvertUToPtr %[[#]] [[Arg2]]
 ; CHECK: %[[#]] = OpUConvert [[U32v4]] %[[#]]
 ; CHECK: %[[#]] = OpSConvert [[U32v4]] %[[#]]
-; CHECK: %[[#]] = OpConvertUToF [[F32]] %[[#]]
-; CHECK: %[[#]] = OpConvertUToF [[F32]] %[[#]]
+; CHECK: %[[#R14]] = OpConvertUToF [[F32]] %[[#]]
+; CHECK: %[[#R15]] = OpConvertUToF [[F32]] %[[#]]
 ; CHECK: %[[#R16]] = OpFConvert [[F32v2]] %[[#]]
 ; CHECK: %[[#R17]] = OpFConvert [[F32v2]] %[[#]]
 ; CHECK: %[[#R18]] = OpFConvert [[F32v2]] %[[#]]
 ; CHECK: %[[#R19]] = OpFConvert [[F32v2]] %[[#]]
 ; CHECK: %[[#R20]] = OpConvertFToU [[U8]] %[[#]]
 ; CHECK: OpFunctionEnd
-define dso_local spir_kernel void @test_wrappers(ptr addrspace(4) %arg, i64 %arg_ptr, <4 x i8> %arg_v2) {
+define dso_local spir_kernel void @test_wrappers(ptr addrspace(4) %arg, i64 %arg_ptr, <4 x i8> %arg_v2, ptr addrspace(1) %out_i32, ptr addrspace(1) %out_float, ptr addrspace(1) %out_half, ptr addrspace(1) %out_i64, ptr addrspace(1) %out_ptr, ptr addrspace(1) %out_v4i32, ptr addrspace(1) %out_v2f32, ptr addrspace(1) %out_i8) {
   %r1 = call spir_func i32 @__spirv_ConvertFToU(float 0.000000e+00)
+  store volatile i32 %r1, ptr addrspace(1) %out_i32
   %r2 = call spir_func i32 @__spirv_ConvertFToS(float 0.000000e+00)
+  store volatile i32 %r2, ptr addrspace(1) %out_i32
   %r3 = call spir_func float @__spirv_ConvertSToF(i32 1)
+  store volatile float %r3, ptr addrspace(1) %out_float
   %r4 = call spir_func float @__spirv_ConvertUToF(i32 1)
+  store volatile float %r4, ptr addrspace(1) %out_float
   %r5 = call spir_func i32 @__spirv_UConvert(i64 1)
+  store volatile i32 %r5, ptr addrspace(1) %out_i32
   %r6 = call spir_func i32 @__spirv_SConvert(i64 1)
+  store volatile i32 %r6, ptr addrspace(1) %out_i32
   %r7 = call spir_func half @__spirv_FConvert(float 0.000000e+00)
+  store volatile half %r7, ptr addrspace(1) %out_half
   %r8 = call spir_func i64 @__spirv_SatConvertSToU(i64 1)
+  store volatile i64 %r8, ptr addrspace(1) %out_i64
   %r9 = call spir_func i64 @__spirv_SatConvertUToS(i64 1)
+  store volatile i64 %r9, ptr addrspace(1) %out_i64
   %r10 = call spir_func i64 @__spirv_ConvertPtrToU(ptr addrspace(4) %arg)
+  store volatile i64 %r10, ptr addrspace(1) %out_i64
   %r11 = call spir_func ptr addrspace(4) @__spirv_ConvertUToPtr(i64 %arg_ptr)
+  store volatile ptr addrspace(4) %r11, ptr addrspace(1) %out_ptr
   %r12 = call spir_func <4 x i32> @_Z22__spirv_UConvert_Rint2Dv2_a(<4 x i8> %arg_v2)
+  store volatile <4 x i32> %r12, ptr addrspace(1) %out_v4i32
   %r13 = call spir_func <4 x i32> @_Z22__spirv_SConvert_Rint2Dv2_a(<4 x i8> %arg_v2)
+  store volatile <4 x i32> %r13, ptr addrspace(1) %out_v4i32
   %r14 = call spir_func float @_Z30__spirv_ConvertUToF_Rfloat_rtz(i64 %arg_ptr)
+  store volatile float %r14, ptr addrspace(1) %out_float
   %r15 = call spir_func float @__spirv_ConvertUToF_Rfloat_rtz(i64 %arg_ptr)
+  store volatile float %r15, ptr addrspace(1) %out_float
   %r16 = call spir_func <2 x float> @_Z28__spirv_FConvert_Rfloat2_rtzDv2_DF16_(<2 x half> noundef <half 0xH409A, half 0xH439A>)
+  store volatile <2 x float> %r16, ptr addrspace(1) %out_v2f32
   %r17 = call spir_func <2 x float> @_Z28__spirv_FConvert_Rfloat2_rteDv2_DF16_(<2 x half> noundef <half 0xH409A, half 0xH439A>)
+  store volatile <2 x float> %r17, ptr addrspace(1) %out_v2f32
   %r18 = call spir_func <2 x float> @_Z28__spirv_FConvert_Rfloat2_rtpDv2_DF16_(<2 x half> noundef <half 0xH409A, half 0xH439A>)
+  store volatile <2 x float> %r18, ptr addrspace(1) %out_v2f32
   %r19 = call spir_func <2 x float> @_Z28__spirv_FConvert_Rfloat2_rtnDv2_DF16_(<2 x half> noundef <half 0xH409A, half 0xH439A>)
+  store volatile <2 x float> %r19, ptr addrspace(1) %out_v2f32
   %r20 = call spir_func i8 @_Z30__spirv_ConvertFToU_Ruchar_satf(float noundef 42.0)
+  store volatile i8 %r20, ptr addrspace(1) %out_i8
   ret void
 }
 
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll
index 691325251f11d..32a86ed13b4ff 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll
@@ -2,9 +2,7 @@
 
 ; CHECK-SPIRV-NOT: OpCapability ExpectAssumeKHR
 ; CHECK-SPIRV-NOT: OpExtension "SPV_KHR_expect_assume"
-; CHECK-SPIRV:     OpName %[[#COMPARE:]] "cmp"
-; CHECK-SPIRV:     %[[#COMPARE]] = OpINotEqual %[[#]] %[[#]] %[[#]]
-; CHECK-SPIRV-NOT: OpAssumeTrueKHR %[[#COMPARE]]
+; CHECK-SPIRV-NOT: OpAssumeTrueKHR
 
 %class.anon = type { i8 }
 
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
index 8e8e4df8fabc6..14d25ae9b686e 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
@@ -1,27 +1,21 @@
 ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK-DAG: OpName %[[#r1:]] "r1"
-; CHECK-DAG: OpName %[[#r2:]] "r2"
-; CHECK-DAG: OpName %[[#r3:]] "r3"
-; CHECK-DAG: OpName %[[#r4:]] "r4"
-; CHECK-DAG: OpName %[[#r5:]] "r5"
-; CHECK-DAG: OpName %[[#r6:]] "r6"
-
-; CHECK-NOT: OpDecorate %[[#r5]] FPRoundingMode
-; CHECK-NOT: OpDecorate %[[#r6]] FPRoundingMode
+; CHECK-DAG: %[[#r1:]] = OpFAdd %[[#]] %[[#]]
+; CHECK-DAG: %[[#r2:]] = OpFDiv %[[#]] %[[#]]
+; CHECK-DAG: %[[#r3:]] = OpFSub %[[#]] %[[#]]
+; CHECK-DAG: %[[#r4:]] = OpFMul %[[#]] %[[#]]
+; CHECK-DAG: %[[#r5:]] = OpExtInst %[[#]] %[[#]] fma %[[#]] %[[#]] %[[#]]
+; CHECK-DAG: %[[#r6:]] = OpFRem
 
 ; CHECK-DAG: OpDecorate %[[#r1]] FPRoundingMode RTE
 ; CHECK-DAG: OpDecorate %[[#r2]] FPRoundingMode RTZ
 ; CHECK-DAG: OpDecorate %[[#r4]] FPRoundingMode RTN
 ; CHECK-DAG: OpDecorate %[[#r3]] FPRoundingMode RTP
 
-; CHECK: OpFAdd %[[#]] %[[#]]
-; CHECK: OpFDiv %[[#]] %[[#]]
-; CHECK: OpFSub %[[#]] %[[#]]
-; CHECK: OpFMul %[[#]] %[[#]]
-; CHECK: OpExtInst %[[#]] %[[#]] fma %[[#]] %[[#]] %[[#]]
-; CHECK: OpFRem
+; CHECK-NOT: OpDecorate %[[#r5]] FPRoundingMode
+; CHECK-NOT: OpDecorate %[[#r6]] FPRoundingMode
+
 
 @G_r1 = global float 0.0
 @G_r2 = global float 0.0
diff --git a/llvm/test/CodeGen/SPIRV/opencl/vload2.ll b/llvm/test/CodeGen/SPIRV/opencl/vload2.ll
index 1a1b6c484e74f..926c88fc2b632 100644
--- a/llvm/test/CodeGen/SPIRV/opencl/vload2.ll
+++ b/llvm/test/CodeGen/SPIRV/opencl/vload2.ll
@@ -3,12 +3,6 @@
 
 ; CHECK-DAG: %[[#IMPORT:]] = OpExtInstImport "OpenCL.std"
 
-; CHECK-DAG: OpName %[[#CALL1:]] "call1"
-; CHECK-DAG: OpName %[[#CALL2:]] "call2"
-; CHECK-DAG: OpName %[[#CALL3:]] "call3"
-; CHECK-DAG: OpName %[[#CALL4:]] "call4"
-; CHECK-DAG: OpName %[[#CALL5:]] "call5"
-
 ; CHECK-DAG: %[[#INT8:]] = OpTypeInt 8 0
 ; CHECK-DAG: %[[#INT16:]] = OpTypeInt 16 0
 ; CHECK-DAG: %[[#INT32:]] = OpTypeInt 32 0
@@ -27,22 +21,27 @@
 
 ; CHECK: %[[#OFFSET:]] = OpFunctionParameter %[[#INT64]]
 
-define spir_kernel void @test_fn(i64 %offset, ptr addrspace(1) %address) {
+define spir_kernel void @test_fn(i64 %offset, ptr addrspace(1) %address, ptr addrspace(1) %out) {
 ; CHECK-DAG: %[[#CASTorPARAMofPTRI8:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRINT8]]{{.*}}
-; CHECK-DAG: %[[#CALL1]] = OpExtInst %[[#VINT8]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI8]] 2
+; CHECK-DAG: %[[#CALL1:]] = OpExtInst %[[#VINT8]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI8]] 2
   %call1 = call spir_func <2 x i8> @_Z6vload2mPU3AS1Kc(i64 %offset, ptr addrspace(1) %address)
+  store volatile <2 x i8> %call1, ptr addrspace(1) %out
 ; CHECK-DAG: %[[#CASTorPARAMofPTRI16:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRINT16]]{{.*}}
-; CHECK-DAG: %[[#CALL2]] = OpExtInst %[[#VINT16]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI16]] 2
+; CHECK-DAG: %[[#CALL2:]] = OpExtInst %[[#VINT16]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI16]] 2
   %call2 = call spir_func <2 x i16> @_Z6vload2mPU3AS1Ks(i64 %offset, ptr addrspace(1) %address)
+  store volatile <2 x i16> %call2, ptr addrspace(1) %out
 ; CHECK-DAG: %[[#CASTorPARAMofPTRI32:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRINT32]]{{.*}}
-; CHECK-DAG: %[[#CALL3]] = OpExtInst %[[#VINT32]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI32]] 2
+; CHECK-DAG: %[[#CALL3:]] = OpExtInst %[[#VINT32]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI32]] 2
   %call3 = call spir_func <2 x i32> @_Z6vload2mPU3AS1Ki(i64 %offset, ptr addrspace(1) %address)
+  store volatile <2 x i32> %call3, ptr addrspace(1) %out
 ; CHECK-DAG: %[[#CASTorPARAMofPTRI64:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRINT64]]{{.*}}
-; CHECK-DAG: %[[#CALL4]] = OpExtInst %[[#VINT64]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI64]] 2
+; CHECK-DAG: %[[#CALL4:]] = OpExtInst %[[#VINT64]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI64]] 2
   %call4 = call spir_func <2 x i64> @_Z6vload2mPU3AS1Kl(i64 %offset, ptr addrspace(1) %address)
+  store volatile <2 x i64> %call4, ptr addrspace(1) %out
 ; CHECK-DAG: %[[#CASTorPARAMofPTRFLOAT:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRFLOAT]]{{.*}}
-; CHECK-DAG: %[[#CALL5]] = OpExtInst %[[#VFLOAT]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRFLOAT]] 2
+; CHECK-DAG: %[[#CALL5:]] = OpExtInst %[[#VFLOAT]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRFLOAT]] 2
   %call5 = call spir_func <2 x float> @_Z6vload2mPU3AS1Kf(i64 %offset, ptr addrspace(1) %address)
+  store volatile <2 x float> %call5, ptr addrspace(1) %out
   ret void
 }
 
diff --git a/llvm/test/CodeGen/SPIRV/optimizations/add-check-overflow.ll b/llvm/test/CodeGen/SPIRV/optimizations/add-check-overflow.ll
index 2db620dab8801..d257a73aa19d3 100644
--- a/llvm/test/CodeGen/SPIRV/optimizations/add-check-overflow.ll
+++ b/llvm/test/CodeGen/SPIRV/optimizations/add-check-overflow.ll
@@ -16,9 +16,6 @@
 ; RUN: llc -O3 -disable-lsr -mtriple=spirv64-unknown-unknown %s -o - | FileCheck --check-prefix=NOLSR %s
 ; RUN: %if spirv-tools %{ llc -O3 -disable-lsr -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK-DAG: OpName %[[PhiRes:.*]] "lsr.iv"
-; CHECK-DAG: OpName %[[IsOver:.*]] "fl"
-; CHECK-DAG: OpName %[[Val:.*]] "lsr.iv.next"
 ; CHECK-DAG: %[[Int:.*]] = OpTypeInt 32 0
 ; CHECK-DAG: %[[Char:.*]] = OpTypeInt 8 0
 ; CHECK-DAG: %[[PtrChar:.*]] = OpTypePointer Generic %[[Char]]
@@ -33,8 +30,8 @@
 ; CHECK: %[[APlusOne:.*]] = OpIAdd %[[Int]] %[[A]] %[[Const1]]
 ;	CHECK: OpBranch %[[#]]
 ;	CHECK: [[#]] = OpLabel
-;	CHECK: %[[PhiRes]] = OpPhi %[[Int]] %[[Val]] %[[#]] %[[APlusOne]] %[[#]]
-;	CHECK: %[[IsOver]] = OpIEqual %[[Bool]] %[[#]] %[[#]]
+;	CHECK: %[[PhiRes:.*]] = OpPhi %[[Int]] %[[Val:.*]] %[[#]] %[[APlusOne]] %[[#]]
+;	CHECK: %[[IsOver:.*]] = OpIEqual %[[Bool]] %[[#]] %[[#]]
 ;	CHECK: OpBranchConditional %[[IsOver]] %[[#]] %[[#]]
 ;	CHECK: [[#]] = OpLabel
 ;	CHECK: OpStore %[[Ptr]] %[[Const42]] Aligned 1
@@ -43,8 +40,6 @@
 ;	CHECK: [[#]] = OpLabel
 ;	OpReturnValue %[[PhiRes]]
 
-; NOLSR-DAG: OpName %[[Val:.*]] "math"
-; NOLSR-DAG: OpName %[[IsOver:.*]] "ov"
 ; NOLSR-DAG: %[[Int:.*]] = OpTypeInt 32 0
 ; NOLSR-DAG: %[[Char:.*]] = OpTypeInt 8 0
 ; NOLSR-DAG: %[[PtrChar:.*]] = OpTypePointer Generic %[[Char]]
@@ -60,11 +55,11 @@
 ; NOLSR: %[[#]] = OpLabel
 ; NOLSR: OpBranch %[[#]]
 ; NOLSR: %[[#]] = OpLabel
-; NOLSR: %[[PhiRes:.*]] = OpPhi %[[Int]] %[[A]] %[[#]] %[[Val]] %[[#]]
+; NOLSR: %[[PhiRes:.*]] = OpPhi %[[Int]] %[[A]] %[[#]] %[[Val:.*]] %[[#]]
 ; NOLSR: %[[AggRes:.*]] = OpIAddCarry %[[Struct]] %[[PhiRes]] %[[Const1]]
 ; NOLSR: %[[Val]] = OpCompositeExtract %[[Int]] %[[AggRes]] 0
 ; NOLSR: %[[Over:.*]] = OpCompositeExtract %[[Int]] %[[AggRes]] 1
-; NOLSR: %[[IsOver]] = OpINotEqual %[[Bool:.*]] %[[Over]] %[[Zero]]
+; NOLSR: %[[IsOver:.*]] = OpINotEqual %[[Bool:.*]] %[[Over]] %[[Zero]]
 ; NOLSR: OpBranchConditional %[[IsOver]] %[[#]] %[[#]]
 ; NOLSR: OpStore %[[Ptr]] %[[Const42]] Aligned 1
 ; NOLSR: OpBranch %[[#]]
diff --git a/llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll b/llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll
index 6baac7877a4a8..59a0668df445c 100644
--- a/llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll
+++ b/llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll
@@ -9,20 +9,20 @@
 ; Aggregate data are wrapped into @llvm.fake.use(),
 ; and their attributes are packed into a metadata for @llvm.spv.value.md().
 ; CHECK-IR: %[[R1:.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32
-; CHECK-IR: call void @llvm.spv.value.md(metadata !1)
+; CHECK-IR: call void @llvm.spv.value.md(metadata ![[#MD1:]])
 ; CHECK-IR: call void (...) @llvm.fake.use({ i32, i1 } %[[R1]])
 ; CHECK-IR: %math = extractvalue { i32, i1 } %[[R1]], 0
 ; CHECK-IR: %ov = extractvalue { i32, i1 } %[[R1]], 1
 ; Type/Name attributes of the value.
-; CHECK-IR: !1 = !{{[{]}}!2, !""{{[}]}}
+; CHECK-IR: ![[#MD1]] = !{{[{]}}![[#MD2:]], !""{{[}]}}
 ; Origin data type of the value.
-; CHECK-IR: !2 = !{{[{]}}{{[{]}} i32, i1 {{[}]}} poison{{[}]}}
+; CHECK-IR: ![[#MD2]] = !{{[{]}}{{[{]}} i32, i1 {{[}]}} poison{{[}]}}
 
 ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -print-after=irtranslator 2>&1 | FileCheck %s  --check-prefix=CHECK-GMIR
 ; Required info succeeded to get through IRTranslator.
 ; CHECK-GMIR: %[[phires:.*]]:_(s32) = G_PHI
 ; CHECK-GMIR: %[[math:.*]]:id(s32), %[[ov:.*]]:_(s1) = G_UADDO %[[phires]]:_, %[[#]]:_
-; CHECK-GMIR: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.value.md), !1
+; CHECK-GMIR: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.value.md), ![[MD1:]]
 ; CHECK-GMIR: FAKE_USE %[[math]]:id(s32), %[[ov]]:_(s1)
 
 ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -print-after=spirv-prelegalizer 2>&1 | FileCheck %s  --check-prefix=CHECK-PRE
@@ -41,8 +41,6 @@
 ; CHECK-ISEL-DAG: %[[math:.*]]:id = OpCompositeExtract %[[int32]]:type, %[[res]]:iid, 0
 ; CHECK-ISEL-DAG: %[[ov32:.*]]:iid = OpCompositeExtract %[[int32]]:type, %[[res]]:iid, 1
 ; CHECK-ISEL-DAG: %[[ov:.*]]:iid = OpINotEqual %[[bool]]:type, %[[ov32]]:iid, %[[zero32:.*]]:iid
-; CHECK-ISEL-DAG: OpName %[[math]]:id, 1752457581, 0
-; CHECK-ISEL-DAG: OpName %[[ov]]:iid, 30319
 
 define spir_func i32 @foo(i32 %a, ptr addrspace(4) %p) {
 entry:
diff --git a/llvm/test/CodeGen/SPIRV/pointers/phi-chain-types.ll b/llvm/test/CodeGen/SPIRV/pointers/phi-chain-types.ll
index 44134f83cfec3..452e6a1026b74 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/phi-chain-types.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/phi-chain-types.ll
@@ -5,13 +5,7 @@
 ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
 
 ; CHECK-DAG: OpName %[[#Foo:]] "foo"
-; CHECK-DAG: OpName %[[#FooVal1:]] "val1"
-; CHECK-DAG: OpName %[[#FooVal2:]] "val2"
-; CHECK-DAG: OpName %[[#FooVal3:]] "val3"
 ; CHECK-DAG: OpName %[[#Bar:]] "bar"
-; CHECK-DAG: OpName %[[#BarVal1:]] "val1"
-; CHECK-DAG: OpName %[[#BarVal2:]] "val2"
-; CHECK-DAG: OpName %[[#BarVal3:]] "val3"
 
 ; CHECK-DAG: %[[#Short:]] = OpTypeInt 16 0
 ; CHECK-DAG: %[[#ShortGenPtr:]] = OpTypePointer Generic %[[#Short]]
@@ -24,8 +18,8 @@
 ; CHECK: OpFunctionParameter
 ; CHECK: OpFunctionParameter
 ; CHECK: %[[#FooG1:]] = OpPtrCastToGeneric %[[#ShortGenPtr]] %[[#G1]]
-; CHECK: %[[#FooVal2]] = OpPhi %[[#ShortGenPtr]] %[[#FooArgP]] %[[#]] %[[#FooVal3]] %[[#]]
-; CHECK: %[[#FooVal1]] = OpPhi %[[#ShortGenPtr]] %[[#FooG1]] %[[#]] %[[#FooVal2]] %[[#]]
+; CHECK: %[[#FooVal2:]] = OpPhi %[[#ShortGenPtr]] %[[#FooArgP]] %[[#]] %[[#FooVal3:]] %[[#]]
+; CHECK: %[[#FooVal1:]] = OpPhi %[[#ShortGenPtr]] %[[#FooG1]] %[[#]] %[[#FooVal2]] %[[#]]
 ; CHECK: %[[#FooVal3]] = OpLoad %[[#ShortGenPtr]] %[[#]]
 
 ; CHECK: %[[#Bar:]] = OpFunction %[[#]] None %[[#]]
@@ -33,9 +27,9 @@
 ; CHECK: OpFunctionParameter
 ; CHECK: OpFunctionParameter
 ; CHECK: OpFunctionParameter
-; CHECK: %[[#BarVal3]] = OpLoad %[[#ShortGenPtr]] %[[#]]
+; CHECK: %[[#BarVal3:]] = OpLoad %[[#ShortGenPtr]] %[[#]]
 ; CHECK: %[[#BarG1:]] = OpPtrCastToGeneric %[[#ShortGenPtr]] %[[#G1]]
-; CHECK: %[[#BarVal1]] = OpPhi %[[#ShortGenPtr]] %[[#BarG1]] %[[#]] %[[#BarVal2]] %[[#]]
+; CHECK: %[[#BarVal1:]] = OpPhi %[[#ShortGenPtr]] %[[#BarG1]] %[[#]] %[[#BarVal2:]] %[[#]]
 ; CHECK: %[[#BarVal2]] = OpPhi %[[#ShortGenPtr]] %[[#BarArgP]] %[[#]] %[[#BarVal3]] %[[#]]
 
 @G1 = internal addrspace(3) global i16 undef, align 8
diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll
index dbc88cd1a7859..979fe48511972 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll
@@ -3,7 +3,6 @@
 
 ; CHECK-SPIRV-DAG: OpName %[[ArgCum:.*]] "_arg_cum"
 ; CHECK-SPIRV-DAG: OpName %[[FunTest:.*]] "test"
-; CHECK-SPIRV-DAG: OpName %[[Addr:.*]] "addr"
 ; CHECK-SPIRV-DAG: OpName %[[StubObj:.*]] "stub_object"
 ; CHECK-SPIRV-DAG: OpName %[[MemOrder:.*]] "mem_order"
 ; CHECK-SPIRV-DAG: OpName %[[FooStub:.*]] "foo_stub"
@@ -24,7 +23,7 @@
 ; CHECK-SPIRV: %[[FunTest]] = OpFunction %[[TyVoid]] None %[[TyFunPtrLong]]
 ; CHECK-SPIRV: %[[ArgCum]] = OpFunctionParameter %[[TyPtrLong]]
 
-; CHECK-SPIRV: OpFunctionCall %[[TyVoid]] %[[FooFunc]] %[[Addr]] %[[Const3]]
+; CHECK-SPIRV: OpFunctionCall %[[TyVoid]] %[[FooFunc]] %[[Addr:.*]] %[[Const3]]
 
 ; CHECK-SPIRV: %[[HalfAddr:.*]] = OpPtrCastToGeneric
 ; CHECK-SPIRV-NEXT: %[[HalfAddrCasted:.*]] = OpBitcast %[[TyGenPtrLong]] %[[HalfAddr]]
diff --git a/llvm/test/CodeGen/SPIRV/select-builtin.ll b/llvm/test/CodeGen/SPIRV/select-builtin.ll
index 6717970d160fc..b4601d33dd38f 100644
--- a/llvm/test/CodeGen/SPIRV/select-builtin.ll
+++ b/llvm/test/CodeGen/SPIRV/select-builtin.ll
@@ -6,10 +6,11 @@
 
 ;; LLVM IR was generated with -cl-std=c++ option
 
-define spir_kernel void @test(i32 %op1, i32 %op2) {
+define spir_kernel void @test(i32 %op1, i32 %op2, i32 addrspace(1)* %out) {
 entry:
   %0 = trunc i8 undef to i1
   %call = call spir_func i32 @_Z14__spirv_Selectbii(i1 zeroext %0, i32 %op1, i32 %op2)
+  store i32 %call, i32 addrspace(1)* %out
   ret void
 }
 
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpDot.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpDot.ll
index 58fcc3688c89d..c761e7729d25e 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/OpDot.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpDot.ll
@@ -14,9 +14,10 @@
 ; CHECK-SPIRV-NOT:   %[[#]] = OpDot %[[#]] %[[#]] %[[#]]
 ; CHECK-SPIRV:       OpFunctionEnd
 
-define spir_kernel void @testScalar(float %f) {
+define spir_kernel void @testScalar(float %f, float addrspace(1)* %out) {
 entry:
   %call = tail call spir_func float @_Z3dotff(float %f, float %f)
+  store float %call, float addrspace(1)* %out
   ret void
 }
 
@@ -28,11 +29,14 @@ entry:
 ; CHECK-SPIRV:       %[[#]] = OpDot %[[#TyHalf]] %[[#]] %[[#]]
 ; CHECK-SPIRV:       OpFunctionEnd
 
-define spir_kernel void @testVector(<2 x float> %f, <2 x half> %h) {
+define spir_kernel void @testVector(<2 x float> %f, <2 x half> %h, float addrspace(1)* %out, half addrspace(1)* %outh) {
 entry:
   %call = tail call spir_func float @_Z3dotDv2_fS_(<2 x float> %f, <2 x float> %f)
+  store float %call, float addrspace(1)* %out
   %call2 = tail call spir_func float @__spirv_Dot(<2 x float> %f, <2 x float> %f)
+  store float %call2, float addrspace(1)* %out
   %call3 = tail call spir_func half @_Z11__spirv_DotDv2_DF16_S_(<2 x half> %h, <2 x half> %h)
+  store half %call3, half addrspace(1)* %outh
   ret void
 }
 
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll
index 03731b6d67565..ef92c4418d21d 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll
@@ -5,12 +5,11 @@
 
 ; CHECK-SPIRV: OpName %[[#vec:]] "vec"
 ; CHECK-SPIRV: OpName %[[#index:]] "index"
-; CHECK-SPIRV: OpName %[[#res:]] "res"
 
 ; CHECK-SPIRV: %[[#float:]] = OpTypeFloat 32
 ; CHECK-SPIRV: %[[#float2:]] = OpTypeVector %[[#float]] 2
 
-; CHECK-SPIRV: %[[#res]] = OpVectorExtractDynamic %[[#float]] %[[#vec]] %[[#index]]
+; CHECK-SPIRV: %[[#res:]] = OpVectorExtractDynamic %[[#float]] %[[#vec]] %[[#index]]
 
 define spir_kernel void @test(float addrspace(1)* nocapture %out, <2 x float> %vec, i32 %index) {
 entry:
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
index c939f827e2bba..76f990ed6806a 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
@@ -4,9 +4,6 @@
 ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK:     OpName %[[#v:]] "v"
-; CHECK:     OpName %[[#index:]] "index"
-; CHECK:     OpName %[[#res:]] "res"
 ; CHECK-DAG: %[[#int16:]] = OpTypeInt 16
 ; CHECK-DAG: %[[#int32:]] = OpTypeInt 32
 ; CHECK-DAG: %[[#int16_2:]] = OpTypeVector %[[#int16]] 2
@@ -17,7 +14,7 @@
 ; CHECK-NOT: %[[#idx2:]] = OpConstant %[[#int32]] 1{{$}}
 ; CHECK:     %[[#vec1:]] = OpCompositeInsert %[[#int16_2]] %[[#const1]] %[[#undef]] 0
 ; CHECK:     %[[#vec2:]] = OpCompositeInsert %[[#int16_2]] %[[#const2]] %[[#vec1]] 1
-; CHECK:     %[[#res]] = OpVectorInsertDynamic %[[#int16_2]] %[[#vec2]] %[[#v]] %[[#index]]
+; CHECK:     %[[#res:]] = OpVectorInsertDynamic %[[#int16_2]] %[[#vec2]] %[[#v:]] %[[#index:]]
 
 define spir_kernel void @test(<2 x i16>* nocapture %out, i16 %v, i32 %index) {
 entry:
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll b/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
index d84fd492a86a8..ff73eb4c2eb5d 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
@@ -1,64 +1,65 @@
 ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK-SPIRV:     OpName %[[#r1:]] "r1"
-; CHECK-SPIRV:     OpName %[[#r2:]] "r2"
-; CHECK-SPIRV:     OpName %[[#r3:]] "r3"
-; CHECK-SPIRV:     OpName %[[#r4:]] "r4"
-; CHECK-SPIRV:     OpName %[[#r5:]] "r5"
-; CHECK-SPIRV:     OpName %[[#r6:]] "r6"
-; CHECK-SPIRV:     OpName %[[#r7:]] "r7"
-; CHECK-SPIRV:     OpName %[[#r1d:]] "r1"
-; CHECK-SPIRV:     OpName %[[#r2d:]] "r2"
-; CHECK-SPIRV:     OpName %[[#r3d:]] "r3"
-; CHECK-SPIRV:     OpName %[[#r4d:]] "r4"
-; CHECK-SPIRV:     OpName %[[#r5d:]] "r5"
-; CHECK-SPIRV:     OpName %[[#r6d:]] "r6"
-; CHECK-SPIRV:     OpName %[[#r7d:]] "r7"
-; CHECK-SPIRV-NOT: OpDecorate %[[#r1]] FPFastMathMode
-; CHECK-SPIRV-DAG: OpDecorate %[[#r2]] FPFastMathMode NotNaN
-; CHECK-SPIRV-DAG: OpDecorate %[[#r3]] FPFastMathMode NotInf
-; CHECK-SPIRV-DAG: OpDecorate %[[#r4]] FPFastMathMode NSZ
-; CHECK-SPIRV-DAG: OpDecorate %[[#r5]] FPFastMathMode AllowRecip
-; CHECK-SPIRV-DAG: OpDecorate %[[#r6]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|Fast
-; CHECK-SPIRV-DAG: OpDecorate %[[#r7]] FPFastMathMode NotNaN|NotInf
+; CHECK-SPIRV-NOT: OpDecorate %[[#]] FPFastMathMode
+; CHECK-SPIRV-DAG: OpDecorate %[[#r2:]] FPFastMathMode NotNaN
+; CHECK-SPIRV-DAG: OpDecorate %[[#r3:]] FPFastMathMode NotInf
+; CHECK-SPIRV-DAG: OpDecorate %[[#r4:]] FPFastMathMode NSZ
+; CHECK-SPIRV-DAG: OpDecorate %[[#r5:]] FPFastMathMode AllowRecip
+; CHECK-SPIRV-DAG: OpDecorate %[[#r6:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|Fast
+; CHECK-SPIRV-DAG: OpDecorate %[[#r7:]] FPFastMathMode NotNaN|NotInf
 ; CHECK-SPIRV-DAG: %[[#float:]] = OpTypeFloat 32
 ; CHECK-SPIRV-DAG: %[[#double:]] = OpTypeFloat 64
 
-; CHECK-SPIRV:     %[[#r1]] = OpFAdd %[[#float]]
+; CHECK-SPIRV:     %[[#r1:]] = OpFAdd %[[#float]]
 ; CHECK-SPIRV:     %[[#r2]] = OpFAdd %[[#float]]
 ; CHECK-SPIRV:     %[[#r3]] = OpFAdd %[[#float]]
 ; CHECK-SPIRV:     %[[#r4]] = OpFAdd %[[#float]]
 ; CHECK-SPIRV:     %[[#r5]] = OpFAdd %[[#float]]
 ; CHECK-SPIRV:     %[[#r6]] = OpFAdd %[[#float]]
 ; CHECK-SPIRV:     %[[#r7]] = OpFAdd %[[#float]]
-define spir_kernel void @testFAdd_float(float %a, float %b) {
+define spir_kernel void @testFAdd_float(float %a, float %b, ptr addrspace(1) %out) {
 entry:
   %r1 = fadd float %a, %b
+  store volatile float %r1, float addrspace(1)* %out
   %r2 = fadd nnan float %a, %b
+  store volatile float %r2, float addrspace(1)* %out
   %r3 = fadd ninf float %a, %b
+  store volatile float %r3, float addrspace(1)* %out
   %r4 = fadd nsz float %a, %b
+  store volatile float %r4, float addrspace(1)* %out
   %r5 = fadd arcp float %a, %b
+  store volatile float %r5, float addrspace(1)* %out
   %r6 = fadd fast float %a, %b
+  store volatile float %r6, float addrspace(1)* %out
   %r7 = fadd nnan ninf float %a, %b
+  store volatile float %r7, float addrspace(1)* %out
   ret void
 }
 
-; CHECK-SPIRV:     %[[#r1d]] = OpFAdd %[[#double]]
-; CHECK-SPIRV:     %[[#r2d]] = OpFAdd %[[#double]]
-; CHECK-SPIRV:     %[[#r3d]] = OpFAdd %[[#double]]
-; CHECK-SPIRV:     %[[#r4d]] = OpFAdd %[[#double]]
-; CHECK-SPIRV:     %[[#r5d]] = OpFAdd %[[#double]]
-; CHECK-SPIRV:     %[[#r6d]] = OpFAdd %[[#double]]
-; CHECK-SPIRV:     %[[#r7d]] = OpFAdd %[[#double]]
-define spir_kernel void @testFAdd_double(double %a, double %b) {
+; CHECK-SPIRV:     %[[#]] = OpFAdd %[[#double]]
+; CHECK-SPIRV:     %[[#]] = OpFAdd %[[#double]]
+; CHECK-SPIRV:     %[[#]] = OpFAdd %[[#double]]
+; CHECK-SPIRV:     %[[#]] = OpFAdd %[[#double]]
+; CHECK-SPIRV:     %[[#]] = OpFAdd %[[#double]]
+; CHECK-SPIRV:     %[[#]] = OpFAdd %[[#double]]
+; CHECK-SPIRV:     %[[#]] = OpFAdd %[[#double]]
+
+define spir_kernel void @testFAdd_double(double %a, double %b, double addrspace(1)* %out) local_unnamed_addr {
 entry:
-  %r1 = fadd double %a, %b
-  %r2 = fadd nnan double %a, %b
-  %r3 = fadd ninf double %a, %b
-  %r4 = fadd nsz double %a, %b
-  %r5 = fadd arcp double %a, %b
-  %r6 = fadd fast double %a, %b
-  %r7 = fadd nnan ninf double %a, %b
+  %r11 = fadd double %a, %b
+  store volatile double %r11, double addrspace(1)* %out
+  %r12 = fadd nnan double %a, %b
+  store volatile double %r12, double addrspace(1)* %out
+  %r13 = fadd ninf double %a, %b
+  store volatile double %r13, double addrspace(1)* %out
+  %r14 = fadd nsz double %a, %b
+  store volatile double %r14, double addrspace(1)* %out
+  %r15 = fadd arcp double %a, %b
+  store volatile double %r15, double addrspace(1)* %out
+  %r16 = fadd fast double %a, %b
+  store volatile double %r16, double addrspace(1)* %out
+  %r17 = fadd nnan ninf double %a, %b
+  store volatile double %r17, double addrspace(1)* %out
   ret void
 }
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fcmp.ll b/llvm/test/CodeGen/SPIRV/transcoding/fcmp.ll
index c752e278927a9..1423b970b1e08 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/fcmp.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/fcmp.ll
@@ -1,188 +1,98 @@
 ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK-SPIRV: OpName %[[#r1:]] "r1"
-; CHECK-SPIRV: OpName %[[#r2:]] "r2"
-; CHECK-SPIRV: OpName %[[#r3:]] "r3"
-; CHECK-SPIRV: OpName %[[#r4:]] "r4"
-; CHECK-SPIRV: OpName %[[#r5:]] "r5"
-; CHECK-SPIRV: OpName %[[#r6:]] "r6"
-; CHECK-SPIRV: OpName %[[#r7:]] "r7"
-; CHECK-SPIRV: OpName %[[#r8:]] "r8"
-; CHECK-SPIRV: OpName %[[#r9:]] "r9"
-; CHECK-SPIRV: OpName %[[#r10:]] "r10"
-; CHECK-SPIRV: OpName %[[#r11:]] "r11"
-; CHECK-SPIRV: OpName %[[#r12:]] "r12"
-; CHECK-SPIRV: OpName %[[#r13:]] "r13"
-; CHECK-SPIRV: OpName %[[#r14:]] "r14"
-; CHECK-SPIRV: OpName %[[#r15:]] "r15"
-; CHECK-SPIRV: OpName %[[#r16:]] "r16"
-; CHECK-SPIRV: OpName %[[#r17:]] "r17"
-; CHECK-SPIRV: OpName %[[#r18:]] "r18"
-; CHECK-SPIRV: OpName %[[#r19:]] "r19"
-; CHECK-SPIRV: OpName %[[#r20:]] "r20"
-; CHECK-SPIRV: OpName %[[#r21:]] "r21"
-; CHECK-SPIRV: OpName %[[#r22:]] "r22"
-; CHECK-SPIRV: OpName %[[#r23:]] "r23"
-; CHECK-SPIRV: OpName %[[#r24:]] "r24"
-; CHECK-SPIRV: OpName %[[#r25:]] "r25"
-; CHECK-SPIRV: OpName %[[#r26:]] "r26"
-; CHECK-SPIRV: OpName %[[#r27:]] "r27"
-; CHECK-SPIRV: OpName %[[#r28:]] "r28"
-; CHECK-SPIRV: OpName %[[#r29:]] "r29"
-; CHECK-SPIRV: OpName %[[#r30:]] "r30"
-; CHECK-SPIRV: OpName %[[#r31:]] "r31"
-; CHECK-SPIRV: OpName %[[#r32:]] "r32"
-; CHECK-SPIRV: OpName %[[#r33:]] "r33"
-; CHECK-SPIRV: OpName %[[#r34:]] "r34"
-; CHECK-SPIRV: OpName %[[#r35:]] "r35"
-; CHECK-SPIRV: OpName %[[#r36:]] "r36"
-; CHECK-SPIRV: OpName %[[#r37:]] "r37"
-; CHECK-SPIRV: OpName %[[#r38:]] "r38"
-; CHECK-SPIRV: OpName %[[#r39:]] "r39"
-; CHECK-SPIRV: OpName %[[#r40:]] "r40"
-; CHECK-SPIRV: OpName %[[#r41:]] "r41"
-; CHECK-SPIRV: OpName %[[#r42:]] "r42"
-; CHECK-SPIRV: OpName %[[#r43:]] "r43"
-; CHECK-SPIRV: OpName %[[#r44:]] "r44"
-; CHECK-SPIRV: OpName %[[#r45:]] "r45"
-; CHECK-SPIRV: OpName %[[#r46:]] "r46"
-; CHECK-SPIRV: OpName %[[#r47:]] "r47"
-; CHECK-SPIRV: OpName %[[#r48:]] "r48"
-; CHECK-SPIRV: OpName %[[#r49:]] "r49"
-; CHECK-SPIRV: OpName %[[#r50:]] "r50"
-; CHECK-SPIRV: OpName %[[#r51:]] "r51"
-; CHECK-SPIRV: OpName %[[#r52:]] "r52"
-; CHECK-SPIRV: OpName %[[#r53:]] "r53"
-; CHECK-SPIRV: OpName %[[#r54:]] "r54"
-; CHECK-SPIRV: OpName %[[#r55:]] "r55"
-; CHECK-SPIRV: OpName %[[#r56:]] "r56"
-; CHECK-SPIRV: OpName %[[#r57:]] "r57"
-; CHECK-SPIRV: OpName %[[#r58:]] "r58"
-; CHECK-SPIRV: OpName %[[#r59:]] "r59"
-; CHECK-SPIRV: OpName %[[#r60:]] "r60"
-; CHECK-SPIRV: OpName %[[#r61:]] "r61"
-; CHECK-SPIRV: OpName %[[#r62:]] "r62"
-; CHECK-SPIRV: OpName %[[#r63:]] "r63"
-; CHECK-SPIRV: OpName %[[#r64:]] "r64"
-; CHECK-SPIRV: OpName %[[#r65:]] "r65"
-; CHECK-SPIRV: OpName %[[#r66:]] "r66"
-; CHECK-SPIRV: OpName %[[#r67:]] "r67"
-; CHECK-SPIRV: OpName %[[#r68:]] "r68"
-; CHECK-SPIRV: OpName %[[#r69:]] "r69"
-; CHECK-SPIRV: OpName %[[#r70:]] "r70"
-; CHECK-SPIRV: OpName %[[#r71:]] "r71"
-; CHECK-SPIRV: OpName %[[#r72:]] "r72"
-; CHECK-SPIRV: OpName %[[#r73:]] "r73"
-; CHECK-SPIRV: OpName %[[#r74:]] "r74"
-; CHECK-SPIRV: OpName %[[#r75:]] "r75"
-; CHECK-SPIRV: OpName %[[#r76:]] "r76"
-; CHECK-SPIRV: OpName %[[#r77:]] "r77"
-; CHECK-SPIRV: OpName %[[#r78:]] "r78"
-; CHECK-SPIRV: OpName %[[#r79:]] "r79"
-; CHECK-SPIRV: OpName %[[#r80:]] "r80"
-; CHECK-SPIRV: OpName %[[#r81:]] "r81"
-; CHECK-SPIRV: OpName %[[#r82:]] "r82"
-; CHECK-SPIRV: OpName %[[#r83:]] "r83"
-; CHECK-SPIRV: OpName %[[#r84:]] "r84"
-; CHECK-SPIRV: OpName %[[#r85:]] "r85"
-; CHECK-SPIRV: OpName %[[#r86:]] "r86"
-; CHECK-SPIRV: OpName %[[#r87:]] "r87"
-; CHECK-SPIRV: OpName %[[#r88:]] "r88"
-; CHECK-SPIRV: OpName %[[#r89:]] "r89"
-; CHECK-SPIRV: OpName %[[#r90:]] "r90"
 ; CHECK-SPIRV-NOT: OpDecorate %{{.*}} FPFastMathMode
 ; CHECK-SPIRV: %[[#bool:]] = OpTypeBool
-; CHECK-SPIRV: %[[#r1]] = OpFOrdEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r2]] = OpFOrdEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r3]] = OpFOrdEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r4]] = OpFOrdEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r5]] = OpFOrdEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r6]] = OpFOrdEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r7]] = OpFOrdEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r8]] = OpFOrdNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r9]] = OpFOrdNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r10]] = OpFOrdNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r11]] = OpFOrdNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r12]] = OpFOrdNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r13]] = OpFOrdNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r14]] = OpFOrdNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r15]] = OpFOrdLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r16]] = OpFOrdLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r17]] = OpFOrdLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r18]] = OpFOrdLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r19]] = OpFOrdLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r20]] = OpFOrdLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r21]] = OpFOrdLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r22]] = OpFOrdGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r23]] = OpFOrdGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r24]] = OpFOrdGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r25]] = OpFOrdGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r26]] = OpFOrdGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r27]] = OpFOrdGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r28]] = OpFOrdGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r29]] = OpFOrdLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r30]] = OpFOrdLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r31]] = OpFOrdLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r32]] = OpFOrdLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r33]] = OpFOrdLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r34]] = OpFOrdLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r35]] = OpFOrdLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r36]] = OpFOrdGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r37]] = OpFOrdGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r38]] = OpFOrdGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r39]] = OpFOrdGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r40]] = OpFOrdGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r41]] = OpFOrdGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r42]] = OpFOrdGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r43]] = OpOrdered %[[#bool]]
-; CHECK-SPIRV: %[[#r44]] = OpOrdered %[[#bool]]
-; CHECK-SPIRV: %[[#r45]] = OpOrdered %[[#bool]]
-; CHECK-SPIRV: %[[#r46]] = OpFUnordEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r47]] = OpFUnordEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r48]] = OpFUnordEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r49]] = OpFUnordEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r50]] = OpFUnordEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r51]] = OpFUnordEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r52]] = OpFUnordEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r53]] = OpFUnordNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r54]] = OpFUnordNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r55]] = OpFUnordNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r56]] = OpFUnordNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r57]] = OpFUnordNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r58]] = OpFUnordNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r59]] = OpFUnordNotEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r60]] = OpFUnordLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r61]] = OpFUnordLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r62]] = OpFUnordLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r63]] = OpFUnordLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r64]] = OpFUnordLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r65]] = OpFUnordLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r66]] = OpFUnordLessThan %[[#bool]]
-; CHECK-SPIRV: %[[#r67]] = OpFUnordGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r68]] = OpFUnordGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r69]] = OpFUnordGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r70]] = OpFUnordGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r71]] = OpFUnordGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r72]] = OpFUnordGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r73]] = OpFUnordGreaterThan %[[#bool]]
-; CHECK-SPIRV: %[[#r74]] = OpFUnordLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r75]] = OpFUnordLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r76]] = OpFUnordLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r77]] = OpFUnordLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r78]] = OpFUnordLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r79]] = OpFUnordLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r80]] = OpFUnordLessThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r81]] = OpFUnordGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r82]] = OpFUnordGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r83]] = OpFUnordGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r84]] = OpFUnordGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r85]] = OpFUnordGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r86]] = OpFUnordGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r87]] = OpFUnordGreaterThanEqual %[[#bool]]
-; CHECK-SPIRV: %[[#r88]] = OpUnordered %[[#bool]]
-; CHECK-SPIRV: %[[#r89]] = OpUnordered %[[#bool]]
-; CHECK-SPIRV: %[[#r90]] = OpUnordered %[[#bool]]
+; CHECK-SPIRV: %[[#r1:]] = OpFOrdEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r2:]] = OpFOrdEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r3:]] = OpFOrdEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r4:]] = OpFOrdEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r5:]] = OpFOrdEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r6:]] = OpFOrdEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r7:]] = OpFOrdEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r8:]] = OpFOrdNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r9:]] = OpFOrdNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r10:]] = OpFOrdNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r11:]] = OpFOrdNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r12:]] = OpFOrdNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r13:]] = OpFOrdNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r14:]] = OpFOrdNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r15:]] = OpFOrdLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r16:]] = OpFOrdLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r17:]] = OpFOrdLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r18:]] = OpFOrdLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r19:]] = OpFOrdLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r20:]] = OpFOrdLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r21:]] = OpFOrdLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r22:]] = OpFOrdGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r23:]] = OpFOrdGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r24:]] = OpFOrdGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r25:]] = OpFOrdGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r26:]] = OpFOrdGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r27:]] = OpFOrdGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r28:]] = OpFOrdGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r29:]] = OpFOrdLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r30:]] = OpFOrdLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r31:]] = OpFOrdLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r32:]] = OpFOrdLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r33:]] = OpFOrdLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r34:]] = OpFOrdLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r35:]] = OpFOrdLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r36:]] = OpFOrdGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r37:]] = OpFOrdGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r38:]] = OpFOrdGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r39:]] = OpFOrdGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r40:]] = OpFOrdGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r41:]] = OpFOrdGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r42:]] = OpFOrdGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r43:]] = OpOrdered %[[#bool]]
+; CHECK-SPIRV: %[[#r44:]] = OpOrdered %[[#bool]]
+; CHECK-SPIRV: %[[#r45:]] = OpOrdered %[[#bool]]
+; CHECK-SPIRV: %[[#r46:]] = OpFUnordEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r47:]] = OpFUnordEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r48:]] = OpFUnordEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r49:]] = OpFUnordEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r50:]] = OpFUnordEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r51:]] = OpFUnordEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r52:]] = OpFUnordEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r53:]] = OpFUnordNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r54:]] = OpFUnordNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r55:]] = OpFUnordNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r56:]] = OpFUnordNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r57:]] = OpFUnordNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r58:]] = OpFUnordNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r59:]] = OpFUnordNotEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r60:]] = OpFUnordLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r61:]] = OpFUnordLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r62:]] = OpFUnordLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r63:]] = OpFUnordLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r64:]] = OpFUnordLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r65:]] = OpFUnordLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r66:]] = OpFUnordLessThan %[[#bool]]
+; CHECK-SPIRV: %[[#r67:]] = OpFUnordGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r68:]] = OpFUnordGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r69:]] = OpFUnordGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r70:]] = OpFUnordGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r71:]] = OpFUnordGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r72:]] = OpFUnordGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r73:]] = OpFUnordGreaterThan %[[#bool]]
+; CHECK-SPIRV: %[[#r74:]] = OpFUnordLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r75:]] = OpFUnordLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r76:]] = OpFUnordLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r77:]] = OpFUnordLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r78:]] = OpFUnordLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r79:]] = OpFUnordLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r80:]] = OpFUnordLessThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r81:]] = OpFUnordGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r82:]] = OpFUnordGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r83:]] = OpFUnordGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r84:]] = OpFUnordGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r85:]] = OpFUnordGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r86:]] = OpFUnordGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r87:]] = OpFUnordGreaterThanEqual %[[#bool]]
+; CHECK-SPIRV: %[[#r88:]] = OpUnordered %[[#bool]]
+; CHECK-SPIRV: %[[#r89:]] = OpUnordered %[[#bool]]
+; CHECK-SPIRV: %[[#r90:]] = OpUnordered %[[#bool]]
 
 @G = global [90 x i1] zeroinitializer
 
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fdiv.ll b/llvm/test/CodeGen/SPIRV/transcoding/fdiv.ll
index 79b786814c716..1d04abd4d6508 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/fdiv.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/fdiv.ll
@@ -1,22 +1,15 @@
 ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK-SPIRV:     OpName %[[#r1:]] "r1"
-; CHECK-SPIRV:     OpName %[[#r2:]] "r2"
-; CHECK-SPIRV:     OpName %[[#r3:]] "r3"
-; CHECK-SPIRV:     OpName %[[#r4:]] "r4"
-; CHECK-SPIRV:     OpName %[[#r5:]] "r5"
-; CHECK-SPIRV:     OpName %[[#r6:]] "r6"
-; CHECK-SPIRV:     OpName %[[#r7:]] "r7"
-; CHECK-SPIRV-NOT: OpDecorate %[[#r1]] FPFastMathMode
-; CHECK-SPIRV-DAG: OpDecorate %[[#r2]] FPFastMathMode NotNaN
-; CHECK-SPIRV-DAG: OpDecorate %[[#r3]] FPFastMathMode NotInf
-; CHECK-SPIRV-DAG: OpDecorate %[[#r4]] FPFastMathMode NSZ
-; CHECK-SPIRV-DAG: OpDecorate %[[#r5]] FPFastMathMode AllowRecip
-; CHECK-SPIRV-DAG: OpDecorate %[[#r6]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|Fast
-; CHECK-SPIRV-DAG: OpDecorate %[[#r7]] FPFastMathMode NotNaN|NotInf
+; CHECK-SPIRV-NOT: OpDecorate %[[#]] FPFastMathMode
+; CHECK-SPIRV-DAG: OpDecorate %[[#r2:]] FPFastMathMode {{NotNaN(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r3:]] FPFastMathMode {{NotInf(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r4:]] FPFastMathMode {{NSZ(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r5:]] FPFastMathMode {{AllowRecip(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r6:]] FPFastMathMode {{NotNaN\|NotInf\|NSZ\|AllowRecip\|Fast(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r7:]] FPFastMathMode {{NotNaN\|NotInf(\||$)}}
 ; CHECK-SPIRV:     %[[#float:]] = OpTypeFloat 32
-; CHECK-SPIRV:     %[[#r1]] = OpFDiv %[[#float]]
+; CHECK-SPIRV:     %[[#r1:]] = OpFDiv %[[#float]]
 ; CHECK-SPIRV:     %[[#r2]] = OpFDiv %[[#float]]
 ; CHECK-SPIRV:     %[[#r3]] = OpFDiv %[[#float]]
 ; CHECK-SPIRV:     %[[#r4]] = OpFDiv %[[#float]]
@@ -24,14 +17,21 @@
 ; CHECK-SPIRV:     %[[#r6]] = OpFDiv %[[#float]]
 ; CHECK-SPIRV:     %[[#r7]] = OpFDiv %[[#float]]
 
-define spir_kernel void @testFDiv(float %a, float %b) local_unnamed_addr {
+define spir_kernel void @testFDiv(float %a, float %b, float addrspace(1)* %out) local_unnamed_addr {
 entry:
   %r1 = fdiv float %a, %b
+  store volatile float %r1, float addrspace(1)* %out
   %r2 = fdiv nnan float %a, %b
+  store volatile float %r2, float addrspace(1)* %out
   %r3 = fdiv ninf float %a, %b
+  store volatile float %r3, float addrspace(1)* %out
   %r4 = fdiv nsz float %a, %b
+  store volatile float %r4, float addrspace(1)* %out
   %r5 = fdiv arcp float %a, %b
+  store volatile float %r5, float addrspace(1)* %out
   %r6 = fdiv fast float %a, %b
+  store volatile float %r6, float addrspace(1)* %out
   %r7 = fdiv nnan ninf float %a, %b
+  store volatile float %r7, float addrspace(1)* %out
   ret void
 }
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fmul.ll b/llvm/test/CodeGen/SPIRV/transcoding/fmul.ll
index fdab29c9041cb..4745124802d96 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/fmul.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/fmul.ll
@@ -1,22 +1,15 @@
 ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK-SPIRV:     OpName %[[#r1:]] "r1"
-; CHECK-SPIRV:     OpName %[[#r2:]] "r2"
-; CHECK-SPIRV:     OpName %[[#r3:]] "r3"
-; CHECK-SPIRV:     OpName %[[#r4:]] "r4"
-; CHECK-SPIRV:     OpName %[[#r5:]] "r5"
-; CHECK-SPIRV:     OpName %[[#r6:]] "r6"
-; CHECK-SPIRV:     OpName %[[#r7:]] "r7"
-; CHECK-SPIRV-NOT: OpDecorate %[[#r1]] FPFastMathMode
-; CHECK-SPIRV-DAG: OpDecorate %[[#r2]] FPFastMathMode NotNaN
-; CHECK-SPIRV-DAG: OpDecorate %[[#r3]] FPFastMathMode NotInf
-; CHECK-SPIRV-DAG: OpDecorate %[[#r4]] FPFastMathMode NSZ
-; CHECK-SPIRV-DAG: OpDecorate %[[#r5]] FPFastMathMode AllowRecip
-; CHECK-SPIRV-DAG: OpDecorate %[[#r6]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|Fast
-; CHECK-SPIRV-DAG: OpDecorate %[[#r7]] FPFastMathMode NotNaN|NotInf
+; CHECK-SPIRV-NOT: OpDecorate %[[#]] FPFastMathMode
+; CHECK-SPIRV-DAG: OpDecorate %[[#r2:]] FPFastMathMode {{NotNaN(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r3:]] FPFastMathMode {{NotInf(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r4:]] FPFastMathMode {{NSZ(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r5:]] FPFastMathMode {{AllowRecip(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r6:]] FPFastMathMode {{NotNaN\|NotInf\|NSZ\|AllowRecip\|Fast(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r7:]] FPFastMathMode {{NotNaN\|NotInf(\||$)}}
 ; CHECK-SPIRV:     %[[#float:]] = OpTypeFloat 32
-; CHECK-SPIRV:     %[[#r1]] = OpFMul %[[#float]]
+; CHECK-SPIRV:     %[[#r1:]] = OpFMul %[[#float]]
 ; CHECK-SPIRV:     %[[#r2]] = OpFMul %[[#float]]
 ; CHECK-SPIRV:     %[[#r3]] = OpFMul %[[#float]]
 ; CHECK-SPIRV:     %[[#r4]] = OpFMul %[[#float]]
@@ -24,14 +17,21 @@
 ; CHECK-SPIRV:     %[[#r6]] = OpFMul %[[#float]]
 ; CHECK-SPIRV:     %[[#r7]] = OpFMul %[[#float]]
 
-define spir_kernel void @testFMul(float %a, float %b) local_unnamed_addr {
+define spir_kernel void @testFMul(float %a, float %b, float addrspace(1)* %out) local_unnamed_addr {
 entry:
   %r1 = fmul float %a, %b
+  store volatile float %r1, float addrspace(1)* %out
   %r2 = fmul nnan float %a, %b
+  store volatile float %r2, float addrspace(1)* %out
   %r3 = fmul ninf float %a, %b
+  store volatile float %r3, float addrspace(1)* %out
   %r4 = fmul nsz float %a, %b
+  store volatile float %r4, float addrspace(1)* %out
   %r5 = fmul arcp float %a, %b
+  store volatile float %r5, float addrspace(1)* %out
   %r6 = fmul fast float %a, %b
+  store volatile float %r6, float addrspace(1)* %out
   %r7 = fmul nnan ninf float %a, %b
+  store volatile float %r7, float addrspace(1)* %out
   ret void
 }
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fneg.ll b/llvm/test/CodeGen/SPIRV/transcoding/fneg.ll
index 60bbfe6b7f393..21947517694f2 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/fneg.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/fneg.ll
@@ -1,31 +1,31 @@
 ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK-SPIRV: OpName %[[#r1:]] "r1"
-; CHECK-SPIRV: OpName %[[#r2:]] "r2"
-; CHECK-SPIRV: OpName %[[#r3:]] "r3"
-; CHECK-SPIRV: OpName %[[#r4:]] "r4"
-; CHECK-SPIRV: OpName %[[#r5:]] "r5"
-; CHECK-SPIRV: OpName %[[#r6:]] "r6"
-; CHECK-SPIRV: OpName %[[#r7:]] "r7"
 ; CHECK-SPIRV-NOT: OpDecorate %{{.*}} FPFastMathMode
 ; CHECK-SPIRV: %[[#float:]] = OpTypeFloat 32
-; CHECK-SPIRV: %[[#r1]] = OpFNegate %[[#float]]
-; CHECK-SPIRV: %[[#r2]] = OpFNegate %[[#float]]
-; CHECK-SPIRV: %[[#r3]] = OpFNegate %[[#float]]
-; CHECK-SPIRV: %[[#r4]] = OpFNegate %[[#float]]
-; CHECK-SPIRV: %[[#r5]] = OpFNegate %[[#float]]
-; CHECK-SPIRV: %[[#r6]] = OpFNegate %[[#float]]
-; CHECK-SPIRV: %[[#r7]] = OpFNegate %[[#float]]
+; CHECK-SPIRV: %[[#r1:]] = OpFNegate %[[#float]]
+; CHECK-SPIRV: %[[#r2:]] = OpFNegate %[[#float]]
+; CHECK-SPIRV: %[[#r3:]] = OpFNegate %[[#float]]
+; CHECK-SPIRV: %[[#r4:]] = OpFNegate %[[#float]]
+; CHECK-SPIRV: %[[#r5:]] = OpFNegate %[[#float]]
+; CHECK-SPIRV: %[[#r6:]] = OpFNegate %[[#float]]
+; CHECK-SPIRV: %[[#r7:]] = OpFNegate %[[#float]]
 
-define spir_kernel void @testFNeg(float %a) local_unnamed_addr {
+define spir_kernel void @testFNeg(float %a, float addrspace(1)* %out) local_unnamed_addr {
 entry:
   %r1 = fneg float %a
+  store volatile float %r1, float addrspace(1)* %out
   %r2 = fneg nnan float %a
+  store volatile float %r2, float addrspace(1)* %out
   %r3 = fneg ninf float %a
+  store volatile float %r3, float addrspace(1)* %out
   %r4 = fneg nsz float %a
+  store volatile float %r4, float addrspace(1)* %out
   %r5 = fneg arcp float %a
+  store volatile float %r5, float addrspace(1)* %out
   %r6 = fneg fast float %a
+  store volatile float %r6, float addrspace(1)* %out
   %r7 = fneg nnan ninf float %a
+  store volatile float %r7, float addrspace(1)* %out
   ret void
 }
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fp_contract_reassoc_fast_mode.ll b/llvm/test/CodeGen/SPIRV/transcoding/fp_contract_reassoc_fast_mode.ll
index 974043c11991f..307fc1e49ecbc 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/fp_contract_reassoc_fast_mode.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/fp_contract_reassoc_fast_mode.ll
@@ -2,10 +2,8 @@
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
 ; CHECK-SPIRV-NOT: OpCapability FPFastMathModeINTEL
-; CHECK-SPIRV:     OpName %[[#mu:]] "mul"
-; CHECK-SPIRV:     OpName %[[#su:]] "sub"
-; CHECK-SPIRV-NOT: OpDecorate %[[#mu]] FPFastMathMode AllowContractFastINTEL
-; CHECK-SPIRV-NOT: OpDecorate %[[#su]] FPFastMathMode AllowReassocINTEL
+; CHECK-SPIRV-NOT: OpDecorate %[[#]] FPFastMathMode AllowContractFastINTEL
+; CHECK-SPIRV-NOT: OpDecorate %[[#]] FPFastMathMode AllowReassocINTEL
 
 define spir_kernel void @test(float %a, float %b) {
 entry:
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/frem.ll b/llvm/test/CodeGen/SPIRV/transcoding/frem.ll
index d36ba7f70e453..f07a3a2d6f075 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/frem.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/frem.ll
@@ -1,22 +1,15 @@
 ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK-SPIRV:     OpName %[[#r1:]] "r1"
-; CHECK-SPIRV:     OpName %[[#r2:]] "r2"
-; CHECK-SPIRV:     OpName %[[#r3:]] "r3"
-; CHECK-SPIRV:     OpName %[[#r4:]] "r4"
-; CHECK-SPIRV:     OpName %[[#r5:]] "r5"
-; CHECK-SPIRV:     OpName %[[#r6:]] "r6"
-; CHECK-SPIRV:     OpName %[[#r7:]] "r7"
-; CHECK-SPIRV-NOT: OpDecorate %[[#r1]] FPFastMathMode
-; CHECK-SPIRV-DAG: OpDecorate %[[#r2]] FPFastMathMode NotNaN
-; CHECK-SPIRV-DAG: OpDecorate %[[#r3]] FPFastMathMode NotInf
-; CHECK-SPIRV-DAG: OpDecorate %[[#r4]] FPFastMathMode NSZ
-; CHECK-SPIRV-DAG: OpDecorate %[[#r5]] FPFastMathMode AllowRecip
-; CHECK-SPIRV-DAG: OpDecorate %[[#r6]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|Fast
-; CHECK-SPIRV-DAG: OpDecorate %[[#r7]] FPFastMathMode NotNaN|NotInf
+; CHECK-SPIRV-NOT: OpDecorate %[[#]] FPFastMathMode
+; CHECK-SPIRV-DAG: OpDecorate %[[#r2:]] FPFastMathMode NotNaN{{$}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r3:]] FPFastMathMode NotInf{{$}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r4:]] FPFastMathMode NSZ{{$}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r5:]] FPFastMathMode AllowRecip{{$}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r6:]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|Fast{{$}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r7:]] FPFastMathMode NotNaN|NotInf{{$}}
 ; CHECK-SPIRV:     %[[#float:]] = OpTypeFloat 32
-; CHECK-SPIRV:     %[[#r1]] = OpFRem %[[#float]]
+; CHECK-SPIRV:     %[[#r1:]] = OpFRem %[[#float]]
 ; CHECK-SPIRV:     %[[#r2]] = OpFRem %[[#float]]
 ; CHECK-SPIRV:     %[[#r3]] = OpFRem %[[#float]]
 ; CHECK-SPIRV:     %[[#r4]] = OpFRem %[[#float]]
@@ -24,14 +17,21 @@
 ; CHECK-SPIRV:     %[[#r6]] = OpFRem %[[#float]]
 ; CHECK-SPIRV:     %[[#r7]] = OpFRem %[[#float]]
 
-define spir_kernel void @testFRem(float %a, float %b) local_unnamed_addr {
+define spir_kernel void @testFRem(float %a, float %b, float addrspace(1)* %out) local_unnamed_addr {
 entry:
   %r1 = frem float %a, %b
+  store volatile float %r1, float addrspace(1)* %out
   %r2 = frem nnan float %a, %b
+  store volatile float %r2, float addrspace(1)* %out
   %r3 = frem ninf float %a, %b
+  store volatile float %r3, float addrspace(1)* %out
   %r4 = frem nsz float %a, %b
+  store volatile float %r4, float addrspace(1)* %out
   %r5 = frem arcp float %a, %b
+  store volatile float %r5, float addrspace(1)* %out
   %r6 = frem fast float %a, %b
+  store volatile float %r6, float addrspace(1)* %out
   %r7 = frem nnan ninf float %a, %b
+  store volatile float %r7, float addrspace(1)* %out
   ret void
 }
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fsub.ll b/llvm/test/CodeGen/SPIRV/transcoding/fsub.ll
index 3677c00405626..3f980b1646142 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/fsub.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/fsub.ll
@@ -1,22 +1,16 @@
 ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK-SPIRV:     OpName %[[#r1:]] "r1"
-; CHECK-SPIRV:     OpName %[[#r2:]] "r2"
-; CHECK-SPIRV:     OpName %[[#r3:]] "r3"
-; CHECK-SPIRV:     OpName %[[#r4:]] "r4"
-; CHECK-SPIRV:     OpName %[[#r5:]] "r5"
-; CHECK-SPIRV:     OpName %[[#r6:]] "r6"
-; CHECK-SPIRV:     OpName %[[#r7:]] "r7"
-; CHECK-SPIRV-NOT: OpDecorate %[[#r1]] FPFastMathMode
-; CHECK-SPIRV-DAG: OpDecorate %[[#r2]] FPFastMathMode NotNaN
-; CHECK-SPIRV-DAG: OpDecorate %[[#r3]] FPFastMathMode NotInf
-; CHECK-SPIRV-DAG: OpDecorate %[[#r4]] FPFastMathMode NSZ
-; CHECK-SPIRV-DAG: OpDecorate %[[#r5]] FPFastMathMode AllowRecip
-; CHECK-SPIRV-DAG: OpDecorate %[[#r6]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|Fast
-; CHECK-SPIRV-DAG: OpDecorate %[[#r7]] FPFastMathMode NotNaN|NotInf
+; CHECK-SPIRV-NOT: OpDecorate {{.*}} FPFastMathMode
+; CHECK-SPIRV-DAG: OpDecorate %[[#r2:]] FPFastMathMode {{NotNaN(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r3:]] FPFastMathMode {{NotInf(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r4:]] FPFastMathMode {{NSZ(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r5:]] FPFastMathMode {{AllowRecip(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r6:]] FPFastMathMode {{NotNaN\|NotInf\|NSZ\|AllowRecip\|Fast(\||$)}}
+; CHECK-SPIRV-DAG: OpDecorate %[[#r7:]] FPFastMathMode {{NotNaN\|NotInf(\||$)}}
+; CHECK-SPIRV-NOT: OpDecorate {{.*}} FPFastMathMode
 ; CHECK-SPIRV:     %[[#float:]] = OpTypeFloat 32
-; CHECK-SPIRV:     %[[#r1]] = OpFSub %[[#float]]
+; CHECK-SPIRV:     %[[#r1:]] = OpFSub %[[#float]]
 ; CHECK-SPIRV:     %[[#r2]] = OpFSub %[[#float]]
 ; CHECK-SPIRV:     %[[#r3]] = OpFSub %[[#float]]
 ; CHECK-SPIRV:     %[[#r4]] = OpFSub %[[#float]]
@@ -24,14 +18,21 @@
 ; CHECK-SPIRV:     %[[#r6]] = OpFSub %[[#float]]
 ; CHECK-SPIRV:     %[[#r7]] = OpFSub %[[#float]]
 
-define spir_kernel void @testFSub(float %a, float %b) local_unnamed_addr {
+define spir_kernel void @testFSub(float %a, float %b, float addrspace(1)* %out) local_unnamed_addr {
 entry:
   %r1 = fsub float %a, %b
+  store volatile float %r1, float addrspace(1)* %out
   %r2 = fsub nnan float %a, %b
+  store volatile float %r2, float addrspace(1)* %out
   %r3 = fsub ninf float %a, %b
+  store volatile float %r3, float addrspace(1)* %out
   %r4 = fsub nsz float %a, %b
+  store volatile float %r4, float addrspace(1)* %out
   %r5 = fsub arcp float %a, %b
+  store volatile float %r5, float addrspace(1)* %out
   %r6 = fsub fast float %a, %b
+  store volatile float %r6, float addrspace(1)* %out
   %r7 = fsub nnan ninf float %a, %b
+  store volatile float %r7, float addrspace(1)* %out
   ret void
 }
diff --git a/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll b/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
index 16cd00b7180a7..6b669007f544b 100644
--- a/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
+++ b/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
@@ -12,12 +12,6 @@
 ; XFAIL: expensive_checks
 
 ; CHECK-DAG: OpName %[[#Struct:]] "struct"
-; CHECK-DAG: OpName %[[#Arg:]] "arg"
-; CHECK-DAG: OpName %[[#QArg:]] "qarg"
-; CHECK-DAG: OpName %[[#R:]] "r"
-; CHECK-DAG: OpName %[[#Q:]] "q"
-; CHECK-DAG: OpName %[[#Tr:]] "tr"
-; CHECK-DAG: OpName %[[#Tq:]] "tq"
 ; CHECK-DAG: %[[#Struct]] = OpTypeStruct %[[#]] %[[#]] %[[#]]
 ; CHECK-DAG: %[[#PtrStruct:]] = OpTypePointer CrossWorkgroup %[[#Struct]]
 ; CHECK-EXT-DAG: %[[#Int40:]] = OpTypeInt 40 0
@@ -26,19 +20,21 @@
 ; CHECK-DAG: %[[#PtrInt40:]] = OpTypePointer CrossWorkgroup %[[#Int40]]
 
 ; CHECK: OpFunction
-
-; CHECK-EXT: %[[#Tr]] = OpUConvert %[[#Int40]] %[[#R]]
+; CHECK: %[[#Arg:]] = OpFunctionParameter
+; CHECK-EXT: %[[#Tr:]] = OpUConvert %[[#Int40]] %[[#R:]]
 ; CHECK-EXT: %[[#Store:]] = OpInBoundsPtrAccessChain %[[#PtrStruct]] %[[#Arg]] %[[#]]
 ; CHECK-EXT: %[[#StoreAsInt40:]] = OpBitcast %[[#PtrInt40]] %[[#Store]]
 ; CHECK-EXT: OpStore %[[#StoreAsInt40]] %[[#Tr]]
 
 ; CHECK-NOEXT: %[[#Store:]] = OpInBoundsPtrAccessChain %[[#PtrStruct]] %[[#Arg]] %[[#]]
 ; CHECK-NOEXT: %[[#StoreAsInt40:]] = OpBitcast %[[#PtrInt40]] %[[#Store]]
-; CHECK-NOEXT: OpStore %[[#StoreAsInt40]] %[[#R]]
+; CHECK-NOEXT: OpStore %[[#StoreAsInt40]] %[[#R:]]
 
 ; CHECK: OpFunction
 
-; CHECK-EXT: %[[#Tq]] = OpUConvert %[[#Int40]] %[[#Q]]
+; CHECK: %[[#QArg:]] = OpFunctionParameter
+; CHECK: %[[#Q:]] = OpFunctionParameter
+; CHECK-EXT: %[[#Tq:]] = OpUConvert %[[#Int40]] %[[#Q]]
 ; CHECK-EXT: OpStore %[[#QArg]] %[[#Tq]]
 
 ; CHECK-NOEXT: OpStore %[[#QArg]] %[[#Q]]
diff --git a/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll b/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
index 9c8b4070d834d..aed759ba843c3 100644
--- a/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
+++ b/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
@@ -9,26 +9,6 @@
 ;; clang -x cl -cl-std=CL2.0 -target spir64 -emit-llvm -S -c test.cl
 
 
-; SPV-DAG: OpName %[[#s1:]] "s1"
-; SPV-DAG: OpName %[[#s2:]] "s2"
-; SPV-DAG: OpName %[[#s3:]] "s3"
-; SPV-DAG: OpName %[[#s4:]] "s4"
-; SPV-DAG: OpName %[[#s5:]] "s5"
-; SPV-DAG: OpName %[[#s6:]] "s6"
-; SPV-DAG: OpName %[[#s7:]] "s7"
-; SPV-DAG: OpName %[[#s8:]] "s8"
-; SPV-DAG: OpName %[[#z1:]] "z1"
-; SPV-DAG: OpName %[[#z2:]] "z2"
-; SPV-DAG: OpName %[[#z3:]] "z3"
-; SPV-DAG: OpName %[[#z4:]] "z4"
-; SPV-DAG: OpName %[[#z5:]] "z5"
-; SPV-DAG: OpName %[[#z6:]] "z6"
-; SPV-DAG: OpName %[[#z7:]] "z7"
-; SPV-DAG: OpName %[[#z8:]] "z8"
-; SPV-DAG: OpName %[[#ufp1:]] "ufp1"
-; SPV-DAG: OpName %[[#ufp2:]] "ufp2"
-; SPV-DAG: OpName %[[#sfp1:]] "sfp1"
-; SPV-DAG: OpName %[[#sfp2:]] "sfp2"
 ; SPV-DAG: %[[#int_32:]] = OpTypeInt 32 0
 ; SPV-DAG: %[[#int_8:]] = OpTypeInt 8 0
 ; SPV-DAG: %[[#int_16:]] = OpTypeInt 16 0
@@ -98,76 +78,76 @@
 define dso_local spir_kernel void @K(float addrspace(1)* nocapture %A, i32 %B, i1 %i1s, <2 x i1> %i1v) local_unnamed_addr {
 entry:
 
-; SPV-DAG: %[[#cmp_res:]] = OpSGreaterThan %[[#bool]] %[[#B]] %[[#zero_32]]
+; SPV: %[[#cmp_res:]] = OpSGreaterThan %[[#bool]] %[[#B]] %[[#zero_32]]
   %cmp = icmp sgt i32 %B, 0
-; SPV-DAG: %[[#select_res:]] = OpSelect %[[#int_32]] %[[#cmp_res]] %[[#one_32]] %[[#zero_32]]
-; SPV-DAG: %[[#utof_res:]] = OpConvertUToF %[[#float]] %[[#select_res]]
+; SPV: %[[#select_res:]] = OpSelect %[[#int_32]] %[[#cmp_res]] %[[#one_32]] %[[#zero_32]]
+; SPV: %[[#utof_res:]] = OpConvertUToF %[[#float]] %[[#select_res]]
   %conv = uitofp i1 %cmp to float
-; SPV-DAG: OpStore %[[#A]] %[[#utof_res]]
+; SPV: OpStore %[[#A]] %[[#utof_res]]
   store float %conv, float addrspace(1)* %A, align 4;
 
-; SPV-DAG: %[[#s1]] = OpSelect %[[#int_8]] %[[#i1s]] %[[#mone_8]] %[[#zero_8]]
+; SPV: %[[#s1:]] = OpSelect %[[#int_8]] %[[#i1s]] %[[#mone_8]] %[[#zero_8]]
   %s1 = sext i1 %i1s to i8
   store i8 %s1, ptr @G_s1
-; SPV-DAG: %[[#s2]] = OpSelect %[[#int_16]] %[[#i1s]] %[[#mone_16]] %[[#zero_16]]
+; SPV: %[[#s2:]] = OpSelect %[[#int_16]] %[[#i1s]] %[[#mone_16]] %[[#zero_16]]
   %s2 = sext i1 %i1s to i16
   store i16 %s2, ptr @G_s2
-; SPV-DAG: %[[#s3]] = OpSelect %[[#int_32]] %[[#i1s]] %[[#mone_32]] %[[#zero_32]]
+; SPV: %[[#s3:]] = OpSelect %[[#int_32]] %[[#i1s]] %[[#mone_32]] %[[#zero_32]]
   %s3 = sext i1 %i1s to i32
   store i32 %s3, ptr @G_s3
-; SPV-DAG: %[[#s4]] = OpSelect %[[#int_64]] %[[#i1s]] %[[#mone_64]] %[[#zero_64]]
+; SPV: %[[#s4:]] = OpSelect %[[#int_64]] %[[#i1s]] %[[#mone_64]] %[[#zero_64]]
   %s4 = sext i1 %i1s to i64
   store i64 %s4, ptr @G_s4
-; SPV-DAG: %[[#s5]] = OpSelect %[[#vec_8]] %[[#i1v]] %[[#mones_8]] %[[#zeros_8]]
+; SPV: %[[#s5:]] = OpSelect %[[#vec_8]] %[[#i1v]] %[[#mones_8]] %[[#zeros_8]]
   %s5 = sext <2 x i1> %i1v to <2 x i8>
   store <2 x i8> %s5, ptr @G_s5
-; SPV-DAG: %[[#s6]] = OpSelect %[[#vec_16]] %[[#i1v]] %[[#mones_16]] %[[#zeros_16]]
+; SPV: %[[#s6:]] = OpSelect %[[#vec_16]] %[[#i1v]] %[[#mones_16]] %[[#zeros_16]]
   %s6 = sext <2 x i1> %i1v to <2 x i16>
   store <2 x i16> %s6, ptr @G_s6
-; SPV-DAG: %[[#s7]] = OpSelect %[[#vec_32]] %[[#i1v]] %[[#mones_32]] %[[#zeros_32]]
+; SPV: %[[#s7:]] = OpSelect %[[#vec_32]] %[[#i1v]] %[[#mones_32]] %[[#zeros_32]]
   %s7 = sext <2 x i1> %i1v to <2 x i32>
   store <2 x i32> %s7, ptr @G_s7
-; SPV-DAG: %[[#s8]] = OpSelect %[[#vec_64]] %[[#i1v]] %[[#mones_64]] %[[#zeros_64]]
+; SPV: %[[#s8:]] = OpSelect %[[#vec_64]] %[[#i1v]] %[[#mones_64]] %[[#zeros_64]]
   %s8 = sext <2 x i1> %i1v to <2 x i64>
   store <2 x i64> %s8, ptr @G_s8
-; SPV-DAG: %[[#z1]] = OpSelect %[[#int_8]] %[[#i1s]] %[[#one_8]] %[[#zero_8]]
+; SPV: %[[#z1:]] = OpSelect %[[#int_8]] %[[#i1s]] %[[#one_8]] %[[#zero_8]]
   %z1 = zext i1 %i1s to i8
   store i8 %z1, ptr @G_z1
-; SPV-DAG: %[[#z2]] = OpSelect %[[#int_16]] %[[#i1s]] %[[#one_16]] %[[#zero_16]]
+; SPV: %[[#z2:]] = OpSelect %[[#int_16]] %[[#i1s]] %[[#one_16]] %[[#zero_16]]
   %z2 = zext i1 %i1s to i16
   store i16 %z2, ptr @G_z2
-; SPV-DAG: %[[#z3]] = OpSelect %[[#int_32]] %[[#i1s]] %[[#one_32]] %[[#zero_32]]
+; SPV: %[[#z3:]] = OpSelect %[[#int_32]] %[[#i1s]] %[[#one_32]] %[[#zero_32]]
   %z3 = zext i1 %i1s to i32
   store i32 %z3, ptr @G_z3
-; SPV-DAG: %[[#z4]] = OpSelect %[[#int_64]] %[[#i1s]] %[[#one_64]] %[[#zero_64]]
+; SPV: %[[#z4:]] = OpSelect %[[#int_64]] %[[#i1s]] %[[#one_64]] %[[#zero_64]]
   %z4 = zext i1 %i1s to i64
   store i64 %z4, ptr @G_z4
-; SPV-DAG: %[[#z5]] = OpSelect %[[#vec_8]] %[[#i1v]] %[[#ones_8]] %[[#zeros_8]]
+; SPV: %[[#z5:]] = OpSelect %[[#vec_8]] %[[#i1v]] %[[#ones_8]] %[[#zeros_8]]
   %z5 = zext <2 x i1> %i1v to <2 x i8>
   store <2 x i8> %z5, ptr @G_z5
-; SPV-DAG: %[[#z6]] = OpSelect %[[#vec_16]] %[[#i1v]] %[[#ones_16]] %[[#zeros_16]]
+; SPV: %[[#z6:]] = OpSelect %[[#vec_16]] %[[#i1v]] %[[#ones_16]] %[[#zeros_16]]
   %z6 = zext <2 x i1> %i1v to <2 x i16>
   store <2 x i16> %z6, ptr @G_z6
-; SPV-DAG: %[[#z7]] = OpSelect %[[#vec_32]] %[[#i1v]] %[[#ones_32]] %[[#zeros_32]]
+; SPV: %[[#z7:]] = OpSelect %[[#vec_32]] %[[#i1v]] %[[#ones_32]] %[[#zeros_32]]
   %z7 = zext <2 x i1> %i1v to <2 x i32>
   store <2 x i32> %z7, ptr @G_z7
-; SPV-DAG: %[[#z8]] = OpSelect %[[#vec_64]] %[[#i1v]] %[[#ones_64]] %[[#zeros_64]]
+; SPV: %[[#z8:]] = OpSelect %[[#vec_64]] %[[#i1v]] %[[#ones_64]] %[[#zeros_64]]
   %z8 = zext <2 x i1> %i1v to <2 x i64>
   store <2 x i64> %z8, ptr @G_z8
-; SPV-DAG: %[[#ufp1_res:]] = OpSelect %[[#int_32]] %[[#i1s]] %[[#one_32]] %[[#zero_32]]
-; SPV-DAG: %[[#ufp1]] = OpConvertUToF %[[#float]] %[[#ufp1_res]]
+; SPV: %[[#ufp1_res:]] = OpSelect %[[#int_32]] %[[#i1s]] %[[#one_32]] %[[#zero_32]]
+; SPV: %[[#ufp1:]] = OpConvertUToF %[[#float]] %[[#ufp1_res]]
   %ufp1 = uitofp i1 %i1s to float
   store float %ufp1, ptr @G_ufp1
-; SPV-DAG: %[[#ufp2_res:]] = OpSelect %[[#vec_32]] %[[#i1v]] %[[#ones_32]] %[[#zeros_32]]
-; SPV-DAG: %[[#ufp2]] = OpConvertUToF %[[#vec_float]] %[[#ufp2_res]]
+; SPV: %[[#ufp2_res:]] = OpSelect %[[#vec_32]] %[[#i1v]] %[[#ones_32]] %[[#zeros_32]]
+; SPV: %[[#ufp2:]] = OpConvertUToF %[[#vec_float]] %[[#ufp2_res]]
   %ufp2 = uitofp <2 x i1> %i1v to <2 x float>
   store <2 x float> %ufp2, ptr @G_ufp2
-; SPV-DAG: %[[#sfp1_res:]] = OpSelect %[[#int_32]] %[[#i1s]] %[[#one_32]] %[[#zero_32]]
-; SPV-DAG: %[[#sfp1]] = OpConvertSToF %[[#float]] %[[#sfp1_res]]
+; SPV: %[[#sfp1_res:]] = OpSelect %[[#int_32]] %[[#i1s]] %[[#one_32]] %[[#zero_32]]
+; SPV: %[[#sfp1:]] = OpConvertSToF %[[#float]] %[[#sfp1_res]]
   %sfp1 = sitofp i1 %i1s to float
   store float %sfp1, ptr @G_sfp1
-; SPV-DAG: %[[#sfp2_res:]] = OpSelect %[[#vec_32]] %[[#i1v]] %[[#ones_32]] %[[#zeros_32]]
-; SPV-DAG: %[[#sfp2]] = OpConvertSToF %[[#vec_float]] %[[#sfp2_res]]
+; SPV: %[[#sfp2_res:]] = OpSelect %[[#vec_32]] %[[#i1v]] %[[#ones_32]] %[[#zeros_32]]
+; SPV: %[[#sfp2:]] = OpConvertSToF %[[#vec_float]] %[[#sfp2_res]]
   %sfp2 = sitofp <2 x i1> %i1v to <2 x float>
   store <2 x float> %sfp2, ptr @G_sfp2
   ret void
diff --git a/llvm/test/CodeGen/SPIRV/zero-length-array.ll b/llvm/test/CodeGen/SPIRV/zero-length-array.ll
index cb34529ebfecd..53cdcb5518397 100644
--- a/llvm/test/CodeGen/SPIRV/zero-length-array.ll
+++ b/llvm/test/CodeGen/SPIRV/zero-length-array.ll
@@ -5,9 +5,6 @@
 
 ; For compute, nothing is generated, but compilation doesn't crash.
 ; CHECK: OpName %[[#FOO:]] "foo"
-; CHECK: OpName %[[#RTM:]] "reg2mem alloca point"
-; CHECK: %[[#INT:]] = OpTypeInt 32 0
-; CHECK: %[[#RTM]] = OpConstant %[[#INT]] 0
 ; CHECK: %[[#FOO]] = OpFunction
 ; CHECK-NEXT: = OpLabel
 ; CHECK-NEXT: OpReturn