diff --git a/llvm/test/CodeGen/X86/pr172046.ll b/llvm/test/CodeGen/X86/pr172046.ll
new file mode 100644
index 0000000000000..850e04bc0bfc9
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr172046.ll
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64
+
+define i32 @shl_nuw_zext(i16 zeroext %x) {
+; X86-LABEL: shl_nuw_zext:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    shll $3, %eax
+; X86-NEXT:    movzwl %ax, %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: shl_nuw_zext:
+; X64:       # %bb.0:
+; X64-NEXT:    shll $3, %edi
+; X64-NEXT:    movzwl %di, %eax
+; X64-NEXT:    retq
+  %shl = shl nuw i16 %x, 3
+  %zext = zext i16 %shl to i32
+  ret i32 %zext
+}
+
+define i32 @shl_nsw_zext(i16 %x) {
+; X86-LABEL: shl_nsw_zext:
+; X86:       # %bb.0:
+; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    movl $256, %eax # imm = 0x100
+; X86-NEXT:    shll %cl, %eax
+; X86-NEXT:    movzwl %ax, %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: shl_nsw_zext:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %ecx
+; X64-NEXT:    movl $256, %eax # imm = 0x100
+; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
+; X64-NEXT:    shll %cl, %eax
+; X64-NEXT:    movzwl %ax, %eax
+; X64-NEXT:    retq
+  %shl = shl nsw i16 256, %x
+  %sext = sext i16 %shl to i32
+  ret i32 %sext
+}