diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 271888ba26820..1aa20015549b1 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -17,6 +17,7 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
+#include "llvm/TableGen/CodeGenHelpers.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TGTimer.h"
@@ -47,6 +48,7 @@ class RegisterBank {
 
   /// Get the human-readable name for the bank.
   StringRef getName() const { return TheDef.getValueAsString("Name"); }
+
   /// Get the name of the enumerator in the ID enumeration.
   std::string getEnumeratorName() const {
     return (TheDef.getName() + "ID").str();
@@ -110,11 +112,11 @@ class RegisterBankEmitter {
   const CodeGenTarget Target;
   const RecordKeeper &Records;
 
-  void emitHeader(raw_ostream &OS, const StringRef TargetName,
+  void emitHeader(raw_ostream &OS, StringRef TargetName,
                   ArrayRef<RegisterBank> Banks);
-  void emitBaseClassDefinition(raw_ostream &OS, const StringRef TargetName,
+  void emitBaseClassDefinition(raw_ostream &OS, StringRef TargetName,
                                ArrayRef<RegisterBank> Banks);
-  void emitBaseClassImplementation(raw_ostream &OS, const StringRef TargetName,
+  void emitBaseClassImplementation(raw_ostream &OS, StringRef TargetName,
                                    ArrayRef<RegisterBank> Banks);
 
 public:
@@ -127,27 +129,27 @@ class RegisterBankEmitter {
 
 /// Emit code to declare the ID enumeration and external global instance
 /// variables.
-void RegisterBankEmitter::emitHeader(raw_ostream &OS,
-                                     const StringRef TargetName,
+void RegisterBankEmitter::emitHeader(raw_ostream &OS, StringRef TargetName,
                                      ArrayRef<RegisterBank> Banks) {
+  IfDefEmitter IfDef(OS, "GET_REGBANK_DECLARATIONS");
+  NamespaceEmitter NS(OS, ("llvm::" + TargetName).str());
+
   // <Target>RegisterBankInfo.h
-  OS << "namespace llvm {\n"
-     << "namespace " << TargetName << " {\n"
-     << "enum : unsigned {\n";
+  OS << "enum : unsigned {\n";
 
   OS << "  InvalidRegBankID = ~0u,\n";
   unsigned ID = 0;
   for (const auto &Bank : Banks)
     OS << "  " << Bank.getEnumeratorName() << " = " << ID++ << ",\n";
   OS << "  NumRegisterBanks,\n"
-     << "};\n"
-     << "} // end namespace " << TargetName << "\n"
-     << "} // end namespace llvm\n";
+     << "};\n";
 }
 
 /// Emit declarations of the <Target>GenRegisterBankInfo class.
 void RegisterBankEmitter::emitBaseClassDefinition(
-    raw_ostream &OS, const StringRef TargetName, ArrayRef<RegisterBank> Banks) {
+    raw_ostream &OS, StringRef TargetName, ArrayRef<RegisterBank> Banks) {
+  IfDefEmitter IfDef(OS, "GET_TARGET_REGBANK_CLASS");
+
   OS << "private:\n"
      << "  static const RegisterBank *RegBanks[];\n"
      << "  static const unsigned Sizes[];\n\n"
@@ -221,44 +223,46 @@ void RegisterBankEmitter::emitBaseClassImplementation(
   const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
   const CodeGenHwModes &CGH = Target.getHwModes();
 
-  OS << "namespace llvm {\n"
-     << "namespace " << TargetName << " {\n";
-  for (const auto &Bank : Banks) {
-    std::vector<std::vector<const CodeGenRegisterClass *>> RCsGroupedByWord(
-        (RegisterClassHierarchy.getRegClasses().size() + 31) / 32);
-
-    for (const auto &RC : Bank.register_classes())
-      RCsGroupedByWord[RC->EnumValue / 32].push_back(RC);
-
-    OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n";
-    unsigned LowestIdxInWord = 0;
-    for (const auto &RCs : RCsGroupedByWord) {
-      OS << "    // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31)
-         << "\n";
-      for (const auto &RC : RCs) {
-        OS << "    (1u << (" << RC->getQualifiedIdName() << " - "
-           << LowestIdxInWord << ")) |\n";
+  IfDefEmitter IfDef(OS, "GET_TARGET_REGBANK_IMPL");
+  NamespaceEmitter LlvmNS(OS, "llvm");
+
+  {
+    NamespaceEmitter TargetNS(OS, TargetName);
+    for (const auto &Bank : Banks) {
+      std::vector<std::vector<const CodeGenRegisterClass *>> RCsGroupedByWord(
+          (RegisterClassHierarchy.getRegClasses().size() + 31) / 32);
+
+      for (const auto &RC : Bank.register_classes())
+        RCsGroupedByWord[RC->EnumValue / 32].push_back(RC);
+
+      OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n";
+      unsigned LowestIdxInWord = 0;
+      for (const auto &RCs : RCsGroupedByWord) {
+        OS << "    // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31)
+           << "\n";
+        for (const auto &RC : RCs) {
+          OS << "    (1u << (" << RC->getQualifiedIdName() << " - "
+             << LowestIdxInWord << ")) |\n";
+        }
+        OS << "    0,\n";
+        LowestIdxInWord += 32;
       }
-      OS << "    0,\n";
-      LowestIdxInWord += 32;
+      OS << "};\n";
     }
-    OS << "};\n";
-  }
-  OS << "\n";
+    OS << "\n";
 
-  for (const auto &Bank : Banks) {
-    std::string QualifiedBankID =
-        (TargetName + "::" + Bank.getEnumeratorName()).str();
-    OS << "constexpr RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "
-       << QualifiedBankID << ", /* Name */ \"" << Bank.getName() << "\", "
-       << "/* CoveredRegClasses */ " << Bank.getCoverageArrayName()
-       << ", /* NumRegClasses */ "
-       << RegisterClassHierarchy.getRegClasses().size() << ");\n";
-  }
-  OS << "} // end namespace " << TargetName << "\n"
-     << "\n";
+    for (const auto &Bank : Banks) {
+      std::string QualifiedBankID =
+          (TargetName + "::" + Bank.getEnumeratorName()).str();
+      OS << "constexpr RegisterBank " << Bank.getInstanceVarName()
+         << "(/* ID */ " << QualifiedBankID << ", /* Name */ \""
+         << Bank.getName() << "\", " << "/* CoveredRegClasses */ "
+         << Bank.getCoverageArrayName() << ", /* NumRegClasses */ "
+         << RegisterClassHierarchy.getRegClasses().size() << ");\n";
+    }
+  } // End target namespace.
 
-  OS << "const RegisterBank *" << TargetName
+  OS << "\nconst RegisterBank *" << TargetName
      << "GenRegisterBankInfo::RegBanks[] = {\n";
   for (const auto &Bank : Banks)
     OS << "    &" << TargetName << "::" << Bank.getInstanceVarName() << ",\n";
@@ -322,7 +326,7 @@ void RegisterBankEmitter::emitBaseClassImplementation(
       E.RBIdName = "InvalidRegBankID";
     }
   }
-  OS << "const RegisterBank &\n"
+  OS << "\nconst RegisterBank &\n"
      << TargetName
      << "GenRegisterBankInfo::getRegBankFromRegClass"
         "(const TargetRegisterClass &RC, LLT) const {\n";
@@ -377,8 +381,6 @@ void RegisterBankEmitter::emitBaseClassImplementation(
         "class ID "
         "0x\").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());\n"
         "}\n";
-
-  OS << "} // end namespace llvm\n";
 }
 
 void RegisterBankEmitter::run(raw_ostream &OS) {
@@ -424,18 +426,9 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
 
   Timer.startTimer("Emit output");
   emitSourceFileHeader("Register Bank Source Fragments", OS);
-  OS << "#ifdef GET_REGBANK_DECLARATIONS\n"
-     << "#undef GET_REGBANK_DECLARATIONS\n";
   emitHeader(OS, TargetName, Banks);
-  OS << "#endif // GET_REGBANK_DECLARATIONS\n\n"
-     << "#ifdef GET_TARGET_REGBANK_CLASS\n"
-     << "#undef GET_TARGET_REGBANK_CLASS\n";
   emitBaseClassDefinition(OS, TargetName, Banks);
-  OS << "#endif // GET_TARGET_REGBANK_CLASS\n\n"
-     << "#ifdef GET_TARGET_REGBANK_IMPL\n"
-     << "#undef GET_TARGET_REGBANK_IMPL\n";
   emitBaseClassImplementation(OS, TargetName, Banks);
-  OS << "#endif // GET_TARGET_REGBANK_IMPL\n";
 }
 
 static TableGen::Emitter::OptClass<RegisterBankEmitter>