diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst index efb20520db1b1..f7df57d05baa0 100644 --- a/llvm/docs/MIRLangRef.rst +++ b/llvm/docs/MIRLangRef.rst @@ -495,13 +495,13 @@ In ``AArch64RegisterInfo.td``: def sub_32 : SubRegIndex<32>; -If the third operand is an immediate with the value ``15`` (a target-dependent +If the second operand is an immediate with the value ``15`` (a target-dependent value), based on the instruction's opcode and the operand's index the operand will be printed as ``%subreg.sub_32``: .. code-block:: text - %1:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32 + %1:gpr64 = SUBREG_TO_REG %0, %subreg.sub_32 For integers larger than 64 bits, we use a special machine operand, ``MO_CImmediate``, which stores the immediate in a ``ConstantInt`` using an ``APInt`` (LLVM's diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h index 873cad4953541..29da32c931eea 100644 --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -672,7 +672,7 @@ class MachineInstr return true; if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0) return true; - if (isSubregToReg() && OpIdx == 3) + if (isSubregToReg() && OpIdx == 2) return true; return false; } diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def index 3217ffafc235a..119e7c69efe89 100644 --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -62,10 +62,10 @@ HANDLE_TARGET_OPCODE(IMPLICIT_DEF) HANDLE_TARGET_OPCODE(INIT_UNDEF) /// SUBREG_TO_REG - Assert the value of bits in a super register. -/// The result of this instruction is the value of the second operand inserted -/// into the subregister specified by the third operand. All other bits are -/// assumed to be equal to the bits in the immediate integer constant in the -/// first operand. This instruction just communicates information; No code +/// The result of this instruction is the value of the first operand inserted +/// into the subregister specified by the second operand. All other bits are +/// assumed to be zero. +/// This instruction just communicates information; No code /// should be generated. /// This is typically used after an instruction where the write to a subregister /// implicitly cleared the bits in the super registers. diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td index abe3a7d1701ee..3d3cfe6948ded 100644 --- a/llvm/include/llvm/Target/Target.td +++ b/llvm/include/llvm/Target/Target.td @@ -1291,7 +1291,7 @@ def INIT_UNDEF : StandardPseudoInstruction { } def SUBREG_TO_REG : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); - let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); + let InOperandList = (ins unknown:$subsrc, i32imm:$subidx); let AsmString = ""; let hasSideEffects = false; } diff --git a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp index 9692420c7020b..94e7ee4fa0855 100644 --- a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp +++ b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp @@ -75,15 +75,14 @@ INITIALIZE_PASS(ExpandPostRALegacy, DEBUG_TYPE, bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); - assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && - MI->getOperand(1).isImm() && - (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && - MI->getOperand(3).isImm() && "Invalid subreg_to_reg"); + assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && + MI->getOperand(1).isReg() && MI->getOperand(1).isUse() && + MI->getOperand(2).isImm() && "Invalid subreg_to_reg"); Register DstReg = MI->getOperand(0).getReg(); - Register InsReg = MI->getOperand(2).getReg(); - assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); - unsigned SubIdx = MI->getOperand(3).getImm(); + Register InsReg = MI->getOperand(1).getReg(); + assert(!MI->getOperand(1).getSubReg() && "SubIdx on physreg?"); + unsigned SubIdx = MI->getOperand(2).getImm(); assert(SubIdx != 0 && "Invalid index for insert_subreg"); Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); @@ -98,17 +97,16 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { if (MI->allDefsAreDead() || DstSubReg == InsReg) { // No need to insert an identity copy instruction. // Watch out for case like this: - // %rax = SUBREG_TO_REG 0, killed %eax, 3 + // %rax = SUBREG_TO_REG killed %eax, 3 // We must leave %rax live. MI->setDesc(TII->get(TargetOpcode::KILL)); - MI->removeOperand(3); // SubIdx - MI->removeOperand(1); // Imm + MI->removeOperand(2); // SubIdx LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI); return true; } TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg, - MI->getOperand(2).isKill()); + MI->getOperand(1).isKill()); // Implicitly define DstReg for subsequent uses. MachineBasicBlock::iterator CopyMI = MI; diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index 8d7694537e07d..fb35c7e62dad6 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -1119,8 +1119,8 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI) SubReg = Cpy.getOperand(1).getSubReg(); } else if (Cpy.isSubregToReg()) { OldReg = Cpy.getOperand(0).getReg(); - NewReg = Cpy.getOperand(2).getReg(); - SubReg = Cpy.getOperand(3).getImm(); + NewReg = Cpy.getOperand(1).getReg(); + SubReg = Cpy.getOperand(2).getImm(); } else { auto CopyDetails = *TII.isCopyInstr(Cpy); const MachineOperand &Src = *CopyDetails.Source; diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp index a28bdd3aefc4e..da30f2d0c0dfc 100644 --- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp +++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp @@ -833,14 +833,14 @@ bool PeepholeOptimizer::optimizeExtInstr( // // %reg1025 = %reg1024 // ... - // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4 + // %reg1026 = SUBREG_TO_REG %reg1024, 4 // // into this: // // %reg1025 = %reg1024 // ... // %reg1027 = COPY %reg1025:4 - // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4 + // %reg1026 = SUBREG_TO_REG %reg1027, 4 // // The problem here is that SUBREG_TO_REG is there to assert that an // implicit zext occurs. It doesn't insert a zext instruction. If we allow @@ -2131,21 +2131,21 @@ ValueTrackerResult ValueTracker::getNextSourceFromExtractSubreg() { ValueTrackerResult ValueTracker::getNextSourceFromSubregToReg() { assert(Def->isSubregToReg() && "Invalid definition"); // We are looking at: - // Def = SUBREG_TO_REG Imm, v0, sub0 + // Def = SUBREG_TO_REG v0, sub0 // Bail if we have to compose sub registers. // If DefSubReg != sub0, we would have to check that all the bits // we track are included in sub0 and if yes, we would have to // determine the right subreg in v0. - if (DefSubReg != Def->getOperand(3).getImm()) + if (DefSubReg != Def->getOperand(2).getImm()) return ValueTrackerResult(); // Bail if we have to compose sub registers. // Likewise, if v0.subreg != 0, we would have to compose it with sub0. - if (Def->getOperand(2).getSubReg()) + if (Def->getOperand(1).getSubReg()) return ValueTrackerResult(); - return ValueTrackerResult(Def->getOperand(2).getReg(), - Def->getOperand(3).getImm()); + return ValueTrackerResult(Def->getOperand(1).getReg(), + Def->getOperand(2).getImm()); } /// Explore each PHI incoming operand and return its sources. diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index 527ecca6eab47..586c27b7e3baf 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -430,9 +430,9 @@ INITIALIZE_PASS_END(RegisterCoalescerLegacy, "register-coalescer", } else if (MI->isSubregToReg()) { Dst = MI->getOperand(0).getReg(); DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), - MI->getOperand(3).getImm()); - Src = MI->getOperand(2).getReg(); - SrcSub = MI->getOperand(2).getSubReg(); + MI->getOperand(2).getImm()); + Src = MI->getOperand(1).getReg(); + SrcSub = MI->getOperand(1).getSubReg(); } else return false; return true; diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index bb203f6367b5b..d9d847d747334 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -574,10 +574,17 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap, } } else if (Opc == TargetOpcode::INSERT_SUBREG || Opc == TargetOpcode::SUBREG_TO_REG) { - SDValue N0 = Node->getOperand(0); - SDValue N1 = Node->getOperand(1); - SDValue N2 = Node->getOperand(2); - unsigned SubIdx = N2->getAsZExtVal(); + SDValue Reg; + SDValue SubReg; + unsigned SubIdx; + if (Opc == TargetOpcode::INSERT_SUBREG) { + Reg = Node->getOperand(0); + SubReg = Node->getOperand(1); + SubIdx = Node->getOperand(2)->getAsZExtVal(); + } else { + SubReg = Node->getOperand(0); + SubIdx = Node->getOperand(1)->getAsZExtVal(); + } // Figure out the register class to create for the destreg. It should be // the largest legal register class supporting SubIdx sub-registers. @@ -605,17 +612,15 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap, MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase); - // If creating a subreg_to_reg, then the first input operand - // is an implicit value immediate, otherwise it's a register - if (Opc == TargetOpcode::SUBREG_TO_REG) { - const ConstantSDNode *SD = cast(N0); - MIB.addImm(SD->getZExtValue()); - } else - AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false, - IsClone, IsCloned); + // If creating an insert_subreg, then the first input operand + // is a register + if (Reg) { + AddOperand(MIB, Reg, 0, nullptr, VRBaseMap, /*IsDebug=*/false, IsClone, + IsCloned); + } // Add the subregister being inserted - AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false, - IsClone, IsCloned); + AddOperand(MIB, SubReg, 0, nullptr, VRBaseMap, /*IsDebug=*/false, IsClone, + IsCloned); MIB.addImm(SubIdx); MBB->insert(InsertPos, MIB); } else diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp index cffb3ed1b8779..a56285679929e 100644 --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -646,7 +646,7 @@ TargetRegisterInfo::lookThruCopyLike(Register SrcReg, CopySrcReg = MI->getOperand(1).getReg(); else { assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike"); - CopySrcReg = MI->getOperand(2).getReg(); + CopySrcReg = MI->getOperand(1).getReg(); } if (!CopySrcReg.isVirtual()) @@ -669,7 +669,7 @@ Register TargetRegisterInfo::lookThruSingleUseCopyChain( CopySrcReg = MI->getOperand(1).getReg(); else { assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike"); - CopySrcReg = MI->getOperand(2).getReg(); + CopySrcReg = MI->getOperand(1).getReg(); } // Continue only if the next definition in the chain is for a virtual diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index ff339d4a23915..fe67e434a4de3 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -357,10 +357,10 @@ bool TwoAddressInstructionImpl::isCopyToReg(MachineInstr &MI, Register &SrcReg, bool &IsDstPhys) const { SrcReg = 0; DstReg = 0; - if (MI.isCopy()) { + if (MI.isCopy() || MI.isSubregToReg()) { DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); - } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { + } else if (MI.isInsertSubreg()) { DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(2).getReg(); } else { diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index 7cd32ebe2e2f7..8c0377fa5550f 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -484,7 +484,6 @@ Register AArch64FastISel::materializeGV(const GlobalValue *GV) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::SUBREG_TO_REG)) .addDef(Result64) - .addImm(0) .addReg(ResultReg, RegState::Kill) .addImm(AArch64::sub_32); return Result64; @@ -1873,7 +1872,6 @@ Register AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr, Register Reg64 = createResultReg(&AArch64::GPR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), Reg64) - .addImm(0) .addReg(ResultReg, getKillRegState(true)) .addImm(AArch64::sub_32); ResultReg = Reg64; @@ -4031,7 +4029,6 @@ Register AArch64FastISel::emiti1Ext(Register SrcReg, MVT DestVT, bool IsZExt) { Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), Reg64) - .addImm(0) .addReg(ResultReg) .addImm(AArch64::sub_32); ResultReg = Reg64; @@ -4178,7 +4175,6 @@ Register AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, Register Op0, Register TmpReg = MRI.createVirtualRegister(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), TmpReg) - .addImm(0) .addReg(Op0) .addImm(AArch64::sub_32); Op0 = TmpReg; @@ -4295,7 +4291,6 @@ Register AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, Register Op0, Register TmpReg = MRI.createVirtualRegister(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), TmpReg) - .addImm(0) .addReg(Op0) .addImm(AArch64::sub_32); Op0 = TmpReg; @@ -4401,7 +4396,6 @@ Register AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, Register Op0, Register TmpReg = MRI.createVirtualRegister(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), TmpReg) - .addImm(0) .addReg(Op0) .addImm(AArch64::sub_32); Op0 = TmpReg; @@ -4459,7 +4453,6 @@ Register AArch64FastISel::emitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, Register Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), Src64) - .addImm(0) .addReg(SrcReg) .addImm(AArch64::sub_32); SrcReg = Src64; @@ -4556,7 +4549,6 @@ bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT, Register Reg64 = createResultReg(&AArch64::GPR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), Reg64) - .addImm(0) .addReg(Reg, getKillRegState(true)) .addImm(AArch64::sub_32); Reg = Reg64; @@ -4599,7 +4591,6 @@ bool AArch64FastISel::selectIntExt(const Instruction *I) { Register ResultReg = createResultReg(&AArch64::GPR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), ResultReg) - .addImm(0) .addReg(SrcReg) .addImm(AArch64::sub_32); SrcReg = ResultReg; diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 0fb2b6493e061..5a4f00ea718fb 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -1756,12 +1756,9 @@ bool AArch64DAGToDAGISel::tryIndexedLoad(SDNode *N) { SDValue LoadedVal = SDValue(Res, 1); if (InsertTo64) { SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); - LoadedVal = - SDValue(CurDAG->getMachineNode( - AArch64::SUBREG_TO_REG, dl, MVT::i64, - CurDAG->getTargetConstant(0, dl, MVT::i64), LoadedVal, - SubReg), - 0); + LoadedVal = SDValue(CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, dl, + MVT::i64, LoadedVal, SubReg), + 0); } ReplaceUses(SDValue(N, 0), LoadedVal); @@ -3989,9 +3986,8 @@ bool AArch64DAGToDAGISel::tryShiftAmountMod(SDNode *N) { NewShiftAmt = narrowIfNeeded(CurDAG, NewShiftAmt); else if (VT == MVT::i64 && NewShiftAmt->getValueType(0) == MVT::i32) { SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, DL, MVT::i32); - MachineSDNode *Ext = CurDAG->getMachineNode( - AArch64::SUBREG_TO_REG, DL, VT, - CurDAG->getTargetConstant(0, DL, MVT::i64), NewShiftAmt, SubReg); + MachineSDNode *Ext = CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, DL, VT, + NewShiftAmt, SubReg); NewShiftAmt = SDValue(Ext, 0); } @@ -4710,8 +4706,8 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) { SDValue MOVIV = SDValue(MOV, 0); SDValue ZSub = CurDAG->getTargetConstant(AArch64::zsub, DL, MVT::i32); - SDNode *SubRegToReg = CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, DL, - VT, Zero, MOVIV, ZSub); + SDNode *SubRegToReg = + CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, DL, VT, MOVIV, ZSub); R1 = N1->getOperand(1); R2 = SDValue(SubRegToReg, 0); diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 840298ff965e1..ea29f89d13f17 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -3378,7 +3378,7 @@ static const MachineInstr *stripVRegCopies(const MachineRegisterInfo &MRI, continue; } if (Opcode == AArch64::SUBREG_TO_REG) { - Reg = DefMI->getOperand(2).getReg(); + Reg = DefMI->getOperand(1).getReg(); continue; } diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td index 5d9215dd71233..21982300f5213 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td +++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td @@ -313,19 +313,19 @@ def ldxr_8 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{ } def : Pat<(ldxr_1 GPR64sp:$addr), - (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDXRB GPR64sp:$addr), sub_32)>; def : Pat<(ldxr_2 GPR64sp:$addr), - (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDXRH GPR64sp:$addr), sub_32)>; def : Pat<(ldxr_4 GPR64sp:$addr), - (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDXRW GPR64sp:$addr), sub_32)>; def : Pat<(ldxr_8 GPR64sp:$addr), (LDXRX GPR64sp:$addr)>; def : Pat<(and (ldxr_1 GPR64sp:$addr), 0xff), - (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDXRB GPR64sp:$addr), sub_32)>; def : Pat<(and (ldxr_2 GPR64sp:$addr), 0xffff), - (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDXRH GPR64sp:$addr), sub_32)>; def : Pat<(and (ldxr_4 GPR64sp:$addr), 0xffffffff), - (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDXRW GPR64sp:$addr), sub_32)>; // Load-exclusives. @@ -354,19 +354,19 @@ def ldaxr_8 : PatFrag<(ops node:$ptr), (int_aarch64_ldaxr node:$ptr), [{ } def : Pat<(ldaxr_1 GPR64sp:$addr), - (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDAXRB GPR64sp:$addr), sub_32)>; def : Pat<(ldaxr_2 GPR64sp:$addr), - (SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDAXRH GPR64sp:$addr), sub_32)>; def : Pat<(ldaxr_4 GPR64sp:$addr), - (SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDAXRW GPR64sp:$addr), sub_32)>; def : Pat<(ldaxr_8 GPR64sp:$addr), (LDAXRX GPR64sp:$addr)>; def : Pat<(and (ldaxr_1 GPR64sp:$addr), 0xff), - (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDAXRB GPR64sp:$addr), sub_32)>; def : Pat<(and (ldaxr_2 GPR64sp:$addr), 0xffff), - (SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDAXRH GPR64sp:$addr), sub_32)>; def : Pat<(and (ldaxr_4 GPR64sp:$addr), 0xffffffff), - (SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDAXRW GPR64sp:$addr), sub_32)>; // Store-exclusives. @@ -596,7 +596,7 @@ let Predicates = [HasRCPC3, HasNEON] in { // by the patterns above. We only need to cover the v1f64 case manually. def : Pat<(releasing_store GPR64sp:$Rn, (i64 (bitconvert (v1f64 VecListOne64:$Vt)))), - (STL1 (SUBREG_TO_REG (i64 0), VecListOne64:$Vt, dsub), (i64 0), GPR64sp:$Rn)>; + (STL1 (SUBREG_TO_REG VecListOne64:$Vt, dsub), (i64 0), GPR64sp:$Rn)>; } // v8.4a FEAT_LRCPC2 patterns diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index ed2028c552dbf..7d4e034ca16c8 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -2768,11 +2768,11 @@ multiclass Shift shift_type, string asm, SDNode OpNode> { def : Pat<(i64 (OpNode GPR64:$Rn, (i64 (sext GPR32:$Rm)))), (!cast(NAME # "Xr") GPR64:$Rn, - (SUBREG_TO_REG (i32 0), GPR32:$Rm, sub_32))>; + (SUBREG_TO_REG GPR32:$Rm, sub_32))>; def : Pat<(i64 (OpNode GPR64:$Rn, (i64 (zext GPR32:$Rm)))), (!cast(NAME # "Xr") GPR64:$Rn, - (SUBREG_TO_REG (i32 0), GPR32:$Rm, sub_32))>; + (SUBREG_TO_REG GPR32:$Rm, sub_32))>; } class ShiftAlias @@ -9468,7 +9468,7 @@ multiclass SIMDFPIndexedTiedPatterns { def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (AArch64dup (f16 FPR16Op_lo:$Rm)))), (!cast(INST # "v8i16_indexed") V128:$Rd, V128:$Rn, - (SUBREG_TO_REG (i32 0), (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>; + (SUBREG_TO_REG (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>; def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (AArch64duplane16 (v8f16 V128_lo:$Rm), @@ -9478,7 +9478,7 @@ multiclass SIMDFPIndexedTiedPatterns { def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (AArch64dup (f16 FPR16Op_lo:$Rm)))), (!cast(INST # "v4i16_indexed") V64:$Rd, V64:$Rn, - (SUBREG_TO_REG (i32 0), (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>; + (SUBREG_TO_REG (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>; def : Pat<(f16 (OpNode (f16 FPR16:$Rd), (f16 FPR16:$Rn), (vector_extract (v8f16 V128_lo:$Rm), VectorIndexH:$idx))), @@ -9500,7 +9500,7 @@ multiclass SIMDFPIndexedTiedPatterns { def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (AArch64dup (f32 FPR32Op:$Rm)))), (!cast(INST # "v2i32_indexed") V64:$Rd, V64:$Rn, - (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; + (SUBREG_TO_REG FPR32Op:$Rm, ssub), (i64 0))>; // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar. @@ -9512,7 +9512,7 @@ multiclass SIMDFPIndexedTiedPatterns { def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (AArch64dup (f32 FPR32Op:$Rm)))), (!cast(INST # "v4i32_indexed") V128:$Rd, V128:$Rn, - (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; + (SUBREG_TO_REG FPR32Op:$Rm, ssub), (i64 0))>; // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar. def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), @@ -9523,7 +9523,7 @@ multiclass SIMDFPIndexedTiedPatterns { def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (AArch64dup (f64 FPR64Op:$Rm)))), (!cast(INST # "v2i64_indexed") V128:$Rd, V128:$Rn, - (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>; + (SUBREG_TO_REG FPR64Op:$Rm, dsub), (i64 0))>; // Covers 2 variants for 32-bit scalar version: extract from .2s or from .4s def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), @@ -9632,7 +9632,7 @@ multiclass SIMDIndexedHSPatterns(NAME # v4i16_indexed) $Rn, - (SUBREG_TO_REG (i32 0), (v4i16 V64_lo:$Rm), dsub), + (SUBREG_TO_REG (v4i16 V64_lo:$Rm), dsub), (UImmS1XForm $idx))>; def : Pat<(v4i16 (OpNodeLaneQ @@ -9645,7 +9645,7 @@ multiclass SIMDIndexedHSPatterns(NAME # v8i16_indexed) $Rn, - (SUBREG_TO_REG (i32 0), $Rm, dsub), + (SUBREG_TO_REG $Rm, dsub), (UImmS1XForm $idx))>; def : Pat<(v8i16 (OpNodeLaneQ @@ -9658,7 +9658,7 @@ multiclass SIMDIndexedHSPatterns(NAME # v2i32_indexed) $Rn, - (SUBREG_TO_REG (i32 0), (v2i32 V64_lo:$Rm), dsub), + (SUBREG_TO_REG (v2i32 V64_lo:$Rm), dsub), (UImmS1XForm $idx))>; def : Pat<(v2i32 (OpNodeLaneQ @@ -9671,7 +9671,7 @@ multiclass SIMDIndexedHSPatterns(NAME # v4i32_indexed) $Rn, - (SUBREG_TO_REG (i32 0), $Rm, dsub), + (SUBREG_TO_REG $Rm, dsub), (UImmS1XForm $idx))>; def : Pat<(v4i32 (OpNodeLaneQ diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 1775e3de8c8c5..a6ca2c5cdaa07 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -823,15 +823,13 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, case AArch64::SUBREG_TO_REG: // Check for the following way to define an 64-bit immediate: // %0:gpr32 = MOVi32imm 1 - // %1:gpr64 = SUBREG_TO_REG 0, %0:gpr32, %subreg.sub_32 - if (!DefMI->getOperand(1).isImm() || DefMI->getOperand(1).getImm() != 0) + // %1:gpr64 = SUBREG_TO_REG %0:gpr32, %subreg.sub_32 + if (!DefMI->getOperand(1).isReg()) return 0; - if (!DefMI->getOperand(2).isReg()) + if (!DefMI->getOperand(2).isImm() || + DefMI->getOperand(2).getImm() != AArch64::sub_32) return 0; - if (!DefMI->getOperand(3).isImm() || - DefMI->getOperand(3).getImm() != AArch64::sub_32) - return 0; - DefMI = MRI.getVRegDef(DefMI->getOperand(2).getReg()); + DefMI = MRI.getVRegDef(DefMI->getOperand(1).getReg()); if (DefMI->getOpcode() != AArch64::MOVi32imm) return 0; if (!DefMI->getOperand(1).isImm() || DefMI->getOperand(1).getImm() != 1) @@ -3557,12 +3555,11 @@ bool AArch64InstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, // ldr Xd, [Xn, Wm, uxtw #N] // Zero-extension looks like an ORRWrs followed by a SUBREG_TO_REG. - if (AddrI.getOperand(1).getImm() != 0 || - AddrI.getOperand(3).getImm() != AArch64::sub_32) + if (AddrI.getOperand(2).getImm() != AArch64::sub_32) return false; const MachineRegisterInfo &MRI = AddrI.getMF()->getRegInfo(); - Register OffsetReg = AddrI.getOperand(2).getReg(); + Register OffsetReg = AddrI.getOperand(1).getReg(); if (!OffsetReg.isVirtual() || !MRI.hasOneNonDBGUse(OffsetReg)) return false; @@ -8029,7 +8026,7 @@ static bool getGatherLanePattern(MachineInstr &Root, return false; // Verify that the subreg to reg loads an integer into the first lane. - auto Lane0LoadReg = CurrInstr->getOperand(2).getReg(); + auto Lane0LoadReg = CurrInstr->getOperand(1).getReg(); unsigned SingleLaneSizeInBits = 128 / NumLanes; if (TRI->getRegSizeInBits(Lane0LoadReg, MRI) != SingleLaneSizeInBits) return false; @@ -8133,7 +8130,7 @@ generateGatherLanePattern(MachineInstr &Root, MachineInstr *SubregToReg = CurrInstr; LoadToLaneInstrs.push_back( - MRI.getUniqueVRegDef(SubregToReg->getOperand(2).getReg())); + MRI.getUniqueVRegDef(SubregToReg->getOperand(1).getReg())); auto LoadToLaneInstrsAscending = llvm::reverse(LoadToLaneInstrs); const TargetRegisterClass *FPR128RegClass = @@ -8237,7 +8234,6 @@ generateGatherLanePattern(MachineInstr &Root, auto SubRegToRegInstr = BuildMI(MF, MIMetadata(Root), TII->get(SubregToReg->getOpcode()), DestRegForSubregToReg) - .addImm(0) .addReg(DestRegForMiddleIndex, getKillRegState(true)) .addImm(SubregType); InstrIdxForVirtReg.insert( diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index ba32eac2f0d28..bd67f97bc0e03 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -2669,7 +2669,7 @@ let Predicates = [OptimizedGISelOrOtherSelector] in { // The SUBREG_TO_REG isn't eliminated at -O0, which can result in pointless // copies. def : Pat<(i64 i64imm_32bit:$src), - (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>; + (SUBREG_TO_REG (MOVi32imm (trunc_imm imm:$src)), sub_32)>; } // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model). @@ -3325,7 +3325,7 @@ def : Pat<(not logical_shifted_reg64:$Rm_and_shift), // Emit (and 0xFFFFFFFF) as a ORRWrr move which may be eliminated. let AddedComplexity = 6 in def : Pat<(i64 (and GPR64:$Rn, 0xffffffff)), - (SUBREG_TO_REG (i64 0), (ORRWrr WZR, (EXTRACT_SUBREG GPR64:$Rn, sub_32)), sub_32)>; + (SUBREG_TO_REG (ORRWrr WZR, (EXTRACT_SUBREG GPR64:$Rn, sub_32)), sub_32)>; //===----------------------------------------------------------------------===// @@ -3907,13 +3907,11 @@ let Predicates = [IsLE] in { multiclass ExtLoadTo64ROPat { def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), - (SUBREG_TO_REG (i64 0), - (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), + (SUBREG_TO_REG (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), sub_32)>; def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), - (SUBREG_TO_REG (i64 0), - (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), + (SUBREG_TO_REG (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), sub_32)>; } @@ -4039,15 +4037,15 @@ defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb", uimm12s1:$offset)))]>; // zextload -> i64 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), - (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; + (SUBREG_TO_REG (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), - (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; + (SUBREG_TO_REG (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; // zextloadi1 -> zextloadi8 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), - (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; + (SUBREG_TO_REG (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; // extload -> zextload def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), @@ -4057,13 +4055,13 @@ def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))), - (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; + (SUBREG_TO_REG (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), - (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; + (SUBREG_TO_REG (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), - (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; + (SUBREG_TO_REG (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), - (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; + (SUBREG_TO_REG (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; // load sign-extended half-word defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh", @@ -4093,7 +4091,7 @@ defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw", // load zero-extended word def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))), - (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; + (SUBREG_TO_REG (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; // Pre-fetch. def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm", @@ -4136,7 +4134,7 @@ def LDRSWl : LoadLiteral<0b10, 0, GPR64z, "ldrsw", let AddedComplexity = 20 in { def : Pat<(i64 (zextloadi32 (AArch64adr alignedglobal:$label))), - (SUBREG_TO_REG (i64 0), (LDRWl $label), sub_32)>; + (SUBREG_TO_REG (LDRWl $label), sub_32)>; } // prefetch @@ -4226,13 +4224,13 @@ def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (LDURBBi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; // unscaled zext def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), (LDURHHi GPR64sp:$Rn, simm9:$offset)>; @@ -4241,13 +4239,13 @@ def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (LDURBBi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; //--- @@ -4304,9 +4302,9 @@ def : InstAlias<"ldr $Rt, [$Rn, $offset]", // zextload -> i64 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; // load sign-extended half-word defm LDURSHW @@ -4360,33 +4358,33 @@ multiclass LoadInsertVTPatterns; + (SUBREG_TO_REG (LoadInst GPR64sp:$Rn, AddrImm:$offset), SubReg)>; // Unscaled def : Pat <(vector_insert (VT immAllZerosV), (ScalarVT (LoadOp (UnscaledAddr GPR64sp:$Rn, simm9:$offset))), (i64 0)), - (SUBREG_TO_REG (i64 0), (UnscaledLoadInst GPR64sp:$Rn, simm9:$offset), SubReg)>; + (SUBREG_TO_REG (UnscaledLoadInst GPR64sp:$Rn, simm9:$offset), SubReg)>; // roW def : Pat <(vector_insert (VT immAllZerosV), (ScalarVT (LoadOp (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), (i64 0)), - (SUBREG_TO_REG (i64 0), (ROWLoadInst GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), SubReg)>; + (SUBREG_TO_REG (ROWLoadInst GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), SubReg)>; // roX def : Pat <(vector_insert (VT immAllZerosV), (ScalarVT (LoadOp (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), (i64 0)), - (SUBREG_TO_REG (i64 0), (ROXLoadInst GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), SubReg)>; + (SUBREG_TO_REG (ROXLoadInst GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), SubReg)>; // Undef equivalents of the patterns above. def : Pat <(VT (vec_ins_or_scal_vec (ScalarVT (LoadOp (Addr GPR64sp:$Rn, AddrImm:$offset))))), - (SUBREG_TO_REG (i64 0), (LoadInst GPR64sp:$Rn, AddrImm:$offset), SubReg)>; + (SUBREG_TO_REG (LoadInst GPR64sp:$Rn, AddrImm:$offset), SubReg)>; def : Pat <(VT (vec_ins_or_scal_vec (ScalarVT (LoadOp (UnscaledAddr GPR64sp:$Rn, simm9:$offset))))), - (SUBREG_TO_REG (i64 0), (UnscaledLoadInst GPR64sp:$Rn, simm9:$offset), SubReg)>; + (SUBREG_TO_REG (UnscaledLoadInst GPR64sp:$Rn, simm9:$offset), SubReg)>; def : Pat <(VT (vec_ins_or_scal_vec (ScalarVT (LoadOp (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))))), - (SUBREG_TO_REG (i64 0), (ROWLoadInst GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), SubReg)>; + (SUBREG_TO_REG (ROWLoadInst GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), SubReg)>; def : Pat <(VT (vec_ins_or_scal_vec (ScalarVT (LoadOp (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))))), - (SUBREG_TO_REG (i64 0), (ROXLoadInst GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), SubReg)>; + (SUBREG_TO_REG (ROXLoadInst GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), SubReg)>; } multiclass LoadInsertPatterns { // 8-bit loads. def : Pat<(OutTy (OuterOp (InnerTy (LoadOp8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), - (SUBREG_TO_REG (i64 0), (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>; + (SUBREG_TO_REG (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))), - (SUBREG_TO_REG (i64 0), (LDURBi GPR64sp:$Rn, simm9:$offset), bsub)>; + (SUBREG_TO_REG (LDURBi GPR64sp:$Rn, simm9:$offset), bsub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp8 (ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$extend))))), - (SUBREG_TO_REG (i64 0), (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$extend), bsub)>; + (SUBREG_TO_REG (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$extend), bsub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp8 (ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$extend))))), - (SUBREG_TO_REG (i64 0), (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$extend), bsub)>; + (SUBREG_TO_REG (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$extend), bsub)>; // 16-bit loads. def : Pat<(OutTy (OuterOp (InnerTy (LoadOp16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), - (SUBREG_TO_REG (i64 0), (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>; + (SUBREG_TO_REG (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))), - (SUBREG_TO_REG (i64 0), (LDURHi GPR64sp:$Rn, simm9:$offset), hsub)>; + (SUBREG_TO_REG (LDURHi GPR64sp:$Rn, simm9:$offset), hsub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp16 (ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$extend))))), - (SUBREG_TO_REG (i64 0), (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$extend), hsub)>; + (SUBREG_TO_REG (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$extend), hsub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp16 (ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$extend))))), - (SUBREG_TO_REG (i64 0), (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$extend), hsub)>; + (SUBREG_TO_REG (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$extend), hsub)>; } // Extended multiclass that includes 32-bit loads in addition to 8-bit and 16-bit. @@ -4481,13 +4479,13 @@ multiclass ExtLoad8_16_32AllModes; + (SUBREG_TO_REG (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))), - (SUBREG_TO_REG (i64 0), (LDURSi GPR64sp:$Rn, simm9:$offset), ssub)>; + (SUBREG_TO_REG (LDURSi GPR64sp:$Rn, simm9:$offset), ssub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp32 (ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$extend))))), - (SUBREG_TO_REG (i64 0), (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$extend), ssub)>; + (SUBREG_TO_REG (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$extend), ssub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp32 (ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$extend))))), - (SUBREG_TO_REG (i64 0), (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$extend), ssub)>; + (SUBREG_TO_REG (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$extend), ssub)>; } // Instantiate bitconvert patterns for floating-point types. @@ -7058,7 +7056,7 @@ def : Pat<(v1i64 (AArch64vashr (v1i64 V64:$Rn), (i32 63))), // f16 -> i16 conversions leave the bit pattern in a f32 class F16ToI16ScalarPat : Pat<(f32 (cvt_isd (f16 FPR16:$Rn))), - (f32 (SUBREG_TO_REG (i64 0), (instr FPR16:$Rn), hsub))>; + (f32 (SUBREG_TO_REG (instr FPR16:$Rn), hsub))>; let Predicates = [HasFullFP16] in { def : F16ToI16ScalarPat; @@ -7460,7 +7458,7 @@ multiclass AddSubHNPatterns; + (ADDHN2 (SUBREG_TO_REG V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; def : Pat<(VT64 (trunc (VT128 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 Shift))))), (SUBHN V128:$Rn, V128:$Rm)>; @@ -7468,7 +7466,7 @@ multiclass AddSubHNPatterns; + (SUBHN2 (SUBREG_TO_REG V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; // xor by -1 can also be treated as sub def : Pat<(VT64 (trunc (VT128 (AArch64vlshr (xor V128:$Rn, immAllOnesV:$Rm), (i32 Shift))))), @@ -7477,7 +7475,7 @@ multiclass AddSubHNPatterns; + (SUBHN2 (SUBREG_TO_REG V64:$Rd, dsub), V128:$Rm, V128:$Rn)>; } defm : AddSubHNPatterns { V64:$Rm, (i32 imm:$imm))), (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, - (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), + (SUBREG_TO_REG V64:$Rm, dsub), (AdjustExtImm imm:$imm)), dsub)>; } @@ -7896,36 +7894,32 @@ def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx), def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx)))), (i64 0xff))), - (SUBREG_TO_REG (i64 0), (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx)), sub_32)>; + (SUBREG_TO_REG (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx)), sub_32)>; def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx)))), (i64 0xffff))), - (SUBREG_TO_REG (i64 0), (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx)), sub_32)>; + (SUBREG_TO_REG (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx)), sub_32)>; defm INS : SIMDIns; def : Pat<(v16i8 (vec_ins_or_scal_vec GPR32:$Rn)), - (SUBREG_TO_REG (i32 0), - (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; + (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; def : Pat<(v8i8 (vec_ins_or_scal_vec GPR32:$Rn)), - (SUBREG_TO_REG (i32 0), - (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; + (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; // The top bits will be zero from the FMOVWSr def : Pat<(v8i8 (bitconvert (i64 (zext GPR32:$Rn)))), - (SUBREG_TO_REG (i32 0), (f32 (FMOVWSr GPR32:$Rn)), ssub)>; + (SUBREG_TO_REG (f32 (FMOVWSr GPR32:$Rn)), ssub)>; def: Pat<(f64 (bitconvert (i64 (zext (i32 (bitconvert (f32 FPR32:$Rn))))))), - (SUBREG_TO_REG (i32 0), (f32 (FMOVSr FPR32:$Rn)), ssub)>; + (SUBREG_TO_REG (f32 (FMOVSr FPR32:$Rn)), ssub)>; def: Pat<(f32 (bitconvert (i32 (trunc (i64 (bitconvert (f64 FPR64:$Rn))))))), (f32 (EXTRACT_SUBREG FPR64:$Rn, ssub))>; def : Pat<(v8i16 (vec_ins_or_scal_vec GPR32:$Rn)), - (SUBREG_TO_REG (i32 0), - (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; + (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; def : Pat<(v4i16 (vec_ins_or_scal_vec GPR32:$Rn)), - (SUBREG_TO_REG (i32 0), - (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; + (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; def : Pat<(v2i32 (vec_ins_or_scal_vec GPR32:$Rn)), (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), GPR32:$Rn, ssub)>; @@ -8105,7 +8099,7 @@ multiclass Neon_INS_elt_pattern; // Extracting from another NEON vector @@ -8123,12 +8117,12 @@ multiclass Neon_INS_elt_pattern; + (VT128 (SUBREG_TO_REG V64:$Rn, dsub)), imm:$Immn)>; def : Pat<(VT64 (vector_insert V64:$src, (VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))), (i64 imm:$Immd))), - (EXTRACT_SUBREG (INS (VT128 (SUBREG_TO_REG (i64 0), V64:$src, dsub)), + (EXTRACT_SUBREG (INS (VT128 (SUBREG_TO_REG V64:$src, dsub)), imm:$Immd, V128:$Rn, imm:$Immn), dsub)>; @@ -8136,8 +8130,8 @@ multiclass Neon_INS_elt_pattern; } @@ -8180,7 +8174,6 @@ multiclass Neon_INS_elt_ext_pattern; @@ -8190,13 +8183,12 @@ multiclass Neon_INS_elt_ext_pattern; def : Pat<(OutVT (scalar_to_vector (i32 (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))))), (EXTRACT_SUBREG (VT128 (SUBREG_TO_REG - (i64 0), (DUP V128:$Rn, imm:$Immn), DUPSub)), dsub)>; @@ -8219,9 +8211,9 @@ def : Pat<(f64 (bitconvert (i64 (vector_extract v2i64:$src, (i64 0))))), // f32 bitcast(vector_extract(v4i32 src, lane)) -> DUPi32(src, lane) def : Pat<(f32 (bitconvert (i32 (vector_extract v16i8:$src, imm:$Immd)))), - (EXTRACT_SUBREG (v16i8 (SUBREG_TO_REG (i64 0), (DUPi8 V128:$src, imm:$Immd), bsub)), ssub)>; + (EXTRACT_SUBREG (v16i8 (SUBREG_TO_REG (DUPi8 V128:$src, imm:$Immd), bsub)), ssub)>; def : Pat<(f32 (bitconvert (i32 (vector_extract v8i16:$src, imm:$Immd)))), - (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (i64 0), (DUPi16 V128:$src, imm:$Immd), hsub)), ssub)>; + (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (DUPi16 V128:$src, imm:$Immd), hsub)), ssub)>; def : Pat<(f32 (bitconvert (i32 (vector_extract v4i32:$src, imm:$Immd)))), (DUPi32 V128:$src, imm:$Immd)>; def : Pat<(f64 (bitconvert (i64 (vector_extract v2i64:$src, imm:$Immd)))), @@ -8261,7 +8253,7 @@ multiclass ConcatPatd register mov, which // will implicitly clear the upper bits. def : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), immAllZerosV)), - (SUBREG_TO_REG (i64 0), (FMOVDr V64:$Rn), dsub)>; + (SUBREG_TO_REG (FMOVDr V64:$Rn), dsub)>; // If the high lanes are undef we can just ignore them: def : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)), @@ -8300,17 +8292,17 @@ defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", AArch64fminnmv>; defm FMINV : SIMDFPAcrossLanes<0b01111, 1, "fminv", AArch64fminv>; def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (sext (v8i8 V64:$op))))), (i64 0))), - (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (i64 0), (SADDLVv8i8v V64:$op), hsub)), ssub)>; + (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (SADDLVv8i8v V64:$op), hsub)), ssub)>; def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (zext (v8i8 V64:$op))))), (i64 0))), - (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub)), ssub)>; + (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (UADDLVv8i8v V64:$op), hsub)), ssub)>; def : Pat<(v8i16 (AArch64uaddv (v8i16 (sext (v8i8 V64:$op))))), - (v8i16 (SUBREG_TO_REG (i64 0), (SADDLVv8i8v V64:$op), hsub))>; + (v8i16 (SUBREG_TO_REG (SADDLVv8i8v V64:$op), hsub))>; def : Pat<(v8i16 (AArch64uaddv (v8i16 (zext (v8i8 V64:$op))))), - (v8i16 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub))>; + (v8i16 (SUBREG_TO_REG (UADDLVv8i8v V64:$op), hsub))>; def : Pat<(v4i32 (AArch64uaddv (v4i32 (sext (v4i16 V64:$op))))), - (v4i32 (SUBREG_TO_REG (i64 0), (SADDLVv4i16v V64:$op), ssub))>; + (v4i32 (SUBREG_TO_REG (SADDLVv4i16v V64:$op), ssub))>; def : Pat<(v4i32 (AArch64uaddv (v4i32 (zext (v4i16 V64:$op))))), - (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv4i16v V64:$op), ssub))>; + (v4i32 (SUBREG_TO_REG (UADDLVv4i16v V64:$op), ssub))>; multiclass SIMDAcrossLaneLongPairIntrinsic { // Patterns for addv(addlp(x)) ==> addlv @@ -8356,29 +8348,29 @@ defm : SIMDAcrossLaneLongPairIntrinsicGISel<"UADDLV", AArch64uaddlp>; defm : SIMDAcrossLaneLongPairIntrinsicGISel<"SADDLV", AArch64saddlp>; def : Pat<(v2i64 (AArch64uaddlv (v4i32 (AArch64uaddlp (v8i16 V128:$op))))), - (v2i64 (SUBREG_TO_REG (i64 0), (UADDLVv8i16v V128:$op), ssub))>; + (v2i64 (SUBREG_TO_REG (UADDLVv8i16v V128:$op), ssub))>; def : Pat<(v4i32 (AArch64uaddlv (v8i16 (AArch64uaddlp (v16i8 V128:$op))))), - (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv16i8v V128:$op), hsub))>; + (v4i32 (SUBREG_TO_REG (UADDLVv16i8v V128:$op), hsub))>; def : Pat<(v4i32 (AArch64uaddlv (v4i16 (AArch64uaddlp (v8i8 V64:$op))))), - (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub))>; + (v4i32 (SUBREG_TO_REG (UADDLVv8i8v V64:$op), hsub))>; multiclass SIMDAcrossLaneLongReductionIntrinsic { def : Pat<(v4i32 (addlv (v8i8 V64:$Rn))), - (v4i32 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v8i8v") V64:$Rn), hsub))>; + (v4i32 (SUBREG_TO_REG (!cast(Opc#"v8i8v") V64:$Rn), hsub))>; def : Pat<(v4i32 (addlv (v4i16 V64:$Rn))), - (v4i32 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v4i16v") V64:$Rn), ssub))>; + (v4i32 (SUBREG_TO_REG (!cast(Opc#"v4i16v") V64:$Rn), ssub))>; def : Pat<(v4i32 (addlv (v16i8 V128:$Rn))), - (v4i32 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v16i8v") V128:$Rn), hsub))>; + (v4i32 (SUBREG_TO_REG (!cast(Opc#"v16i8v") V128:$Rn), hsub))>; def : Pat<(v4i32 (addlv (v8i16 V128:$Rn))), - (v4i32 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v8i16v") V128:$Rn), ssub))>; + (v4i32 (SUBREG_TO_REG (!cast(Opc#"v8i16v") V128:$Rn), ssub))>; def : Pat<(v2i64 (addlv (v4i32 V128:$Rn))), - (v2i64 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v4i32v") V128:$Rn), dsub))>; + (v2i64 (SUBREG_TO_REG (!cast(Opc#"v4i32v") V128:$Rn), dsub))>; } defm : SIMDAcrossLaneLongReductionIntrinsic<"UADDLV", AArch64uaddlv>; @@ -8667,19 +8659,19 @@ def : Pat<(v8bf16 immAllZerosV), (MOVIv2d_ns (i32 0))>; // Prefer NEON instructions when zeroing ZPRs because they are potentially zero-latency. let AddedComplexity = 5 in { -def : Pat<(nxv2i64 (splat_vector (i64 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv4i32 (splat_vector (i32 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv8i16 (splat_vector (i32 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv16i8 (splat_vector (i32 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv2f64 (splat_vector (f64 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv2f32 (splat_vector (f32 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv4f32 (splat_vector (f32 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv2f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv4f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv8f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv2bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv4bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv8bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv2i64 (splat_vector (i64 0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv4i32 (splat_vector (i32 0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv8i16 (splat_vector (i32 0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv16i8 (splat_vector (i32 0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv2f64 (splat_vector (f64 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv2f32 (splat_vector (f32 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv4f32 (splat_vector (f32 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv2f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv4f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv8f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv2bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv4bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv8bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; } def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>; @@ -8858,12 +8850,12 @@ multiclass FMLSIndexedAfterNegPatterns { (i64 0))), VectorIndexS:$idx)))), (FMLSv2i32_indexed V64:$Rd, V64:$Rn, - (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), + (SUBREG_TO_REG V64:$Rm, dsub), VectorIndexS:$idx)>; def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (AArch64dup (f32 (fneg FPR32Op:$Rm))))), (FMLSv2i32_indexed V64:$Rd, V64:$Rn, - (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; + (SUBREG_TO_REG FPR32Op:$Rm, ssub), (i64 0))>; // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit // and DUP scalar. @@ -8879,12 +8871,12 @@ multiclass FMLSIndexedAfterNegPatterns { (i64 0))), VectorIndexS:$idx)))), (FMLSv4i32_indexed V128:$Rd, V128:$Rn, - (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), + (SUBREG_TO_REG V64:$Rm, dsub), VectorIndexS:$idx)>; def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (AArch64dup (f32 (fneg FPR32Op:$Rm))))), (FMLSv4i32_indexed V128:$Rd, V128:$Rn, - (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; + (SUBREG_TO_REG FPR32Op:$Rm, ssub), (i64 0))>; // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar // (DUPLANE from 64-bit would be trivial). @@ -8896,7 +8888,7 @@ multiclass FMLSIndexedAfterNegPatterns { def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (AArch64dup (f64 (fneg FPR64Op:$Rm))))), (FMLSv2i64_indexed V128:$Rd, V128:$Rn, - (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>; + (SUBREG_TO_REG FPR64Op:$Rm, dsub), (i64 0))>; // 2 variants for 32-bit scalar version: extract from .2s or from .4s def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), @@ -8910,7 +8902,7 @@ multiclass FMLSIndexedAfterNegPatterns { (i64 0))), VectorIndexS:$idx))), (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn, - (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>; + (SUBREG_TO_REG V64:$Rm, dsub), VectorIndexS:$idx)>; // 1 variant for 64-bit scalar version: extract from .1d or from .2d def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn), @@ -9432,7 +9424,7 @@ def : InstAlias<"uxtl2 $dst.2d, $src1.4s", let Predicates = [HasNEON] in { def : Pat<(f32 (any_fpextend (bf16 FPR16:$Rn))), (f32 (EXTRACT_SUBREG - (v4i32 (SHLLv4i16 (v4i16 (SUBREG_TO_REG (i64 0), (bf16 FPR16:$Rn), hsub)))), + (v4i32 (SHLLv4i16 (v4i16 (SUBREG_TO_REG (bf16 FPR16:$Rn), hsub)))), ssub))>; def : Pat<(v4f32 (any_fpextend (v4bf16 V64:$Rn))), (SHLLv4i16 V64:$Rn)>; @@ -9443,7 +9435,7 @@ def : Pat<(v4f32 (any_fpextend (extract_high_v8bf16 (v8bf16 V128:$Rn)))), def : Pat<(f32 (any_fpextend (bf16 FPR16:$Rn))), (f32 (COPY_TO_REGCLASS (i32 (UBFMWri (COPY_TO_REGCLASS - (f32 (SUBREG_TO_REG (i32 0), (bf16 FPR16:$Rn), hsub)), + (f32 (SUBREG_TO_REG (bf16 FPR16:$Rn), hsub)), GPR32), (i64 16), (i64 15))), FPR32))>; @@ -9768,7 +9760,7 @@ class Ld1Lane64IdxOpPat; @@ -9808,7 +9800,7 @@ class Ld1Lane64Pat; @@ -9856,7 +9848,7 @@ class St1Lane64Pat; def : St1Lane64Pat; @@ -9872,13 +9864,13 @@ multiclass St1LanePost64Pat; def : Pat<(scalar_store (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), GPR64sp:$Rn, GPR64:$Rm), - (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), + (ST1 (SUBREG_TO_REG VecListOne64:$Vt, dsub), VecIndex:$idx, GPR64sp:$Rn, $Rm)>; } @@ -10002,7 +9994,7 @@ def : Pat<(i64 (anyext GPR32:$src)), // When we need to explicitly zero-extend, we use a 32-bit MOV instruction and // then assert the extension has happened. def : Pat<(i64 (zext GPR32:$src)), - (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>; + (SUBREG_TO_REG (ORRWrs WZR, GPR32:$src, 0), sub_32)>; // To sign extend, we use a signed bitfield move instruction (SBFM) on the // containing super-reg. @@ -10923,7 +10915,7 @@ class NTStore64Pat : Pat<(nontemporalstore (VT FPR64:$Rt), (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)), (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub), - (DUPi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)), + (DUPi32 (SUBREG_TO_REG FPR64:$Rt, dsub), (i64 1)), GPR64sp:$Rn, simm7s4:$offset)>; // FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64? diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp index 6d7c986eccffc..21ff921da9b8a 100644 --- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp +++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp @@ -26,14 +26,14 @@ // 4. Remove redundant ORRWrs which is generated by zero-extend. // // %3:gpr32 = ORRWrs $wzr, %2, 0 -// %4:gpr64 = SUBREG_TO_REG 0, %3, %subreg.sub_32 +// %4:gpr64 = SUBREG_TO_REG %3, %subreg.sub_32 // // If AArch64's 32-bit form of instruction defines the source operand of // ORRWrs, we can remove the ORRWrs because the upper 32 bits of the source // operand are set to zero. // // 5. %reg = INSERT_SUBREG %reg(tied-def 0), %subreg, subidx -// ==> %reg:subidx = SUBREG_TO_REG 0, %subreg, subidx +// ==> %reg:subidx = SUBREG_TO_REG %subreg, subidx // // 6. %intermediate:gpr32 = COPY %src:fpr128 // %dst:fpr128 = INSvi32gpr %dst_vec:fpr128, dst_index, %intermediate:gpr32 @@ -281,7 +281,7 @@ bool AArch64MIPeepholeOpt::visitORR(MachineInstr &MI) { // Check this ORR comes from below zero-extend pattern. // // def : Pat<(i64 (zext GPR32:$src)), - // (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>; + // (SUBREG_TO_REG (ORRWrs WZR, GPR32:$src, 0), sub_32)>; if (MI.getOperand(3).getImm() != 0) return false; @@ -365,7 +365,7 @@ bool AArch64MIPeepholeOpt::visitINSERT(MachineInstr &MI) { // Check this INSERT_SUBREG comes from below zero-extend pattern. // // From %reg = INSERT_SUBREG %reg(tied-def 0), %subreg, subidx - // To %reg:subidx = SUBREG_TO_REG 0, %subreg, subidx + // To %reg:subidx = SUBREG_TO_REG %subreg, subidx // // We're assuming the first operand to INSERT_SUBREG is irrelevant because a // COPY would destroy the upper part of the register anyway @@ -396,7 +396,6 @@ bool AArch64MIPeepholeOpt::visitINSERT(MachineInstr &MI) { MachineInstr *SubregMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(TargetOpcode::SUBREG_TO_REG), DstReg) - .addImm(0) .add(MI.getOperand(2)) .add(MI.getOperand(3)); LLVM_DEBUG(dbgs() << MI << " replace by:\n: " << *SubregMI << "\n"); @@ -541,7 +540,7 @@ bool AArch64MIPeepholeOpt::checkMovImmInstr(MachineInstr &MI, SubregToRegMI = nullptr; if (MovMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) { SubregToRegMI = MovMI; - MovMI = MRI->getUniqueVRegDef(MovMI->getOperand(2).getReg()); + MovMI = MRI->getUniqueVRegDef(MovMI->getOperand(1).getReg()); if (!MovMI) return false; } @@ -812,7 +811,6 @@ bool AArch64MIPeepholeOpt::visitUBFMXri(MachineInstr &MI) { .addImm(Imms); BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::SUBREG_TO_REG), DstReg64) - .addImm(0) .addReg(DstReg32) .addImm(AArch64::sub_32); MI.eraseFromParent(); @@ -851,10 +849,10 @@ bool AArch64MIPeepholeOpt::visitCopy(MachineInstr &MI) { // Look for SUBREG_TO_REG(ORRWrr(WZR, COPY(X.sub_32))) auto getUXTWSrcReg = [&](MachineInstr *SrcMI) -> Register { if (SrcMI->getOpcode() != AArch64::SUBREG_TO_REG || - SrcMI->getOperand(3).getImm() != AArch64::sub_32 || - !MRI->hasOneNonDBGUse(SrcMI->getOperand(2).getReg())) + SrcMI->getOperand(2).getImm() != AArch64::sub_32 || + !MRI->hasOneNonDBGUse(SrcMI->getOperand(1).getReg())) return AArch64::NoRegister; - MachineInstr *Orr = MRI->getUniqueVRegDef(SrcMI->getOperand(2).getReg()); + MachineInstr *Orr = MRI->getUniqueVRegDef(SrcMI->getOperand(1).getReg()); if (!Orr || Orr->getOpcode() != AArch64::ORRWrr || Orr->getOperand(1).getReg() != AArch64::WZR || !MRI->hasOneNonDBGUse(Orr->getOperand(2).getReg())) diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 36a4b553f22c0..51b260755576a 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -3638,9 +3638,9 @@ let Predicates = [HasSVE_or_SME] in { def : Pat<(i32 (and (vector_extract nxv8i16:$vec, VectorIndexH:$index), 0xffff)), (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>; def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract nxv16i8:$vec, VectorIndexB:$index)))), (i64 0xff))), - (SUBREG_TO_REG (i64 0), (i32 (UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)), sub_32)>; + (SUBREG_TO_REG (i32 (UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)), sub_32)>; def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract nxv8i16:$vec, VectorIndexH:$index)))), (i64 0xffff))), - (SUBREG_TO_REG (i64 0), (i32 (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)), sub_32)>; + (SUBREG_TO_REG (i32 (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)), sub_32)>; } // End HasNEON // Extract first element from vector. diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index 557d5c2f8bc89..38e58481e2f71 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -1071,7 +1071,6 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, Register PromoteReg = MRI.createVirtualRegister(PromotionRC); BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG), PromoteReg) - .addImm(0) .addUse(SrcReg) .addImm(SubReg); MachineOperand &RegOp = I.getOperand(1); @@ -2888,7 +2887,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { BuildMI(MBB, I.getIterator(), I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG)) .addDef(SrcReg) - .addImm(0) .addUse(I.getOperand(2).getReg()) .addImm(AArch64::sub_32); RBI.constrainGenericRegister(I.getOperand(2).getReg(), @@ -3056,7 +3054,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { // Generate a SUBREG_TO_REG to extend it. MIB.setInsertPt(MIB.getMBB(), std::next(LdSt.getIterator())); MIB.buildInstr(AArch64::SUBREG_TO_REG, {OldDst}, {}) - .addImm(0) .addUse(NewDst) .addImm(SubReg); auto SubRegRC = getRegClassForTypeOnBank(MRI.getType(OldDst), RB); @@ -3131,7 +3128,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { MIB.setInsertPt(MIB.getMBB(), std::next(LoadStore->getIterator())); MIB.buildInstr(AArch64::SUBREG_TO_REG, {DstReg}, {}) - .addImm(0) .addUse(LdReg) .addImm(AArch64::sub_32); constrainSelectedInstRegOperands(*LoadStore, TII, TRI, RBI); @@ -3350,7 +3346,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { Register ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass); BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG)) .addDef(ExtSrc) - .addImm(0) .addUse(SrcReg) .addImm(AArch64::sub_32); I.getOperand(1).setReg(ExtSrc); @@ -3414,7 +3409,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { .addImm(0); MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {}) - .addImm(0) .addUse(SubregToRegSrc) .addImm(AArch64::sub_32); @@ -3446,7 +3440,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { } SrcReg = MIB.buildInstr(AArch64::SUBREG_TO_REG, {&AArch64::GPR64RegClass}, {}) - .addImm(0) .addUse(SrcReg) .addImm(AArch64::sub_32) .getReg(0); @@ -3908,17 +3901,15 @@ bool AArch64InstructionSelector::selectMergeValues( MachineInstr &SubRegMI = *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::SUBREG_TO_REG)) .addDef(SubToRegDef) - .addImm(0) .addUse(I.getOperand(1).getReg()) .addImm(AArch64::sub_32); Register SubToRegDef2 = MRI.createVirtualRegister(DstRC); // Need to anyext the second scalar before we can use bfm MachineInstr &SubRegMI2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), - TII.get(TargetOpcode::SUBREG_TO_REG)) - .addDef(SubToRegDef2) - .addImm(0) - .addUse(I.getOperand(2).getReg()) - .addImm(AArch64::sub_32); + TII.get(TargetOpcode::SUBREG_TO_REG)) + .addDef(SubToRegDef2) + .addUse(I.getOperand(2).getReg()) + .addImm(AArch64::sub_32); MachineInstr &BFM = *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::BFMXri)) .addDef(I.getOperand(0).getReg()) @@ -5313,7 +5304,6 @@ bool AArch64InstructionSelector::selectUSMovFromExtend( Register NewReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); MIB.buildInstr(Opcode, {NewReg}, {Src0}).addImm(Lane); ExtI = MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {}) - .addImm(0) .addUse(NewReg) .addImm(AArch64::sub_32); RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); @@ -5582,7 +5572,6 @@ bool AArch64InstructionSelector::selectIndexedExtLoad( if (InsertIntoSubReg) { // Generate a SUBREG_TO_REG. auto SubToReg = MIB.buildInstr(TargetOpcode::SUBREG_TO_REG, {Dst}, {}) - .addImm(0) .addUse(LdMI.getReg(1)) .addImm(InsertIntoSubReg); RBI.constrainGenericRegister( @@ -5874,7 +5863,6 @@ bool AArch64InstructionSelector::tryOptBuildVecToSubregToReg( if (!getSubRegForClass(EltRC, TRI, SubReg)) return false; auto SubregToReg = MIB.buildInstr(AArch64::SUBREG_TO_REG, {Dst}, {}) - .addImm(0) .addUse(EltReg) .addImm(SubReg); I.eraseFromParent(); diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 35b0872dc593c..9d988b5654a6e 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -1496,35 +1496,35 @@ multiclass sve_int_perm_dup_i { def : Pat<(nxv16i8 (splat_vector (i32 (vector_extract (nxv16i8 ZPR:$vec), sve_elm_idx_extdup_b:$index)))), (!cast(NAME # _B) ZPR:$vec, sve_elm_idx_extdup_b:$index)>; def : Pat<(nxv16i8 (splat_vector (i32 (vector_extract (v16i8 V128:$vec), sve_elm_idx_extdup_b:$index)))), - (!cast(NAME # _B) (SUBREG_TO_REG (i64 0), $vec, zsub), sve_elm_idx_extdup_b:$index)>; + (!cast(NAME # _B) (SUBREG_TO_REG $vec, zsub), sve_elm_idx_extdup_b:$index)>; def : Pat<(nxv16i8 (splat_vector (i32 (vector_extract (v8i8 V64:$vec), sve_elm_idx_extdup_b:$index)))), - (!cast(NAME # _B) (SUBREG_TO_REG (i64 0), $vec, dsub), sve_elm_idx_extdup_b:$index)>; + (!cast(NAME # _B) (SUBREG_TO_REG $vec, dsub), sve_elm_idx_extdup_b:$index)>; foreach VT = [nxv8i16, nxv2f16, nxv4f16, nxv8f16, nxv2bf16, nxv4bf16, nxv8bf16] in { def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.Packed ZPR:$vec), sve_elm_idx_extdup_h:$index)))), (!cast(NAME # _H) ZPR:$vec, sve_elm_idx_extdup_h:$index)>; def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.ZSub V128:$vec), sve_elm_idx_extdup_h:$index)))), - (!cast(NAME # _H) (SUBREG_TO_REG (i64 0), $vec, zsub), sve_elm_idx_extdup_h:$index)>; + (!cast(NAME # _H) (SUBREG_TO_REG $vec, zsub), sve_elm_idx_extdup_h:$index)>; def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.DSub V64:$vec), sve_elm_idx_extdup_h:$index)))), - (!cast(NAME # _H) (SUBREG_TO_REG (i64 0), $vec, dsub), sve_elm_idx_extdup_h:$index)>; + (!cast(NAME # _H) (SUBREG_TO_REG $vec, dsub), sve_elm_idx_extdup_h:$index)>; } foreach VT = [nxv4i32, nxv2f32, nxv4f32 ] in { def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.Packed ZPR:$vec), sve_elm_idx_extdup_s:$index)))), (!cast(NAME # _S) ZPR:$vec, sve_elm_idx_extdup_s:$index)>; def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.ZSub V128:$vec), sve_elm_idx_extdup_s:$index)))), - (!cast(NAME # _S) (SUBREG_TO_REG (i64 0), $vec, zsub), sve_elm_idx_extdup_s:$index)>; + (!cast(NAME # _S) (SUBREG_TO_REG $vec, zsub), sve_elm_idx_extdup_s:$index)>; def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.DSub V64:$vec), sve_elm_idx_extdup_s:$index)))), - (!cast(NAME # _S) (SUBREG_TO_REG (i64 0), $vec, dsub), sve_elm_idx_extdup_s:$index)>; + (!cast(NAME # _S) (SUBREG_TO_REG $vec, dsub), sve_elm_idx_extdup_s:$index)>; } foreach VT = [nxv2i64, nxv2f64] in { def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (VT ZPR:$vec), sve_elm_idx_extdup_d:$index)))), (!cast(NAME # _D) ZPR:$vec, sve_elm_idx_extdup_d:$index)>; def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.ZSub V128:$vec), sve_elm_idx_extdup_d:$index)))), - (!cast(NAME # _D) (SUBREG_TO_REG (i64 0), $vec, zsub), sve_elm_idx_extdup_d:$index)>; + (!cast(NAME # _D) (SUBREG_TO_REG $vec, zsub), sve_elm_idx_extdup_d:$index)>; def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.DSub V64:$vec), sve_elm_idx_extdup_d:$index)))), - (!cast(NAME # _D) (SUBREG_TO_REG (i64 0), $vec, dsub), sve_elm_idx_extdup_d:$index)>; + (!cast(NAME # _D) (SUBREG_TO_REG $vec, dsub), sve_elm_idx_extdup_d:$index)>; } // When extracting from an unpacked vector the index must be scaled to account @@ -6329,7 +6329,7 @@ multiclass sve_int_index_ir(NAME # "_D") (i64 0), (!cast("MOVi64imm") $imm))>; def : Pat<(nxv2i64 (step_vector i64imm_32bit_tgt:$imm)), - (!cast(NAME # "_D") (i64 0), (SUBREG_TO_REG (i64 0), (!cast("MOVi32imm") (!cast("trunc_imm") $imm)), sub_32))>; + (!cast(NAME # "_D") (i64 0), (SUBREG_TO_REG (!cast("MOVi32imm") (!cast("trunc_imm") $imm)), sub_32))>; // add(step_vector(step), dup(X)) -> index(X, step). def : Pat<(add (nxv16i8 (step_vector_oneuse i8:$imm)), (nxv16i8 (splat_vector(simm5_8b:$imm5)))), @@ -6341,7 +6341,7 @@ multiclass sve_int_index_ir(NAME # "_D") simm5_64b:$imm5, (!cast("MOVi64imm") $imm))>; def : Pat<(add (nxv2i64 (step_vector_oneuse i64imm_32bit_tgt:$imm)), (nxv2i64 (splat_vector(simm5_64b:$imm5)))), - (!cast(NAME # "_D") simm5_64b:$imm5, (SUBREG_TO_REG (i64 0), (!cast("MOVi32imm") (!cast("trunc_imm") $imm)), sub_32))>; + (!cast(NAME # "_D") simm5_64b:$imm5, (SUBREG_TO_REG (!cast("MOVi32imm") (!cast("trunc_imm") $imm)), sub_32))>; // mul(step_vector(1), dup(Y)) -> index(0, Y). def : Pat<(mulop (nxv16i1 (SVEAllActive)), (nxv16i8 (step_vector_oneuse (i8 1))), (nxv16i8 (splat_vector(i32 GPR32:$Rm)))), @@ -6435,7 +6435,7 @@ multiclass sve_int_index_rr { def : Pat<(add (nxv2i64 (step_vector_oneuse i64:$imm)), (nxv2i64 (splat_vector(i64 GPR64:$Rn)))), (!cast(NAME # "_D") GPR64:$Rn, (!cast("MOVi64imm") $imm))>; def : Pat<(add (nxv2i64 (step_vector_oneuse i64imm_32bit_tgt:$imm)), (nxv2i64 (splat_vector(i64 GPR64:$Rn)))), - (!cast(NAME # "_D") GPR64:$Rn, (SUBREG_TO_REG (i64 0), (!cast("MOVi32imm") (!cast("trunc_imm") $imm)), sub_32))>; + (!cast(NAME # "_D") GPR64:$Rn, (SUBREG_TO_REG (!cast("MOVi32imm") (!cast("trunc_imm") $imm)), sub_32))>; // add(mul(step_vector(1), dup(Y)), dup(X)) -> index(X, Y). def : Pat<(add (mulop (nxv16i1 (SVEAllActive)), (nxv16i8 (step_vector_oneuse (i8 1))), (nxv16i8 (splat_vector(i32 GPR32:$Rm)))), (nxv16i8 (splat_vector(i32 GPR32:$Rn)))), diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index dc62a09f942e2..e2450490c83b8 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -7403,29 +7403,25 @@ def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>; let Predicates = [HasNEON] in { def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)), (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG - (SHA1H (SUBREG_TO_REG (i64 0), - (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)), + (SHA1H (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)), ssub_0)), ssub_0)), GPR)>; def : Pat<(v4i32 (int_arm_neon_sha1c v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)), (SHA1C v4i32:$hash_abcd, - (SUBREG_TO_REG (i64 0), - (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), + (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0), v4i32:$wk)>; def : Pat<(v4i32 (int_arm_neon_sha1m v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)), (SHA1M v4i32:$hash_abcd, - (SUBREG_TO_REG (i64 0), - (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), + (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0), v4i32:$wk)>; def : Pat<(v4i32 (int_arm_neon_sha1p v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)), (SHA1P v4i32:$hash_abcd, - (SUBREG_TO_REG (i64 0), - (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), + (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0), v4i32:$wk)>; } diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td index bdacf9cc3a6ab..3d2050e26ca0d 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.td +++ b/llvm/lib/Target/BPF/BPFInstrInfo.td @@ -1343,17 +1343,17 @@ let Predicates = [BPFHasALU32] in { } def : Pat<(i64 (zextloadi8 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>; + (SUBREG_TO_REG (LDB32 ADDRri:$src), sub_32)>; def : Pat<(i64 (zextloadi16 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>; + (SUBREG_TO_REG (LDH32 ADDRri:$src), sub_32)>; def : Pat<(i64 (zextloadi32 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>; + (SUBREG_TO_REG (LDW32 ADDRri:$src), sub_32)>; def : Pat<(i64 (extloadi8 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>; + (SUBREG_TO_REG (LDB32 ADDRri:$src), sub_32)>; def : Pat<(i64 (extloadi16 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>; + (SUBREG_TO_REG (LDH32 ADDRri:$src), sub_32)>; def : Pat<(i64 (extloadi32 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>; + (SUBREG_TO_REG (LDW32 ADDRri:$src), sub_32)>; let Predicates = [BPFHasLoadAcqStoreRel] in { foreach P = [[relaxed_load, LDW32], diff --git a/llvm/lib/Target/BPF/BPFMIPeephole.cpp b/llvm/lib/Target/BPF/BPFMIPeephole.cpp index 6275d5b7721c6..b8e4db78955f5 100644 --- a/llvm/lib/Target/BPF/BPFMIPeephole.cpp +++ b/llvm/lib/Target/BPF/BPFMIPeephole.cpp @@ -227,7 +227,8 @@ bool BPFMIPeephole::eliminateZExtSeq() { } BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), DstReg) - .addImm(0).addReg(SubReg).addImm(BPF::sub_32); + .addReg(SubReg) + .addImm(BPF::sub_32); SllMI->eraseFromParent(); MovMI->eraseFromParent(); @@ -278,7 +279,8 @@ bool BPFMIPeephole::eliminateZExt() { // Build a SUBREG_TO_REG instruction. BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), dst) - .addImm(0).addReg(src).addImm(BPF::sub_32); + .addReg(src) + .addImm(BPF::sub_32); ToErase = &MI; Eliminated = true; diff --git a/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp b/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp index c9b1cbc7ae959..9d6de2044b2b6 100644 --- a/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp +++ b/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp @@ -197,7 +197,7 @@ void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, // We can optimize such a pattern: // %1:gpr = LD_imm64 @"llvm.s:0:4$0:2" // %2:gpr32 = LDW32 %1:gpr, 0 - // %3:gpr = SUBREG_TO_REG 0, %2:gpr32, %subreg.sub_32 + // %3:gpr = SUBREG_TO_REG %2:gpr32, %subreg.sub_32 // %4:gpr = ADD_rr %0:gpr, %3:gpr // or similar patterns below for non-alu32 case. auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index 4f603baab573f..7b050c3715f6c 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -7258,7 +7258,6 @@ emitPseudoXVINSGR2VR(MachineInstr &MI, MachineBasicBlock *BB, .addImm(Idx); BuildMI(*BB, MI, DL, TII->get(LoongArch::SUBREG_TO_REG), XDst) - .addImm(0) .addReg(ScratchSubReg2) .addImm(LoongArch::sub_128); } else { diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td index fa4b720e7ba98..92ba17f5707a1 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td @@ -1731,17 +1731,17 @@ def : Pat<(loongarch_xvinsve0 v8f32:$xd, v8f32:$xj, uimm3:$imm), def : Pat<(loongarch_xvinsve0 v4f64:$xd, v4f64:$xj, uimm2:$imm), (XVINSVE0_D v4f64:$xd, v4f64:$xj, uimm2:$imm)>; def : Pat<(vector_insert v8f32:$xd, FPR32:$fj, uimm3:$imm), - (XVINSVE0_W v8f32:$xd, (SUBREG_TO_REG(i64 0), FPR32:$fj, sub_32), + (XVINSVE0_W v8f32:$xd, (SUBREG_TO_REG FPR32:$fj, sub_32), uimm3:$imm)>; def : Pat<(vector_insert v4f64:$xd, FPR64:$fj, uimm2:$imm), - (XVINSVE0_D v4f64:$xd, (SUBREG_TO_REG(i64 0), FPR64:$fj, sub_64), + (XVINSVE0_D v4f64:$xd, (SUBREG_TO_REG FPR64:$fj, sub_64), uimm2:$imm)>; // scalar_to_vector def : Pat<(v8f32 (scalar_to_vector FPR32:$fj)), - (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32)>; + (SUBREG_TO_REG FPR32:$fj, sub_32)>; def : Pat<(v4f64 (scalar_to_vector FPR64:$fj)), - (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64)>; + (SUBREG_TO_REG FPR64:$fj, sub_64)>; // XVPICKVE2GR_W[U] def : Pat<(loongarch_vpick_sext_elt v8i32:$xd, uimm3:$imm, i32), @@ -1926,9 +1926,9 @@ def : Pat<(loongarch_xvreplve0 v8f32:$xj), def : Pat<(loongarch_xvreplve0 v4f64:$xj), (XVREPLVE0_D v4f64:$xj)>; def : Pat<(lasxsplatf32 FPR32:$fj), - (XVREPLVE0_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32))>; + (XVREPLVE0_W (SUBREG_TO_REG FPR32:$fj, sub_32))>; def : Pat<(lasxsplatf64 FPR64:$fj), - (XVREPLVE0_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64))>; + (XVREPLVE0_D (SUBREG_TO_REG FPR64:$fj, sub_64))>; foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in def : Pat<(vt (loongarch_xvreplve0q LASX256:$xj)), (XVREPLVE0_Q LASX256:$xj)>; @@ -1997,7 +1997,7 @@ def : Pat<(fneg (v4f64 LASX256:$xj)), (XVBITREVI_D LASX256:$xj, 63)>; def : Pat<(v8f32 (sint_to_fp v8i32:$vj)), (XVFFINT_S_W v8i32:$vj)>; def : Pat<(v4f64 (sint_to_fp v4i64:$vj)), (XVFFINT_D_L v4i64:$vj)>; def : Pat<(v4f64 (sint_to_fp v4i32:$vj)), - (XVFFINT_D_L (VEXT2XV_D_W (SUBREG_TO_REG (i64 0), v4i32:$vj, + (XVFFINT_D_L (VEXT2XV_D_W (SUBREG_TO_REG v4i32:$vj, sub_128)))>; def : Pat<(v4f32 (sint_to_fp v4i64:$vj)), (EXTRACT_SUBREG (XVFCVT_S_D (XVPERMI_D (XVFFINT_D_L v4i64:$vj), 238), @@ -2008,7 +2008,7 @@ def : Pat<(v4f32 (sint_to_fp v4i64:$vj)), def : Pat<(v8f32 (uint_to_fp v8i32:$vj)), (XVFFINT_S_WU v8i32:$vj)>; def : Pat<(v4f64 (uint_to_fp v4i64:$vj)), (XVFFINT_D_LU v4i64:$vj)>; def : Pat<(v4f64 (uint_to_fp v4i32:$vj)), - (XVFFINT_D_LU (VEXT2XV_DU_WU (SUBREG_TO_REG (i64 0), v4i32:$vj, + (XVFFINT_D_LU (VEXT2XV_DU_WU (SUBREG_TO_REG v4i32:$vj, sub_128)))>; def : Pat<(v4f32 (uint_to_fp v4i64:$vj)), (EXTRACT_SUBREG (XVFCVT_S_D (XVPERMI_D (XVFFINT_D_LU v4i64:$vj), 238), @@ -2018,7 +2018,7 @@ def : Pat<(v4f32 (uint_to_fp v4i64:$vj)), // XVFTINTRZ_{W_S/L_D} def : Pat<(v8i32 (fp_to_sint v8f32:$vj)), (XVFTINTRZ_W_S v8f32:$vj)>; def : Pat<(v4i64 (fp_to_sint v4f64:$vj)), (XVFTINTRZ_L_D v4f64:$vj)>; -def : Pat<(v4i64(fp_to_sint v4f32:$vj)), (VEXT2XV_D_W(SUBREG_TO_REG(i64 0), +def : Pat<(v4i64(fp_to_sint v4f32:$vj)), (VEXT2XV_D_W(SUBREG_TO_REG (VFTINTRZ_W_S v4f32:$vj), sub_128))>; def : Pat<(v4i32(fp_to_sint v4f64:$vj)), @@ -2029,7 +2029,7 @@ def : Pat<(v4i32(fp_to_sint v4f64:$vj)), // XVFTINTRZ_{W_SU/L_DU} def : Pat<(v8i32 (fp_to_uint v8f32:$vj)), (XVFTINTRZ_WU_S v8f32:$vj)>; def : Pat<(v4i64 (fp_to_uint v4f64:$vj)), (XVFTINTRZ_LU_D v4f64:$vj)>; -def : Pat<(v4i64(fp_to_uint v4f32:$vj)), (VEXT2XV_DU_WU(SUBREG_TO_REG(i64 0), +def : Pat<(v4i64(fp_to_uint v4f32:$vj)), (VEXT2XV_DU_WU(SUBREG_TO_REG (VFTINTRZ_WU_S v4f32:$vj), sub_128))>; def : Pat<(v4i32(fp_to_uint v4f64:$vj)), diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td index da7b6e833c996..2c06d9f827548 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td @@ -1907,20 +1907,20 @@ def : Pat<(vector_insert v2f64:$vd, (f64 (bitconvert i64:$rj)), uimm1:$imm), foreach imm = 0...3 in { defvar Imm = !shl(imm, 4); def : Pat<(vector_insert v4f32:$vd, FPR32:$fj, imm), - (VEXTRINS_W $vd, (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), Imm)>; + (VEXTRINS_W $vd, (SUBREG_TO_REG FPR32:$fj, sub_32), Imm)>; } foreach imm = 0...1 in { defvar Imm = !shl(imm, 4); def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, imm), - (VEXTRINS_D $vd, (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), Imm)>; + (VEXTRINS_D $vd, (SUBREG_TO_REG FPR64:$fj, sub_64), Imm)>; } // scalar_to_vector def : Pat<(v4f32 (scalar_to_vector FPR32:$fj)), - (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32)>; + (SUBREG_TO_REG FPR32:$fj, sub_32)>; def : Pat<(v2f64 (scalar_to_vector FPR64:$fj)), - (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64)>; + (SUBREG_TO_REG FPR64:$fj, sub_64)>; // VPICKVE2GR_{B/H/W}[U] def : Pat<(loongarch_vpick_sext_elt v16i8:$vd, uimm4:$imm, i8), @@ -2090,9 +2090,9 @@ def : Pat<(loongarch_vreplvei v2f64:$vj, immZExt1:$ui1), // VREPLVEI_{W/D} def : Pat<(lsxsplatf32 FPR32:$fj), - (VREPLVEI_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)>; + (VREPLVEI_W (SUBREG_TO_REG FPR32:$fj, sub_32), 0)>; def : Pat<(lsxsplatf64 FPR64:$fj), - (VREPLVEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>; + (VREPLVEI_D (SUBREG_TO_REG FPR64:$fj, sub_64), 0)>; defm : VstelmPat; defm : VstelmPat; @@ -2547,28 +2547,28 @@ def : Pat<(loongarch_vfrsqrte v2f64:$src), // Vector floating-point conversion def : Pat<(f32 (fceil FPR32:$fj)), (f32 (EXTRACT_SUBREG (VFRINTRP_S (VREPLVEI_W - (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>; + (SUBREG_TO_REG FPR32:$fj, sub_32), 0)), sub_32))>; def : Pat<(f64 (fceil FPR64:$fj)), (f64 (EXTRACT_SUBREG (VFRINTRP_D (VREPLVEI_D - (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>; + (SUBREG_TO_REG FPR64:$fj, sub_64), 0)), sub_64))>; def : Pat<(f32 (ffloor FPR32:$fj)), (f32 (EXTRACT_SUBREG (VFRINTRM_S (VREPLVEI_W - (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>; + (SUBREG_TO_REG FPR32:$fj, sub_32), 0)), sub_32))>; def : Pat<(f64 (ffloor FPR64:$fj)), (f64 (EXTRACT_SUBREG (VFRINTRM_D (VREPLVEI_D - (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>; + (SUBREG_TO_REG FPR64:$fj, sub_64), 0)), sub_64))>; def : Pat<(f32 (ftrunc FPR32:$fj)), (f32 (EXTRACT_SUBREG (VFRINTRZ_S (VREPLVEI_W - (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>; + (SUBREG_TO_REG FPR32:$fj, sub_32), 0)), sub_32))>; def : Pat<(f64 (ftrunc FPR64:$fj)), (f64 (EXTRACT_SUBREG (VFRINTRZ_D (VREPLVEI_D - (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>; + (SUBREG_TO_REG FPR64:$fj, sub_64), 0)), sub_64))>; def : Pat<(f32 (froundeven FPR32:$fj)), (f32 (EXTRACT_SUBREG (VFRINTRNE_S (VREPLVEI_W - (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>; + (SUBREG_TO_REG FPR32:$fj, sub_32), 0)), sub_32))>; def : Pat<(f64 (froundeven FPR64:$fj)), (f64 (EXTRACT_SUBREG (VFRINTRNE_D (VREPLVEI_D - (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>; + (SUBREG_TO_REG FPR64:$fj, sub_64), 0)), sub_64))>; defm : PatVrF; defm : PatVrF; diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.td b/llvm/lib/Target/MSP430/MSP430InstrInfo.td index 546ba6fd8e3b4..f25c96e3109a9 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.td +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.td @@ -398,7 +398,7 @@ def def8 : PatLeaf<(i8 GR8:$src), [{ // In the case of a 8-bit def that is known to implicitly zero-extend, // we can use a SUBREG_TO_REG. def : Pat<(i16 (zext def8:$src)), - (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; + (SUBREG_TO_REG GR8:$src, subreg_8bit)>; def MOV8mc : I8mc<0b0100, (outs), (ins memdst:$dst, cg8imm:$imm), @@ -909,7 +909,7 @@ def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; // anyext def : Pat<(i16 (anyext GR8:$src)), - (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; + (SUBREG_TO_REG GR8:$src, subreg_8bit)>; // truncs def : Pat<(i8 (trunc GR16:$src)), diff --git a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td index 47e3d48921155..810c8ffe13514 100644 --- a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td @@ -229,19 +229,19 @@ def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f def : MipsPat< (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f), (OR64 (SELEQZ64 i64:$t, - (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)), + (SUBREG_TO_REG (SLTi64 i64:$cond, (Plus1 imm:$imm)), sub_32)), (SELNEZ64 i64:$f, - (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)), + (SUBREG_TO_REG (SLTi64 i64:$cond, (Plus1 imm:$imm)), sub_32)))>, ISA_MIPS64R6; def : MipsPat< (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f), (OR64 (SELEQZ64 i64:$t, - (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)), + (SUBREG_TO_REG (SLTiu64 i64:$cond, (Plus1 imm:$imm)), sub_32)), (SELNEZ64 i64:$f, - (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)), + (SUBREG_TO_REG (SLTiu64 i64:$cond, (Plus1 imm:$imm)), sub_32)))>, ISA_MIPS64R6; diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 1a6ebc72684b7..5cb1e12854564 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -1159,10 +1159,8 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { Hi ? SDValue(Res, 0) : ZeroVal, LoVal); Res = CurDAG->getMachineNode( - Mips::SUBREG_TO_REG, DL, MVT::i64, - CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64), - SDValue(Res, 0), - CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64)); + Mips::SUBREG_TO_REG, DL, MVT::i64, SDValue(Res, 0), + CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64)); Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0)); @@ -1265,16 +1263,12 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { if (HiResNonZero) HiRes = CurDAG->getMachineNode( - Mips::SUBREG_TO_REG, DL, MVT::i64, - CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64), - SDValue(HiRes, 0), + Mips::SUBREG_TO_REG, DL, MVT::i64, SDValue(HiRes, 0), CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64)); if (ResNonZero) Res = CurDAG->getMachineNode( - Mips::SUBREG_TO_REG, DL, MVT::i64, - CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64), - SDValue(Res, 0), + Mips::SUBREG_TO_REG, DL, MVT::i64, SDValue(Res, 0), CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64)); // We have 3 cases: diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index 442839975c3f5..001d1326649fe 100644 --- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -3336,7 +3336,6 @@ MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI, : &Mips::MSA128WEvensRegClass); BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) - .addImm(0) .addReg(Fs) .addImm(Mips::sub_lo); BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) @@ -3370,7 +3369,6 @@ MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI, Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) - .addImm(0) .addReg(Fs) .addImm(Mips::sub_64); BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd) @@ -3455,7 +3453,6 @@ MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX( if (IsFP) { Register Wt = RegInfo.createVirtualRegister(VecRC); BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) - .addImm(0) .addReg(SrcValReg) .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo); SrcValReg = Wt; @@ -3611,7 +3608,6 @@ MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI, if(!UsingMips32) { Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass); BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp) - .addImm(0) .addReg(Rs) .addImm(Mips::sub_32); Rs = Tmp; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index a13e0ffc1607b..640b3b48e5707 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -14645,7 +14645,6 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, Register Val64 = MRI.createVirtualRegister(&PPC::G8RCRegClass); if (IsLwat) BuildMI(*BB, MI, DL, TII->get(TargetOpcode::SUBREG_TO_REG), Val64) - .addImm(0) .addReg(ValReg) .addImm(PPC::sub_32); else diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td index bd9a999237c09..1b03a3db7d112 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrP10.td +++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td @@ -1341,7 +1341,7 @@ let Predicates = [PCRelativeMemops, HasFPU] in { (PSTFDpc $FRS, $ga, 0)>; def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))), - (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>; + (SUBREG_TO_REG (PLFDpc $addr, 0), sub_64)>; } let Predicates = [PCRelativeMemops, HasP10Vector] in { @@ -2843,7 +2843,7 @@ let Predicates = [PrefixInstrs, HasFPU] in { def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>; // Prefixed fpext to v2f64 def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)), - (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>; + (SUBREG_TO_REG (PLFD PDForm:$src), sub_64)>; } diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index ed4b58fef3a26..01cc8059f6924 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -2253,7 +2253,7 @@ def VectorExtractions { def AlignValues { dag F32_TO_BE_WORD1 = (v4f32 (XSCVDPSPN $B)); - dag I32_TO_BE_WORD1 = (SUBREG_TO_REG (i64 1), (MTVSRWZ $B), sub_64); + dag I32_TO_BE_WORD1 = (SUBREG_TO_REG (MTVSRWZ $B), sub_64); } // Integer extend helper dags 32 -> 64 @@ -2404,14 +2404,14 @@ def LoadFP { // FP merge dags (for f32 -> v4f32) def MrgFP { - dag LD32A = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64); - dag LD32B = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$B), sub_64); - dag LD32C = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$C), sub_64); - dag LD32D = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$D), sub_64); - dag AC = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64), - (SUBREG_TO_REG (i64 1), $C, sub_64), 0)); - dag BD = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), - (SUBREG_TO_REG (i64 1), $D, sub_64), 0)); + dag LD32A = (SUBREG_TO_REG (LIWZX ForceXForm:$A), sub_64); + dag LD32B = (SUBREG_TO_REG (LIWZX ForceXForm:$B), sub_64); + dag LD32C = (SUBREG_TO_REG (LIWZX ForceXForm:$C), sub_64); + dag LD32D = (SUBREG_TO_REG (LIWZX ForceXForm:$D), sub_64); + dag AC = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG $A, sub_64), + (SUBREG_TO_REG $C, sub_64), 0)); + dag BD = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG $B, sub_64), + (SUBREG_TO_REG $D, sub_64), 0)); dag ABhToFlt = (XVCVDPSP (XXPERMDI $A, $B, 0)); dag ABlToFlt = (XVCVDPSP (XXPERMDI $A, $B, 3)); dag BAhToFlt = (XVCVDPSP (XXPERMDI $B, $A, 0)); @@ -2438,10 +2438,10 @@ def MrgWords { // For big endian, we merge hi doublewords of (A, C) and (B, D), convert // then merge. - dag AC = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$A, sub_64), - (SUBREG_TO_REG (i64 1), f64:$C, sub_64), 0)); - dag BD = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$B, sub_64), - (SUBREG_TO_REG (i64 1), f64:$D, sub_64), 0)); + dag AC = (v2f64 (XXPERMDI (SUBREG_TO_REG f64:$A, sub_64), + (SUBREG_TO_REG f64:$C, sub_64), 0)); + dag BD = (v2f64 (XXPERMDI (SUBREG_TO_REG f64:$B, sub_64), + (SUBREG_TO_REG f64:$D, sub_64), 0)); dag CVACS = (v4i32 (XVCVDPSXWS AC)); dag CVBDS = (v4i32 (XVCVDPSXWS BD)); dag CVACU = (v4i32 (XVCVDPUXWS AC)); @@ -2449,10 +2449,10 @@ def MrgWords { // For little endian, we merge hi doublewords of (D, B) and (C, A), convert // then merge. - dag DB = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$D, sub_64), - (SUBREG_TO_REG (i64 1), f64:$B, sub_64), 0)); - dag CA = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$C, sub_64), - (SUBREG_TO_REG (i64 1), f64:$A, sub_64), 0)); + dag DB = (v2f64 (XXPERMDI (SUBREG_TO_REG f64:$D, sub_64), + (SUBREG_TO_REG f64:$B, sub_64), 0)); + dag CA = (v2f64 (XXPERMDI (SUBREG_TO_REG f64:$C, sub_64), + (SUBREG_TO_REG f64:$A, sub_64), 0)); dag CVDBS = (v4i32 (XVCVDPSXWS DB)); dag CVCAS = (v4i32 (XVCVDPSXWS CA)); dag CVDBU = (v4i32 (XVCVDPUXWS DB)); @@ -2863,31 +2863,31 @@ def : Pat<(v2i64 immAllZerosV), // Build vectors of floating point converted to i32. def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.A, DblToInt.A, DblToInt.A)), - (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS $A), sub_64), 1))>; + (v4i32 (XXSPLTW (SUBREG_TO_REG (XSCVDPSXWS $A), sub_64), 1))>; def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.A, DblToUInt.A, DblToUInt.A)), - (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS $A), sub_64), 1))>; + (v4i32 (XXSPLTW (SUBREG_TO_REG (XSCVDPUXWS $A), sub_64), 1))>; def : Pat<(v2i64 (build_vector DblToLong.A, DblToLong.A)), - (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPSXDS $A), sub_64), - (SUBREG_TO_REG (i64 1), (XSCVDPSXDS $A), sub_64), 0))>; + (v2i64 (XXPERMDI (SUBREG_TO_REG (XSCVDPSXDS $A), sub_64), + (SUBREG_TO_REG (XSCVDPSXDS $A), sub_64), 0))>; def : Pat<(v2i64 (build_vector DblToULong.A, DblToULong.A)), - (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), - (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), 0))>; + (v2i64 (XXPERMDI (SUBREG_TO_REG (XSCVDPUXDS $A), sub_64), + (SUBREG_TO_REG (XSCVDPUXDS $A), sub_64), 0))>; def : Pat<(v4i32 (PPCSToV DblToInt.A)), - (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS f64:$A), sub_64))>; + (v4i32 (SUBREG_TO_REG (XSCVDPSXWS f64:$A), sub_64))>; def : Pat<(v4i32 (PPCSToV DblToUInt.A)), - (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS f64:$A), sub_64))>; + (v4i32 (SUBREG_TO_REG (XSCVDPUXWS f64:$A), sub_64))>; defm : ScalToVecWPermute< v4i32, FltToIntLoad.A, - (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), - (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>; + (XXSPLTW (SUBREG_TO_REG (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), + (SUBREG_TO_REG (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>; defm : ScalToVecWPermute< v4i32, FltToUIntLoad.A, - (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), - (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>; + (XXSPLTW (SUBREG_TO_REG (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), + (SUBREG_TO_REG (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>; def : Pat<(v4f32 (build_vector (f32 (fpround f64:$A)), (f32 (fpround f64:$A)), (f32 (fpround f64:$A)), (f32 (fpround f64:$A)))), - (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$A), sub_64), 0))>; + (v4f32 (XXSPLTW (SUBREG_TO_REG (XSCVDPSP f64:$A), sub_64), 0))>; def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)), (v4f32 (XXSPLTW (v4f32 (XSCVDPSPN $A)), 0))>; @@ -2896,11 +2896,11 @@ def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)), def : Pat<(v2f64 (PPCldsplat ForceXForm:$A)), (v2f64 (LXVDSX ForceXForm:$A))>; def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)), - (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>; + (v4f32 (XXSPLTW (SUBREG_TO_REG (LFIWZX ForceXForm:$A), sub_64), 1))>; def : Pat<(v2i64 (PPCldsplat ForceXForm:$A)), (v2i64 (LXVDSX ForceXForm:$A))>; def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)), - (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>; + (v4i32 (XXSPLTW (SUBREG_TO_REG (LFIWZX ForceXForm:$A), sub_64), 1))>; def : Pat<(v2i64 (PPCzextldsplat ForceXForm:$A)), (v2i64 (XXPERMDIs (LFIWZX ForceXForm:$A), 0))>; def : Pat<(v2i64 (PPCsextldsplat ForceXForm:$A)), @@ -2967,7 +2967,7 @@ def : Pat<(PPCstore_scal_int_from_vsr f128:$src, XForm:$dst, 8), // Any big endian VSX subtarget. let Predicates = [HasVSX, IsBigEndian] in { def : Pat<(v2f64 (scalar_to_vector f64:$A)), - (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>; + (v2f64 (SUBREG_TO_REG $A, sub_64))>; def : Pat<(f64 (extractelt v2f64:$S, 0)), (f64 (EXTRACT_SUBREG $S, sub_64))>; @@ -2987,8 +2987,8 @@ def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)), def : Pat<(v2f64 (build_vector f64:$A, f64:$B)), (v2f64 (XXPERMDI - (SUBREG_TO_REG (i64 1), $A, sub_64), - (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>; + (SUBREG_TO_REG $A, sub_64), + (SUBREG_TO_REG $B, sub_64), 0))>; // Using VMRGEW to assemble the final vector would be a lower latency // solution. However, we choose to go with the slightly higher latency // XXPERMDI for 2 reasons: @@ -3072,17 +3072,17 @@ def : Pat; def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)), - (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>; + (v2f64 (XXPERMDI (SUBREG_TO_REG $B, sub_64), $A, 1))>; def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)), - (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>; + (v2f64 (XXPERMDI $A, (SUBREG_TO_REG $B, sub_64), 0))>; } // HasVSX, IsBigEndian // Any little endian VSX subtarget. let Predicates = [HasVSX, IsLittleEndian] in { defm : ScalToVecWPermute; + (XXPERMDI (SUBREG_TO_REG $A, sub_64), + (SUBREG_TO_REG $A, sub_64), 0), + (SUBREG_TO_REG $A, sub_64)>; def : Pat<(f64 (extractelt v2f64:$S, 0)), (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>; @@ -3112,8 +3112,8 @@ def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)), // Little endian, available on all targets with VSX def : Pat<(v2f64 (build_vector f64:$A, f64:$B)), (v2f64 (XXPERMDI - (SUBREG_TO_REG (i64 1), $B, sub_64), - (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>; + (SUBREG_TO_REG $B, sub_64), + (SUBREG_TO_REG $A, sub_64), 0))>; // Using VMRGEW to assemble the final vector would be a lower latency // solution. However, we choose to go with the slightly higher latency // XXPERMDI for 2 reasons: @@ -3197,9 +3197,9 @@ def : Pat; def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)), - (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>; + (v2f64 (XXPERMDI $A, (SUBREG_TO_REG $B, sub_64), 0))>; def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)), - (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>; + (v2f64 (XXPERMDI (SUBREG_TO_REG $B, sub_64), $A, 1))>; } // HasVSX, IsLittleEndian // Any pre-Power9 VSX subtarget. @@ -3212,21 +3212,21 @@ def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 8), // Load-and-splat with fp-to-int conversion (using X-Form VSX/FP loads). defm : ScalToVecWPermute< v4i32, DblToIntLoad.A, - (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1), - (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64)>; + (XXSPLTW (SUBREG_TO_REG (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1), + (SUBREG_TO_REG (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64)>; defm : ScalToVecWPermute< v4i32, DblToUIntLoad.A, - (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1), - (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64)>; + (XXSPLTW (SUBREG_TO_REG (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1), + (SUBREG_TO_REG (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64)>; defm : ScalToVecWPermute< v2i64, FltToLongLoad.A, (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0), - (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), + (SUBREG_TO_REG (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), sub_64)>; defm : ScalToVecWPermute< v2i64, FltToULongLoad.A, (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0), - (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), + (SUBREG_TO_REG (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), sub_64)>; } // HasVSX, NoP9Vector @@ -3236,11 +3236,11 @@ let Predicates = [HasVSX, NoP9Vector, IsLittleEndian] in { defm : ScalToVecWPermute< v2i64, (i64 (load ForceXForm:$src)), (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2), - (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (XFLOADf64 ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v2f64, (f64 (load ForceXForm:$src)), (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2), - (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (XFLOADf64 ForceXForm:$src), sub_64)>; // Splat loads. def : Pat<(v8i16 (PPCldsplatAlign16 ForceXForm:$A)), @@ -3284,7 +3284,7 @@ let Predicates = [HasVSX, HasOnlySwappingMemOps, IsBigEndian] in { def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>; def : Pat<(v2i64 (scalar_to_vector (i64 (load ForceXForm:$src)))), - (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (XFLOADf64 ForceXForm:$src), sub_64)>; } // HasVSX, HasOnlySwappingMemOps, IsBigEndian // Target before Power8 with VSX. @@ -3450,11 +3450,11 @@ def : Pat<(f64 (vector_extract v2f64:$S, i32:$Idx)), defm : ScalToVecWPermute< v4i32, (i32 (load ForceXForm:$src)), (XXSLDWIs (LIWZX ForceXForm:$src), 1), - (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LIWZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v4f32, (f32 (load ForceXForm:$src)), (XXSLDWIs (LIWZX ForceXForm:$src), 1), - (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LIWZX ForceXForm:$src), sub_64)>; } // HasVSX, HasP8Vector, IsBigEndian // Big endian Power8 64Bit VSX subtarget. @@ -3466,9 +3466,9 @@ def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)), // LIWZX - This instruction will be emitted for i32, f32, and when // zero-extending i32 to i64 (zext i32 -> i64). def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 ForceXForm:$src)))), - (v2i64 (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64))>; + (v2i64 (SUBREG_TO_REG (LIWAX ForceXForm:$src), sub_64))>; def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 ForceXForm:$src)))), - (v2i64 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64))>; + (v2i64 (SUBREG_TO_REG (LIWZX ForceXForm:$src), sub_64))>; def : Pat; + (SUBREG_TO_REG (LIWAX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v2i64, (i64 (zextloadi32 ForceXForm:$src)), (XXPERMDIs (LIWZX ForceXForm:$src), 2), - (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LIWZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v4i32, (i32 (load ForceXForm:$src)), (XXPERMDIs (LIWZX ForceXForm:$src), 2), - (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LIWZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v4f32, (f32 (load ForceXForm:$src)), (XXPERMDIs (LIWZX ForceXForm:$src), 2), - (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LIWZX ForceXForm:$src), sub_64)>; def : Pat; + (v8i16 (SUBREG_TO_REG (MTVSRWZ $A), sub_64))>; def : Pat<(v16i8 (PPCmtvsrz i32:$A)), - (v16i8 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>; + (v16i8 (SUBREG_TO_REG (MTVSRWZ $A), sub_64))>; // Endianness-neutral constant splat on P8 and newer targets. The reason // for this pattern is that on targets with direct moves, we don't expand @@ -3685,18 +3685,18 @@ let Predicates = [HasVSX, HasDirectMove, IsBigEndian] in { // v16i8 scalar <-> vector conversions (BE) defm : ScalToVecWPermute< v16i8, (i32 i32:$A), - (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64), - (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; + (SUBREG_TO_REG MovesToVSR.BE_BYTE_0, sub_64), + (SUBREG_TO_REG (MTVSRWZ $A), sub_64)>; defm : ScalToVecWPermute< v8i16, (i32 i32:$A), - (SUBREG_TO_REG (i64 1), MovesToVSR.BE_HALF_0, sub_64), - (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; + (SUBREG_TO_REG MovesToVSR.BE_HALF_0, sub_64), + (SUBREG_TO_REG (MTVSRWZ $A), sub_64)>; defm : ScalToVecWPermute< v4i32, (i32 i32:$A), - (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64), - (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; + (SUBREG_TO_REG MovesToVSR.BE_WORD_0, sub_64), + (SUBREG_TO_REG (MTVSRWZ $A), sub_64)>; def : Pat<(v2i64 (scalar_to_vector i64:$A)), - (v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>; + (v2i64 (SUBREG_TO_REG MovesToVSR.BE_DWORD_0, sub_64))>; // v2i64 scalar <-> vector conversions (BE) def : Pat<(i64 (vector_extract v2i64:$S, 0)), @@ -3717,7 +3717,7 @@ let Predicates = [HasVSX, HasDirectMove, IsLittleEndian] in { (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC), (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>; defm : ScalToVecWPermute; + (SUBREG_TO_REG (MTVSRWZ $A), sub_64)>; defm : ScalToVecWPermute; @@ -3875,16 +3875,16 @@ let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64] in { // Big endian integer vectors using direct moves. def : Pat<(v2i64 (build_vector i64:$A, i64:$B)), (v2i64 (XXPERMDI - (SUBREG_TO_REG (i64 1), (MTVSRD $A), sub_64), - (SUBREG_TO_REG (i64 1), (MTVSRD $B), sub_64), 0))>; + (SUBREG_TO_REG (MTVSRD $A), sub_64), + (SUBREG_TO_REG (MTVSRD $B), sub_64), 0))>; def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), (XXPERMDI - (SUBREG_TO_REG (i64 1), + (SUBREG_TO_REG (MTVSRD (RLDIMI AnyExts.B, AnyExts.A, 32, 0)), sub_64), - (SUBREG_TO_REG (i64 1), + (SUBREG_TO_REG (MTVSRD (RLDIMI AnyExts.D, AnyExts.C, 32, 0)), sub_64), 0)>; def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), - (XXSPLTW (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64), 1)>; + (XXSPLTW (SUBREG_TO_REG (MTVSRWZ $A), sub_64), 1)>; } // HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64 // Little endian pre-Power9 VSX subtarget that has direct moves. @@ -3892,16 +3892,16 @@ let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian] in { // Little endian integer vectors using direct moves. def : Pat<(v2i64 (build_vector i64:$A, i64:$B)), (v2i64 (XXPERMDI - (SUBREG_TO_REG (i64 1), (MTVSRD $B), sub_64), - (SUBREG_TO_REG (i64 1), (MTVSRD $A), sub_64), 0))>; + (SUBREG_TO_REG (MTVSRD $B), sub_64), + (SUBREG_TO_REG (MTVSRD $A), sub_64), 0))>; def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), (XXPERMDI - (SUBREG_TO_REG (i64 1), + (SUBREG_TO_REG (MTVSRD (RLDIMI AnyExts.C, AnyExts.D, 32, 0)), sub_64), - (SUBREG_TO_REG (i64 1), + (SUBREG_TO_REG (MTVSRD (RLDIMI AnyExts.A, AnyExts.B, 32, 0)), sub_64), 0)>; def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), - (XXSPLTW (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64), 1)>; + (XXSPLTW (SUBREG_TO_REG (MTVSRWZ $A), sub_64), 1)>; } // Any Power9 VSX subtarget. @@ -4006,39 +4006,39 @@ def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, XForm:$dst), // Build vectors from i8 loads defm : ScalToVecWPermute; + (SUBREG_TO_REG (LXSIBZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute; + (SUBREG_TO_REG (LXSIBZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute; + (SUBREG_TO_REG (LXSIBZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v4i32, ScalarLoads.SELi8, (XXSPLTWs (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), 1), - (SUBREG_TO_REG (i64 1), (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), sub_64)>; + (SUBREG_TO_REG (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), sub_64)>; defm : ScalToVecWPermute< v2i64, ScalarLoads.SELi8i64, (XXPERMDIs (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), 0), - (SUBREG_TO_REG (i64 1), (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), sub_64)>; + (SUBREG_TO_REG (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), sub_64)>; // Build vectors from i16 loads defm : ScalToVecWPermute< v4i32, ScalarLoads.ZELi16, (XXSPLTWs (LXSIHZX ForceXForm:$src), 1), - (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LXSIHZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v2i64, ScalarLoads.ZELi16i64, (XXPERMDIs (LXSIHZX ForceXForm:$src), 0), - (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LXSIHZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v4i32, ScalarLoads.SELi16, (XXSPLTWs (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), 1), - (SUBREG_TO_REG (i64 1), (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), sub_64)>; + (SUBREG_TO_REG (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), sub_64)>; defm : ScalToVecWPermute< v2i64, ScalarLoads.SELi16i64, (XXPERMDIs (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), 0), - (SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>; + (SUBREG_TO_REG (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>; // Load/convert and convert/store patterns for f16. def : Pat<(f128 (extloadf16 ForceXForm:$src)), @@ -4073,9 +4073,9 @@ def : Pat<(f32 (fpround (f64 (extloadf32 DSForm:$src)))), (f32 (DFLOADf32 DSForm:$src))>; def : Pat<(v4f32 (PPCldvsxlh XForm:$src)), - (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>; + (SUBREG_TO_REG (XFLOADf64 XForm:$src), sub_64)>; def : Pat<(v4f32 (PPCldvsxlh DSForm:$src)), - (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>; + (SUBREG_TO_REG (DFLOADf64 DSForm:$src), sub_64)>; // Convert (Un)Signed DWord in memory -> QP def : Pat<(f128 (sint_to_fp (i64 (load XForm:$src)))), @@ -4137,7 +4137,7 @@ def : Pat<(f32 (PPCxsminc f32:$XA, f32:$XB)), // Endianness-neutral patterns for const splats with ISA 3.0 instructions. defm : ScalToVecWPermute; + (SUBREG_TO_REG (MTVSRWZ $A), sub_64)>; def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), (v4i32 (MTVSRWS $A))>; def : Pat<(v16i8 (build_vector immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, @@ -4152,30 +4152,28 @@ def : Pat<(v16i8 (build_vector immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, defm : ScalToVecWPermute< v4i32, FltToIntLoad.A, (XVCVSPSXWS (LXVWSX ForceXForm:$A)), - (XVCVSPSXWS (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64))>; + (XVCVSPSXWS (SUBREG_TO_REG (LIWZX ForceXForm:$A), sub_64))>; defm : ScalToVecWPermute< v4i32, FltToUIntLoad.A, (XVCVSPUXWS (LXVWSX ForceXForm:$A)), - (XVCVSPUXWS (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64))>; + (XVCVSPUXWS (SUBREG_TO_REG (LIWZX ForceXForm:$A), sub_64))>; defm : ScalToVecWPermute< v4i32, DblToIntLoadP9.A, - (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64), 1), - (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64)>; + (XXSPLTW (SUBREG_TO_REG (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64), 1), + (SUBREG_TO_REG (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64)>; defm : ScalToVecWPermute< v4i32, DblToUIntLoadP9.A, - (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64), 1), - (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64)>; + (XXSPLTW (SUBREG_TO_REG (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64), 1), + (SUBREG_TO_REG (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64)>; defm : ScalToVecWPermute< v2i64, FltToLongLoadP9.A, (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0), (SUBREG_TO_REG - (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>; defm : ScalToVecWPermute< v2i64, FltToULongLoadP9.A, (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0), (SUBREG_TO_REG - (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>; def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)), (v4f32 (LXVWSX ForceXForm:$A))>; @@ -4201,12 +4199,12 @@ let Predicates = [HasVSX, HasP9Vector, NoP10Vector] in { defm : ScalToVecWPermute< v16i8, ScalarLoads.Li8, (VSPLTBs 7, (LXSIBZX ForceXForm:$src)), - (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LXSIBZX ForceXForm:$src), sub_64)>; // Build vectors from i16 loads defm : ScalToVecWPermute< v8i16, ScalarLoads.Li16, (VSPLTHs 3, (LXSIHZX ForceXForm:$src)), - (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LXSIHZX ForceXForm:$src), sub_64)>; } // HasVSX, HasP9Vector, NoP10Vector // Any big endian Power9 VSX subtarget @@ -4217,12 +4215,12 @@ let Predicates = [HasVSX, HasP9Vector, IsBigEndian] in { defm : ScalToVecWPermute< v16i8, ScalarLoads.Li8, (VSPLTBs 7, (LXSIBZX ForceXForm:$src)), - (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LXSIBZX ForceXForm:$src), sub_64)>; // Build vectors from i16 loads defm : ScalToVecWPermute< v8i16, ScalarLoads.Li16, (VSPLTHs 3, (LXSIHZX ForceXForm:$src)), - (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LXSIHZX ForceXForm:$src), sub_64)>; def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>; @@ -4244,49 +4242,41 @@ def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 0))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 0))>; def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 4))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 4))>; def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 8))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 8))>; def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 12))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 12))>; def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)), (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>; @@ -4299,16 +4289,16 @@ def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)), def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 0))>; def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 4))>; def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 8))>; def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 12))>; // Scalar stores of i8 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), ForceXForm:$dst), @@ -4366,14 +4356,14 @@ def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst), // Big endian 64Bit Power9 subtarget. let Predicates = [HasVSX, HasP9Vector, IsBigEndian, IsPPC64] in { def : Pat<(v2i64 (scalar_to_vector (i64 (load DSForm:$src)))), - (v2i64 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64))>; + (v2i64 (SUBREG_TO_REG (DFLOADf64 DSForm:$src), sub_64))>; def : Pat<(v2i64 (scalar_to_vector (i64 (load XForm:$src)))), - (v2i64 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64))>; + (v2i64 (SUBREG_TO_REG (XFLOADf64 XForm:$src), sub_64))>; def : Pat<(v2f64 (scalar_to_vector (f64 (load DSForm:$src)))), - (v2f64 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64))>; + (v2f64 (SUBREG_TO_REG (DFLOADf64 DSForm:$src), sub_64))>; def : Pat<(v2f64 (scalar_to_vector (f64 (load XForm:$src)))), - (v2f64 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64))>; + (v2f64 (SUBREG_TO_REG (XFLOADf64 XForm:$src), sub_64))>; def : Pat<(store (i64 (extractelt v2i64:$A, 1)), XForm:$src), (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), XForm:$src)>; @@ -4503,7 +4493,7 @@ foreach Idx = 0-15 in { // Unsiged int in vsx register -> QP def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), (f128 (XSCVUDQP - (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 4)))>; + (XXEXTRACTUW (SUBREG_TO_REG $src, sub_64), 4)))>; } // HasVSX, HasP9Vector, IsBigEndian, IsPPC64 // Little endian Power9 subtarget. @@ -4528,49 +4518,41 @@ def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 12))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 12))>; def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 8))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 8))>; def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 4))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 4))>; def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 0))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 0))>; def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)), (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>; @@ -4583,16 +4565,16 @@ def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)), def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 12))>; def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 8))>; def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 4))>; def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 0))>; def : Pat<(v8i16 (PPCld_vec_be ForceXForm:$src)), (COPY_TO_REGCLASS (LXVH8X ForceXForm:$src), VRRC)>; @@ -4659,19 +4641,19 @@ def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst), defm : ScalToVecWPermute< v2i64, (i64 (load DSForm:$src)), (XXPERMDIs (DFLOADf64 DSForm:$src), 2), - (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>; + (SUBREG_TO_REG (DFLOADf64 DSForm:$src), sub_64)>; defm : ScalToVecWPermute< v2i64, (i64 (load XForm:$src)), (XXPERMDIs (XFLOADf64 XForm:$src), 2), - (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>; + (SUBREG_TO_REG (XFLOADf64 XForm:$src), sub_64)>; defm : ScalToVecWPermute< v2f64, (f64 (load DSForm:$src)), (XXPERMDIs (DFLOADf64 DSForm:$src), 2), - (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>; + (SUBREG_TO_REG (DFLOADf64 DSForm:$src), sub_64)>; defm : ScalToVecWPermute< v2f64, (f64 (load XForm:$src)), (XXPERMDIs (XFLOADf64 XForm:$src), 2), - (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>; + (SUBREG_TO_REG (XFLOADf64 XForm:$src), sub_64)>; def : Pat<(store (i64 (extractelt v2i64:$A, 0)), XForm:$src), (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), @@ -4826,7 +4808,7 @@ foreach Idx = [[0,15],[1,14],[2,13],[3,12],[4,11],[5,10],[6,9],[7,8],[8,7], // Unsiged int in vsx register -> QP def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), (f128 (XSCVUDQP - (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 8)))>; + (XXEXTRACTUW (SUBREG_TO_REG $src, sub_64), 8)))>; } // HasVSX, HasP9Vector, IsLittleEndian // Any Power9 VSX subtarget that supports Power9 Altivec. diff --git a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp index 2bf05e7518803..85a90992816e5 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp @@ -394,10 +394,10 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() { // (FIXME) a cost model could be used. However, introduced // swaps could potentially be CSEd, so this is not trivial. if (isVecReg(MI.getOperand(0).getReg()) && - isVecReg(MI.getOperand(2).getReg())) + isVecReg(MI.getOperand(1).getReg())) SwapVector[VecIdx].IsSwappable = 1; else if (isVecReg(MI.getOperand(0).getReg()) && - isScalarVecReg(MI.getOperand(2).getReg())) { + isScalarVecReg(MI.getOperand(1).getReg())) { SwapVector[VecIdx].IsSwappable = 1; SwapVector[VecIdx].SpecialHandling = SHValues::SH_COPYWIDEN; } @@ -559,13 +559,9 @@ unsigned PPCVSXSwapRemoval::lookThruCopyLike(unsigned SrcReg, if (!MI->isCopyLike()) return SrcReg; - unsigned CopySrcReg; - if (MI->isCopy()) - CopySrcReg = MI->getOperand(1).getReg(); - else { - assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike"); - CopySrcReg = MI->getOperand(2).getReg(); - } + assert((MI->isCopy() || MI->isSubregToReg()) && + "bad opcode for lookThruCopyLike"); + unsigned CopySrcReg = MI->getOperand(1).getReg(); if (!Register::isVirtualRegister(CopySrcReg)) { if (!isScalarVecReg(CopySrcReg)) diff --git a/llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp b/llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp index 2ec566ddb0b8e..741aa20eab479 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp @@ -93,8 +93,6 @@ struct PPCVSXWACCCopy : public MachineFunctionPass { Register NewVReg = MRI.createVirtualRegister(SrcRC); BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg) - .addImm(1) // add 1, not 0, because there is no implicit clearing - // of the high bits. .add(SrcMO) .addImm(PPC::sub_64); diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp index 74440422b2f2e..bbc7f464eda4a 100644 --- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp +++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp @@ -304,7 +304,6 @@ bool X86InstructionSelector::selectCopy(MachineInstr &I, BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::SUBREG_TO_REG)) .addDef(ExtSrc) - .addImm(0) .addReg(SrcReg) .addImm(getSubRegIndex(SrcRC)); @@ -322,7 +321,6 @@ bool X86InstructionSelector::selectCopy(MachineInstr &I, Register ExtReg = MRI.createVirtualRegister(&X86::GR32RegClass); BuildMI(*I.getParent(), I, DL, TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg) - .addImm(0) .addReg(SrcReg) .addImm(X86::sub_16bit); @@ -1043,7 +1041,6 @@ bool X86InstructionSelector::selectAnyext(MachineInstr &I, BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::SUBREG_TO_REG)) .addDef(DstReg) - .addImm(0) .addReg(SrcReg) .addImm(getSubRegIndex(SrcRC)); @@ -1875,7 +1872,6 @@ bool X86InstructionSelector::selectMulDivRem(MachineInstr &I, } else if (RegTy.getSizeInBits() == 64) { BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg) - .addImm(0) .addReg(Zero32) .addImm(X86::sub_32bit); } diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 934ab80ae8133..bd36f2ccf4aed 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -1098,7 +1098,6 @@ bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) { Register ExtReg = createResultReg(&X86::GR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg) - .addImm(0) .addReg(CopyReg) .addImm(X86::sub_32bit); Reg = ExtReg; @@ -1574,9 +1573,10 @@ bool X86FastISel::X86SelectZExt(const Instruction *I) { .addReg(ResultReg); ResultReg = createResultReg(&X86::GR64RegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::SUBREG_TO_REG), - ResultReg) - .addImm(0).addReg(Result32).addImm(X86::sub_32bit); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, + TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg) + .addReg(Result32) + .addImm(X86::sub_32bit); } else if (DstVT == MVT::i16) { // i8->i16 doesn't exist in the autogenerated isel table. Need to zero // extend to 32-bits and then extract down to 16-bits. @@ -1989,7 +1989,8 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) { } else if (VT == MVT::i64) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg) - .addImm(0).addReg(Zero32).addImm(X86::sub_32bit); + .addReg(Zero32) + .addImm(X86::sub_32bit); } } } @@ -3708,7 +3709,8 @@ Register X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) { Register ResultReg = createResultReg(&X86::GR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg) - .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit); + .addReg(SrcReg) + .addImm(X86::sub_32bit); return ResultReg; } } diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index eb425a10acf09..7607fad150db0 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -486,8 +486,7 @@ namespace { if (VT == MVT::i64) { Zero = SDValue( CurDAG->getMachineNode( - TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, - CurDAG->getTargetConstant(0, dl, MVT::i64), Zero, + TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, Zero, CurDAG->getTargetConstant(X86::sub_32bit, dl, MVT::i32)), 0); } @@ -1720,11 +1719,11 @@ void X86DAGToDAGISel::PostprocessISelDAG() { } // Attempt to remove vectors moves that were inserted to zero upper bits. case TargetOpcode::SUBREG_TO_REG: { - unsigned SubRegIdx = N->getConstantOperandVal(2); + unsigned SubRegIdx = N->getConstantOperandVal(1); if (SubRegIdx != X86::sub_xmm && SubRegIdx != X86::sub_ymm) continue; - SDValue Move = N->getOperand(1); + SDValue Move = N->getOperand(0); if (!Move.isMachineOpcode()) continue; @@ -1764,7 +1763,7 @@ void X86DAGToDAGISel::PostprocessISelDAG() { // Producing instruction is another vector instruction. We can drop the // move. - CurDAG->UpdateNodeOperands(N, N->getOperand(0), In, N->getOperand(2)); + CurDAG->UpdateNodeOperands(N, In, N->getOperand(1)); MadeChange = true; } } @@ -5974,13 +5973,11 @@ void X86DAGToDAGISel::Select(SDNode *Node) { case MVT::i32: break; case MVT::i64: - ClrNode = - SDValue(CurDAG->getMachineNode( - TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, - CurDAG->getTargetConstant(0, dl, MVT::i64), ClrNode, - CurDAG->getTargetConstant(X86::sub_32bit, dl, - MVT::i32)), - 0); + ClrNode = SDValue( + CurDAG->getMachineNode( + TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, ClrNode, + CurDAG->getTargetConstant(X86::sub_32bit, dl, MVT::i32)), + 0); break; default: llvm_unreachable("Unexpected division source"); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 755cd7b287e21..e86d478d1baa0 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -36586,7 +36586,6 @@ X86TargetLowering::EmitVAARGWithCustomInserter(MachineInstr &MI, // Zero-extend the offset Register OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); BuildMI(offsetMBB, MIMD, TII->get(X86::SUBREG_TO_REG), OffsetReg64) - .addImm(0) .addReg(OffsetReg) .addImm(X86::sub_32bit); @@ -37849,9 +37848,8 @@ X86TargetLowering::emitLongJmpShadowStackFix(MachineInstr &MI, if (PVT == MVT::i64) { Register TmpZReg = MRI.createVirtualRegister(PtrRC); BuildMI(checkSspMBB, MIMD, TII->get(X86::SUBREG_TO_REG), TmpZReg) - .addImm(0) - .addReg(ZReg) - .addImm(X86::sub_32bit); + .addReg(ZReg) + .addImm(X86::sub_32bit); ZReg = TmpZReg; } @@ -38225,7 +38223,6 @@ X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI, .addReg(0); // movzx IReg64, IReg BuildMI(DispContBB, MIMD, TII->get(TargetOpcode::SUBREG_TO_REG), IReg64) - .addImm(0) .addReg(IReg) .addImm(X86::sub_32bit); diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 0392100f8c6c3..df0d614a0251f 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2724,7 +2724,7 @@ def : Pat<(i8 (bitconvert (v8i1 VK8:$src))), def : Pat<(i32 (zext (i16 (bitconvert (v16i1 VK16:$src))))), (KMOVWrk VK16:$src)>; def : Pat<(i64 (zext (i16 (bitconvert (v16i1 VK16:$src))))), - (SUBREG_TO_REG (i64 0), (KMOVWrk VK16:$src), sub_32bit)>; + (SUBREG_TO_REG (KMOVWrk VK16:$src), sub_32bit)>; def : Pat<(i32 (anyext (i16 (bitconvert (v16i1 VK16:$src))))), (COPY_TO_REGCLASS VK16:$src, GR32)>; def : Pat<(i64 (anyext (i16 (bitconvert (v16i1 VK16:$src))))), @@ -2733,7 +2733,7 @@ def : Pat<(i64 (anyext (i16 (bitconvert (v16i1 VK16:$src))))), def : Pat<(i32 (zext (i8 (bitconvert (v8i1 VK8:$src))))), (KMOVBrk VK8:$src)>, Requires<[HasDQI]>; def : Pat<(i64 (zext (i8 (bitconvert (v8i1 VK8:$src))))), - (SUBREG_TO_REG (i64 0), (KMOVBrk VK8:$src), sub_32bit)>, Requires<[HasDQI]>; + (SUBREG_TO_REG (KMOVBrk VK8:$src), sub_32bit)>, Requires<[HasDQI]>; def : Pat<(i32 (anyext (i8 (bitconvert (v8i1 VK8:$src))))), (COPY_TO_REGCLASS VK8:$src, GR32)>; def : Pat<(i64 (anyext (i8 (bitconvert (v8i1 VK8:$src))))), @@ -4455,20 +4455,20 @@ let Predicates = [HasAVX512, OptForSize] in { // Move low f32 and clear high bits. def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4f32 (VMOVSSZrr (v4f32 (AVX512_128_SET0)), (v4f32 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4i32 (VMOVSSZrr (v4i32 (AVX512_128_SET0)), (v4i32 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v16f32 (X86vzmovl (v16f32 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4f32 (VMOVSSZrr (v4f32 (AVX512_128_SET0)), (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v16i32 (X86vzmovl (v16i32 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4i32 (VMOVSSZrr (v4i32 (AVX512_128_SET0)), (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm)))), sub_xmm)>; } @@ -4477,12 +4477,12 @@ let Predicates = [HasAVX512, OptForSize] in { // VMOVSS/SD. Unfortunately, loses the ability to use XMM16-31. let Predicates = [HasAVX512, OptForSpeed] in { def : Pat<(v16f32 (X86vzmovl (v16f32 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4f32 (VBLENDPSrri (v4f32 (V_SET0)), (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm)), (i8 1))), sub_xmm)>; def : Pat<(v16i32 (X86vzmovl (v16i32 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4i32 (VPBLENDWrri (v4i32 (V_SET0)), (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm)), (i8 3))), sub_xmm)>; @@ -4497,16 +4497,16 @@ let Predicates = [HasAVX512] in { // Represent the same patterns above but in the form they appear for // 256-bit types def : Pat<(v8f32 (X86vzload32 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSSZrm addr:$src), sub_xmm)>; def : Pat<(v4f64 (X86vzload64 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSDZrm addr:$src), sub_xmm)>; // Represent the same patterns above but in the form they appear for // 512-bit types def : Pat<(v16f32 (X86vzload32 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSSZrm addr:$src), sub_xmm)>; def : Pat<(v8f64 (X86vzload64 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSDZrm addr:$src), sub_xmm)>; } let Predicates = [HasFP16] in { def : Pat<(v8f16 (X86vzmovl (v8f16 VR128X:$src))), @@ -4516,21 +4516,21 @@ let Predicates = [HasFP16] in { // FIXME we need better canonicalization in dag combine def : Pat<(v16f16 (X86vzmovl (v16f16 VR256X:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v8f16 (VMOVSHZrr (v8f16 (AVX512_128_SET0)), (v8f16 (EXTRACT_SUBREG (v16f16 VR256X:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v16i16 (X86vzmovl (v16i16 VR256X:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v8i16 (VMOVSHZrr (v8i16 (AVX512_128_SET0)), (v8i16 (EXTRACT_SUBREG (v16i16 VR256X:$src), sub_xmm)))), sub_xmm)>; // FIXME we need better canonicalization in dag combine def : Pat<(v32f16 (X86vzmovl (v32f16 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v8f16 (VMOVSHZrr (v8f16 (AVX512_128_SET0)), (v8f16 (EXTRACT_SUBREG (v32f16 VR512:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v32i16 (X86vzmovl (v32i16 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v8i16 (VMOVSHZrr (v8i16 (AVX512_128_SET0)), (v8i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_xmm)))), sub_xmm)>; @@ -4538,10 +4538,10 @@ let Predicates = [HasFP16] in { (VMOVSHZrm addr:$src)>; def : Pat<(v16f16 (X86vzload16 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSHZrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSHZrm addr:$src), sub_xmm)>; def : Pat<(v32f16 (X86vzload16 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSHZrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSHZrm addr:$src), sub_xmm)>; } let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecLogic.XMM] in { @@ -4567,38 +4567,38 @@ let Predicates = [HasAVX512] in { def : Pat<(v4i32 (X86vzload32 addr:$src)), (VMOVDI2PDIZrm addr:$src)>; def : Pat<(v8i32 (X86vzload32 addr:$src)), - (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))), (VMOVZPQILo2PQIZrr VR128X:$src)>; def : Pat<(v2i64 (X86vzload64 addr:$src)), (VMOVQI2PQIZrm addr:$src)>; def : Pat<(v4i64 (X86vzload64 addr:$src)), - (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; // Use regular 128-bit instructions to match 512-bit scalar_to_vec+zext. def : Pat<(v16i32 (X86vzload32 addr:$src)), - (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; def : Pat<(v8i64 (X86vzload64 addr:$src)), - (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v2f64 (VMOVZPQILo2PQIZrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v2i64 (VMOVZPQILo2PQIZrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v8f64 (X86vzmovl (v8f64 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v2f64 (VMOVZPQILo2PQIZrr (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v8i64 (X86vzmovl (v8i64 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v2i64 (VMOVZPQILo2PQIZrr (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm)))), sub_xmm)>; @@ -13033,13 +13033,13 @@ def : Pat<(v8i32 (X86vzmovl (v4i32 (scalar_to_vector (and GR32:$src, 0xffff))), (iPTR 0)))), - (SUBREG_TO_REG (i32 0), (VMOVW2SHrr GR32:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVW2SHrr GR32:$src), sub_xmm)>; def : Pat<(v16i32 (X86vzmovl (insert_subvector undef, (v4i32 (scalar_to_vector (and GR32:$src, 0xffff))), (iPTR 0)))), - (SUBREG_TO_REG (i32 0), (VMOVW2SHrr GR32:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVW2SHrr GR32:$src), sub_xmm)>; def : Pat<(v8i16 (X86vzmovl (scalar_to_vector (i16 GR16:$src)))), (VMOVW2SHrr (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit))>; @@ -13048,11 +13048,11 @@ def : Pat<(v8i16 (X86vzmovl (scalar_to_vector (i16 GR16:$src)))), def : Pat<(v8i16 (X86vzload16 addr:$src)), (VMOVWrm addr:$src)>; def : Pat<(v16i16 (X86vzload16 addr:$src)), - (SUBREG_TO_REG (i32 0), (v8i16 (VMOVWrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v8i16 (VMOVWrm addr:$src)), sub_xmm)>; // Use regular 128-bit instructions to match 512-bit scalar_to_vec+zext. def : Pat<(v32i16 (X86vzload16 addr:$src)), - (SUBREG_TO_REG (i32 0), (v8i16 (VMOVWrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v8i16 (VMOVWrm addr:$src)), sub_xmm)>; def : Pat<(v4i32 (scalar_to_vector (i32 (extloadi16 addr:$src)))), (VMOVWrm addr:$src)>; @@ -13063,13 +13063,13 @@ def : Pat<(v8i32 (X86vzmovl (v4i32 (scalar_to_vector (i32 (zextloadi16 addr:$src)))), (iPTR 0)))), - (SUBREG_TO_REG (i32 0), (VMOVWrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVWrm addr:$src), sub_xmm)>; def : Pat<(v16i32 (X86vzmovl (insert_subvector undef, (v4i32 (scalar_to_vector (i32 (zextloadi16 addr:$src)))), (iPTR 0)))), - (SUBREG_TO_REG (i32 0), (VMOVWrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVWrm addr:$src), sub_xmm)>; // Move word from xmm register to r/m16 def VMOVSH2Wrr : AVX512<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src), diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index 83294d7d6d3bd..6c8a7d7c83f0a 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -330,7 +330,7 @@ def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", let AddedComplexity = 10 in { def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; -def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>; +def : Pat<(i64 0), (SUBREG_TO_REG (MOV32r0), sub_32bit)>; } let Predicates = [OptForSize, Not64BitMode], @@ -1456,7 +1456,7 @@ def : Pat<(zextloadi16i1 addr:$src), (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; def : Pat<(zextloadi64i1 addr:$src), - (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rm8 addr:$src), sub_32bit)>; // extload bool -> extload byte // When extloading from 16-bit and smaller memory locations into 64-bit @@ -1477,13 +1477,13 @@ def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; // NOTE: The extloadi64i32 pattern needs to be first as it will try to form // 32-bit loads for 4 byte aligned i8/i16 loads. def : Pat<(extloadi64i32 addr:$src), - (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOV32rm addr:$src), sub_32bit)>; def : Pat<(extloadi64i1 addr:$src), - (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rm8 addr:$src), sub_32bit)>; def : Pat<(extloadi64i8 addr:$src), - (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rm8 addr:$src), sub_32bit)>; def : Pat<(extloadi64i16 addr:$src), - (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rm16 addr:$src), sub_32bit)>; // anyext. Define these to do an explicit zero-extend to // avoid partial-register updates. @@ -1496,9 +1496,9 @@ def : Pat<(i32 (anyext GR16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; def : Pat<(i64 (anyext GR8 :$src)), - (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rr8 GR8 :$src), sub_32bit)>; def : Pat<(i64 (anyext GR16:$src)), - (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rr16 GR16 :$src), sub_32bit)>; def : Pat<(i64 (anyext GR32:$src)), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>; @@ -1507,9 +1507,9 @@ def : Pat<(i32 (anyext_sdiv GR8:$src)), (MOVSX32rr8 GR8:$src)>; // In the case of a 32-bit def that is known to implicitly zero-extend, // we can use a SUBREG_TO_REG. def : Pat<(i64 (zext def32:$src)), - (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; + (SUBREG_TO_REG GR32:$src, sub_32bit)>; def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)), - (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; + (SUBREG_TO_REG GR32:$src, sub_32bit)>; //===----------------------------------------------------------------------===// // Pattern match OR as ADD @@ -1676,7 +1676,6 @@ let AddedComplexity = 1 in { let Predicates = [NoNDD] in { def : Pat<(and GR64:$src, i64immZExt32:$imm), (SUBREG_TO_REG - (i64 0), (AND32ri (EXTRACT_SUBREG GR64:$src, sub_32bit), (i32 (GetLo32XForm imm:$imm))), @@ -1685,7 +1684,6 @@ let AddedComplexity = 1 in { let Predicates = [HasNDD] in { def : Pat<(and GR64:$src, i64immZExt32:$imm), (SUBREG_TO_REG - (i64 0), (AND32ri_ND (EXTRACT_SUBREG GR64:$src, sub_32bit), (i32 (GetLo32XForm imm:$imm))), @@ -1711,18 +1709,15 @@ def : Pat<(and GR16:$src1, 0xff), // r & (2^32-1) ==> movz def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), - (SUBREG_TO_REG (i64 0), - (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), + (SUBREG_TO_REG (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), sub_32bit)>; // r & (2^16-1) ==> movz def : Pat<(and GR64:$src, 0xffff), - (SUBREG_TO_REG (i64 0), - (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), - sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), + sub_32bit)>; // r & (2^8-1) ==> movz def : Pat<(and GR64:$src, 0xff), - (SUBREG_TO_REG (i64 0), - (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), + (SUBREG_TO_REG (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), sub_32bit)>; } // AddedComplexity = 1 @@ -1846,19 +1841,16 @@ def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)), // h-register extract and zero-extend. def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), (SUBREG_TO_REG - (i64 0), (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)), sub_32bit)>; def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), (SUBREG_TO_REG - (i64 0), (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), sub_32bit)>; def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), (SUBREG_TO_REG - (i64 0), (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), sub_32bit)>; @@ -2253,13 +2245,13 @@ defm : EFLAGSDefiningPats<"_ND", HasNDD>; let Predicates = [HasZU] in { // zext (mul reg/mem, imm) -> imulzu def : Pat<(i32 (zext (i16 (mul GR16:$src1, imm:$src2)))), - (SUBREG_TO_REG (i32 0), (IMULZU16rri GR16:$src1, imm:$src2), sub_16bit)>; + (SUBREG_TO_REG (IMULZU16rri GR16:$src1, imm:$src2), sub_16bit)>; def : Pat<(i32 (zext (i16 (mul (loadi16 addr:$src1), imm:$src2)))), - (SUBREG_TO_REG (i32 0), (IMULZU16rmi addr:$src1, imm:$src2), sub_16bit)>; + (SUBREG_TO_REG (IMULZU16rmi addr:$src1, imm:$src2), sub_16bit)>; def : Pat<(i64 (zext (i16 (mul GR16:$src1, imm:$src2)))), - (SUBREG_TO_REG (i64 0), (IMULZU16rri GR16:$src1, imm:$src2), sub_16bit)>; + (SUBREG_TO_REG (IMULZU16rri GR16:$src1, imm:$src2), sub_16bit)>; def : Pat<(i64 (zext (i16 (mul (loadi16 addr:$src1), imm:$src2)))), - (SUBREG_TO_REG (i64 0), (IMULZU16rmi addr:$src1, imm:$src2), sub_16bit)>; + (SUBREG_TO_REG (IMULZU16rmi addr:$src1, imm:$src2), sub_16bit)>; } // mul reg, imm diff --git a/llvm/lib/Target/X86/X86InstrExtension.td b/llvm/lib/Target/X86/X86InstrExtension.td index 46554dfc5167a..7bf0cb1d64755 100644 --- a/llvm/lib/Target/X86/X86InstrExtension.td +++ b/llvm/lib/Target/X86/X86InstrExtension.td @@ -202,14 +202,14 @@ def MOVZX64rm16 : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), // 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a // 32-bit register. def : Pat<(i64 (zext GR8:$src)), - (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rr8 GR8:$src), sub_32bit)>; def : Pat<(zextloadi64i8 addr:$src), - (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rm8 addr:$src), sub_32bit)>; def : Pat<(i64 (zext GR16:$src)), - (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rr16 GR16:$src), sub_32bit)>; def : Pat<(zextloadi64i16 addr:$src), - (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rm16 addr:$src), sub_32bit)>; // The preferred way to do 32-bit-to-64-bit zero extension on x86-64 is to use a // SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible @@ -217,6 +217,6 @@ def : Pat<(zextloadi64i16 addr:$src), // where the high bits aren't necessarily all zero. In such cases, we fall back // to these explicit zext instructions. def : Pat<(i64 (zext GR32:$src)), - (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>; + (SUBREG_TO_REG (MOV32rr GR32:$src), sub_32bit)>; def : Pat<(i64 (zextloadi64i32 addr:$src)), - (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOV32rm addr:$src), sub_32bit)>; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index c99865cc2dfcd..4532327067d8d 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -1070,17 +1070,12 @@ findRedundantFlagInstr(MachineInstr &CmpInstr, MachineInstr &CmpValDefInstr, } if (CmpInstr.getOpcode() == X86::TEST64rr) { - // As seen in X86 td files, CmpValDefInstr.getOperand(1).getImm() is - // typically 0. - if (CmpValDefInstr.getOperand(1).getImm() != 0) - return false; - // As seen in X86 td files, CmpValDefInstr.getOperand(3) is typically // sub_32bit or sub_xmm. - if (CmpValDefInstr.getOperand(3).getImm() != X86::sub_32bit) + if (CmpValDefInstr.getOperand(2).getImm() != X86::sub_32bit) return false; - VregDefInstr = MRI->getVRegDef(CmpValDefInstr.getOperand(2).getReg()); + VregDefInstr = MRI->getVRegDef(CmpValDefInstr.getOperand(1).getReg()); } assert(VregDefInstr && "Must have a definition (SSA)"); @@ -1098,7 +1093,7 @@ findRedundantFlagInstr(MachineInstr &CmpInstr, MachineInstr &CmpValDefInstr, // Get a sequence of instructions like // %reg = and* ... // Set EFLAGS // ... // EFLAGS not changed - // %extended_reg = subreg_to_reg 0, %reg, %subreg.sub_32bit + // %extended_reg = subreg_to_reg %reg, %subreg.sub_32bit // test64rr %extended_reg, %extended_reg, implicit-def $eflags // or // %reg = and32* ... @@ -4618,13 +4613,10 @@ bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI, if (MI.isSubregToReg()) { // We use following pattern to setup 64b immediate. // %8:gr32 = MOV32r0 implicit-def dead $eflags - // %6:gr64 = SUBREG_TO_REG 0, killed %8:gr32, %subreg.sub_32bit - if (!MI.getOperand(1).isImm()) - return false; - unsigned FillBits = MI.getOperand(1).getImm(); - unsigned SubIdx = MI.getOperand(3).getImm(); - MovReg = MI.getOperand(2).getReg(); - if (SubIdx != X86::sub_32bit || FillBits != 0) + // %6:gr64 = SUBREG_TO_REG killed %8:gr32, %subreg.sub_32bit + unsigned SubIdx = MI.getOperand(2).getImm(); + MovReg = MI.getOperand(1).getReg(); + if (SubIdx != X86::sub_32bit) return false; const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); MovMI = MRI.getUniqueVRegDef(MovReg); @@ -5391,7 +5383,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, // Example for test64rr: // %reg = and32ri %in_reg, 5 // ... // EFLAGS not changed. - // %src_reg = subreg_to_reg 0, %reg, %subreg.sub_index + // %src_reg = subreg_to_reg %reg, %subreg.sub_index // test64rr %src_reg, %src_reg, implicit-def $eflags MachineInstr *AndInstr = nullptr; if (IsCmpZero && diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index 290d91bb2ce69..d94108754d555 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1340,23 +1340,19 @@ def AndMask64 : ImmLeaf; + (SUBREG_TO_REG (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), (BEXTR64rm addr:$src, - (SUBREG_TO_REG (i64 0), - (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; + (SUBREG_TO_REG (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; } let Predicates = [HasBMI, NoBMI2, NoTBM, HasEGPR] in { def : Pat<(and GR64:$src, AndMask64:$mask), (BEXTR64rr_EVEX GR64:$src, - (SUBREG_TO_REG (i64 0), - (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; + (SUBREG_TO_REG (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), (BEXTR64rm_EVEX addr:$src, - (SUBREG_TO_REG (i64 0), - (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; + (SUBREG_TO_REG (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; } // Use BZHI for 64-bit 'and' with large immediate 'mask'. diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index e915e47046d9c..f67bc0e74acc8 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -301,9 +301,9 @@ let Predicates = [UseAVX] in { // Represent the same patterns above but in the form they appear for // 256-bit types def : Pat<(v8f32 (X86vzload32 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSSrm addr:$src), sub_xmm)>; def : Pat<(v4f64 (X86vzload64 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSDrm addr:$src), sub_xmm)>; } let Predicates = [UseAVX, OptForSize] in { @@ -316,11 +316,11 @@ let Predicates = [UseAVX, OptForSize] in { // Move low f32 and clear high bits. def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4f32 (VMOVSSrr (v4f32 (V_SET0)), (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4i32 (VMOVSSrr (v4i32 (V_SET0)), (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)))), sub_xmm)>; } @@ -4293,7 +4293,7 @@ let Predicates = [UseAVX] in { def : Pat<(v4i32 (X86vzload32 addr:$src)), (VMOVDI2PDIrm addr:$src)>; def : Pat<(v8i32 (X86vzload32 addr:$src)), - (SUBREG_TO_REG (i64 0), (v4i32 (VMOVDI2PDIrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v4i32 (VMOVDI2PDIrm addr:$src)), sub_xmm)>; } let Predicates = [UseSSE2] in { @@ -4373,7 +4373,7 @@ let Predicates = [UseAVX] in { def : Pat<(v2i64 (X86vzload64 addr:$src)), (VMOVQI2PQIrm addr:$src)>; def : Pat<(v4i64 (X86vzload64 addr:$src)), - (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v2i64 (VMOVQI2PQIrm addr:$src)), sub_xmm)>; def : Pat<(X86vextractstore64 (v2i64 VR128:$src), addr:$dst), (VMOVPQI2QImr addr:$dst, VR128:$src)>; @@ -4412,12 +4412,12 @@ let Predicates = [UseSSE2] in { let Predicates = [UseAVX] in { def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v2f64 (VMOVZPQILo2PQIrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v2i64 (VMOVZPQILo2PQIrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)))), sub_xmm)>; @@ -6442,12 +6442,12 @@ let Predicates = [HasAVX, OptForSpeed] in { // Move low f32 and clear high bits. def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4f32 (VBLENDPSrri (v4f32 (V_SET0)), (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), (i8 1))), sub_xmm)>; def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4i32 (VPBLENDWrri (v4i32 (V_SET0)), (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), (i8 3))), sub_xmm)>; diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td index eb0b5a43afdf9..fdf576baba02d 100644 --- a/llvm/lib/Target/X86/X86InstrSystem.td +++ b/llvm/lib/Target/X86/X86InstrSystem.td @@ -749,14 +749,14 @@ let Predicates = [HasINVPCID, NoEGPR] in { // type),/ so it doesn't hurt us that one can't supply a 64 bit value here. def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2), (INVPCID64 - (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit), + (SUBREG_TO_REG (MOV32rr GR32:$src1), sub_32bit), addr:$src2)>; } let Predicates = [HasINVPCID, HasEGPR] in { def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2), (INVPCID64_EVEX - (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit), + (SUBREG_TO_REG (MOV32rr GR32:$src1), sub_32bit), addr:$src2)>; } diff --git a/llvm/lib/Target/X86/X86InstrVecCompiler.td b/llvm/lib/Target/X86/X86InstrVecCompiler.td index 122627ca45d31..9cd479b518543 100644 --- a/llvm/lib/Target/X86/X86InstrVecCompiler.td +++ b/llvm/lib/Target/X86/X86InstrVecCompiler.td @@ -120,7 +120,7 @@ multiclass subvec_zero_lowering { def : Pat<(DstTy (insert_subvector immAllZerosV, (SrcTy RC:$src), (iPTR 0))), - (SUBREG_TO_REG (i64 0), + (SUBREG_TO_REG (SrcTy (!cast("VMOV"#MoveStr#"rr") RC:$src)), SubIdx)>; } diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp index e0b17ce1be79d..817cc86a63cdf 100644 --- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -501,7 +501,6 @@ bool X86SpeculativeLoadHardeningImpl::run(MachineFunction &MF) { ZeroEFLAGSDefOp->setIsDead(true); BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::SUBREG_TO_REG), PS->InitialReg) - .addImm(0) .addReg(PredStateSubReg) .addImm(X86::sub_32bit); } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/166563.mir b/llvm/test/CodeGen/AArch64/GlobalISel/166563.mir index 12e362e7b7fd2..b2bb44e551f81 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/166563.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/166563.mir @@ -16,7 +16,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 457873110 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK-NEXT: TBNZW [[MOVi32imm1]], 0, %bb.2 ; CHECK-NEXT: B %bb.1 @@ -132,7 +132,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 457873110 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK-NEXT: TBNZW [[MOVi32imm1]], 0, %bb.2 ; CHECK-NEXT: B %bb.1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir index 99bb62b117080..2771cead06da4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir @@ -49,10 +49,10 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY2]], 0, 15 - ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG1]] ; CHECK-NEXT: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY3]], 16, 15 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64sp = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir index dc2e1c5dc28d4..2aee1bbc8ddd4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir @@ -139,7 +139,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 4103 ; CHECK-NEXT: [[LDRHHroX:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16)) ; CHECK-NEXT: RET_ReallyLR implicit [[LDRHHroX]] @@ -393,7 +393,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[SUBREG_TO_REG]], [[COPY]], $xzr ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1 ; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load (s64) from %ir.addr) @@ -427,7 +427,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 16 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[SUBREG_TO_REG]], [[COPY]], $xzr ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1 ; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load (s64) from %ir.addr) @@ -496,7 +496,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 4103 ; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s64)) ; CHECK-NEXT: [[LDRXroX1:%[0-9]+]]:gpr64 = LDRXroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s64)) @@ -578,7 +578,7 @@ body: | ; CHECK-FAST-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-FAST-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31 ; CHECK-FAST-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0 - ; CHECK-FAST-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-FAST-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-FAST-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 4103 ; CHECK-FAST-NEXT: [[LDRHHroX:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16)) ; CHECK-FAST-NEXT: [[LDRHHroX1:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16)) @@ -592,7 +592,7 @@ body: | ; CHECK-SLOW-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-SLOW-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31 ; CHECK-SLOW-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0 - ; CHECK-SLOW-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-SLOW-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-SLOW-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]] ; CHECK-SLOW-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY [[COPY]] @@ -636,7 +636,7 @@ body: | ; CHECK-FAST-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-FAST-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31 ; CHECK-FAST-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0 - ; CHECK-FAST-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-FAST-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-FAST-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 4103 ; CHECK-FAST-NEXT: [[LDRHHroX:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16)) ; CHECK-FAST-NEXT: [[LDRHHroX1:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16)) @@ -650,7 +650,7 @@ body: | ; CHECK-SLOW-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-SLOW-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31 ; CHECK-SLOW-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0 - ; CHECK-SLOW-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-SLOW-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-SLOW-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]] ; CHECK-SLOW-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY [[COPY]] @@ -695,7 +695,7 @@ body: | ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[UBFMXri]] ; CHECK-NEXT: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[COPY1]], [[COPY]], 0, 1 :: (load (s32) from %ir.addr) ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[LDRWroX]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri [[UBFMXri]], 2, 0 ; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[SUBREG_TO_REG]], [[ADDXri]] ; CHECK-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr]], [[ADDXrr1]] diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir index 85c2b61aa6740..9283adfaf20df 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir @@ -80,7 +80,7 @@ body: | ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: liveins: $h0 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG $h0, %subreg.hsub ; CHECK-NEXT: %copy:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1 @@ -117,7 +117,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %copy:gpr32 = COPY $w0 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %copy, 0 - ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %zext.sub_32 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir index 64d09ea682e4a..205064a851618 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir @@ -136,7 +136,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK-NEXT: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY]] ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[ORNWrr]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: TBNZX [[SUBREG_TO_REG]], 63, %bb.1 ; CHECK-NEXT: B %bb.0 ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir index a422f60aacc0f..d083e49e1e596 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir @@ -163,7 +163,7 @@ body: | ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32 ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; SELECT-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234567 - ; SELECT-NEXT: %cmp_rhs:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; SELECT-NEXT: %cmp_rhs:gpr64sp = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; SELECT-NEXT: $w0 = COPY %cmp @@ -481,7 +481,7 @@ body: | ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1 ; SELECT-NEXT: %shl_lhs:gpr64 = COPY $x0 ; SELECT-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 64 - ; SELECT-NEXT: %too_large:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; SELECT-NEXT: %too_large:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; SELECT-NEXT: %cmp_lhs:gpr64 = LSLVXr %shl_lhs, %too_large ; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir index e53380c18beb1..5721f235de460 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir @@ -30,7 +30,7 @@ body: | ; CHECK-NEXT: FCMPSrr [[COPY3]], [[COPY4]], implicit-def $nzcv, implicit $fpcr ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv ; CHECK-NEXT: [[SUBWri:%[0-9]+]]:gpr32common = SUBWri [[COPY1]], 1, 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBWri]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[SUBWri]], %subreg.sub_32 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[DEF]] ; CHECK-NEXT: FCMPSrr [[COPY5]], [[COPY4]], implicit-def $nzcv, implicit $fpcr ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv @@ -64,7 +64,7 @@ body: | FCMPSrr %29, %4, implicit-def $nzcv, implicit $fpcr %28:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv %7:gpr32 = SUBSWri %1, 1, 0, implicit-def $nzcv - %8:gpr64 = SUBREG_TO_REG 0, %7, %subreg.sub_32 + %8:gpr64 = SUBREG_TO_REG %7, %subreg.sub_32 %30:fpr32 = COPY %3 FCMPSrr %30, %4, implicit-def $nzcv, implicit $fpcr %27:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir index 34dbad5a94977..7620c729d580e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir @@ -32,7 +32,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2 ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]], implicit $fpcr - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[FCVTHSr]], %subreg.hsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: STRHHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `ptr undef`) ; CHECK-NEXT: B %bb.2 @@ -163,7 +163,7 @@ body: | ; CHECK-NEXT: %gp_phi1:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2 ; CHECK-NEXT: %gp_phi2:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2 ; CHECK-NEXT: %gp_phi3:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %fp_phi, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %fp_phi, %subreg.hsub ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir index 2ca371beb5028..e4d6ad8320ab7 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir @@ -677,7 +677,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32 ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) @@ -713,7 +713,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32 ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 7 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) @@ -749,7 +749,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32 ; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 15 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) @@ -785,7 +785,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32 ; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 7 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir index 6b4bbb85b2ec4..da3c962f2468e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir @@ -51,7 +51,7 @@ body: | ; CHECK-LABEL: name: anyext_load_monotonic_i32 ; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY $xzr ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load monotonic (s32) from `ptr null`) - ; CHECK-NEXT: %ld:gpr64all = SUBREG_TO_REG 0, [[LDRWui]], %subreg.sub_32 + ; CHECK-NEXT: %ld:gpr64all = SUBREG_TO_REG [[LDRWui]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY %ld ; CHECK-NEXT: RET_ReallyLR implicit $x0 %1:gpr(p0) = G_CONSTANT i64 0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir index 5efa45dd78075..457c5d6411b64 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir @@ -32,7 +32,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[SWPX:%[0-9]+]]:gpr64 = SWPX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr) ; CHECK-NEXT: $x0 = COPY [[SWPX]] %0:gpr(p0) = COPY $x0 @@ -54,7 +54,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr) ; CHECK-NEXT: $x0 = COPY [[LDADDX]] %0:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir index d3d413c34ea72..0b2121db4e7c4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir @@ -250,7 +250,7 @@ body: | ; CHECK: liveins: $s0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %val:fpr32 = COPY $s0 - ; CHECK-NEXT: %bv:fpr128 = SUBREG_TO_REG 0, %val, %subreg.ssub + ; CHECK-NEXT: %bv:fpr128 = SUBREG_TO_REG %val, %subreg.ssub ; CHECK-NEXT: $q0 = COPY %bv ; CHECK-NEXT: RET_ReallyLR implicit $q0 %val:fpr(s32) = COPY $s0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir index df4e7ddaac8b9..6154fd27406bf 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir @@ -62,7 +62,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 13132 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBREG_TO_REG]], implicit-def $nzcv ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK-NEXT: $w0 = COPY [[CSINCWr]] @@ -231,7 +231,7 @@ body: | ; CHECK-LABEL: name: cmp_arith_extended_s32 ; CHECK: liveins: $w0, $w1, $h0 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG $h0, %subreg.hsub ; CHECK-NEXT: %reg0:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: %reg1:gpr32sp = COPY $w1 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %reg0 @@ -266,7 +266,7 @@ body: | ; CHECK-NEXT: %reg0:gpr32 = COPY $w0 ; CHECK-NEXT: %reg1:gpr64 = COPY $x1 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %reg0, 0 - ; CHECK-NEXT: %ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %ext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %reg1, %ext, 5, implicit-def $nzcv ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv ; CHECK-NEXT: $w0 = COPY %cmp @@ -425,7 +425,7 @@ body: | ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %cmp, 0 - ; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: %add:gpr64 = ADDXrr %cmp_ext, %add_rhs ; CHECK-NEXT: %or:gpr64 = ORRXrr %add, %cmp_ext ; CHECK-NEXT: $x0 = COPY %or @@ -461,7 +461,7 @@ body: | ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %cmp, 0 - ; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: %add:gpr64 = ADDXrr %cmp_ext, %add_rhs ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], %cmp, %subreg.sub_32 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir index be5939c346223..33cb75f7b8f46 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir @@ -47,7 +47,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[CASX:%[0-9]+]]:gpr64 = CASX [[COPY1]], [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr) ; CHECK-NEXT: $x0 = COPY [[CASX]] %0:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir index 417ac91113f2c..72e691bf520ea 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir @@ -213,7 +213,7 @@ body: | bb.0: ; CHECK-LABEL: name: opt_i64 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s64) = G_CONSTANT i64 42 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir index 55dfbcd7a88a8..69f97f449b430 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir @@ -67,7 +67,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[UMOVvi32_:%[0-9]+]]:gpr32 = UMOVvi32 [[COPY]], 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UMOVvi32_]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[UMOVvi32_]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:fpr(<4 x s32>) = COPY $q0 @@ -95,7 +95,7 @@ body: | ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[UMOVvi32_:%[0-9]+]]:gpr32 = UMOVvi32 [[INSERT_SUBREG]], 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UMOVvi32_]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[UMOVvi32_]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:fpr(<2 x s32>) = COPY $d0 @@ -323,7 +323,7 @@ body: | ; CHECK-LABEL: name: skip_anyext_to_16 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr8 = COPY [[DEF]].bsub - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[COPY]], %subreg.bsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $w0 = COPY [[COPY1]] %5:fpr(<16 x s8>) = G_IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir index 80c2f8ca08608..b485cd2e88edd 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir @@ -17,7 +17,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG 0, %4, %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG %4, %subreg.bsub ; CHECK-NEXT: $h0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -44,7 +44,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %4, %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.bsub ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -71,7 +71,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.bsub ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -98,7 +98,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (s16)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %4, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.hsub ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -125,7 +125,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (s16)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.hsub ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -152,7 +152,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpost [[COPY]], 4 :: (load (s32)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.ssub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.ssub ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -179,7 +179,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG 0, %4, %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG %4, %subreg.bsub ; CHECK-NEXT: $h0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -206,7 +206,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %4, %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.bsub ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -233,7 +233,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.bsub ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -260,7 +260,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (s16)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %4, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.hsub ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -287,7 +287,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (s16)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.hsub ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -314,7 +314,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpre [[COPY]], 4 :: (load (s32)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.ssub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.ssub ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir index 9f02f31a15e32..ce7dc4feb187c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir @@ -62,14 +62,14 @@ body: | ; CHECK: liveins: $w0, $w1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; ; CHECK-TINY-LABEL: name: imm_s64_gpr ; CHECK-TINY: liveins: $w0, $w1 ; CHECK-TINY-NEXT: {{ $}} ; CHECK-TINY-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234 - ; CHECK-TINY-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-TINY-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-TINY-NEXT: $x0 = COPY [[SUBREG_TO_REG]] %0(s64) = G_CONSTANT i64 1234 $x0 = COPY %0(s64) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir index f4675e1b752aa..78d86a6821877 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir @@ -15,9 +15,9 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY]], %subreg.sub_32 ; CHECK-NEXT: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG]], 0, 31 - ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY]], %subreg.sub_32 ; CHECK-NEXT: [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 51, 31 ; CHECK-NEXT: $x0 = COPY [[BFMXri]] ; CHECK-NEXT: $x1 = COPY [[BFMXri1]] diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir index e3712db51ad3a..c2d03330cf41c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir @@ -176,7 +176,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[COPY]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] %0(s32) = COPY $w0 %1(s64) = G_ZEXT %0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir index 4ac009de19113..92121b0b42162 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir @@ -26,7 +26,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG [[LDRBBui]], %subreg.sub_32 ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 8, 0, implicit-def $nzcv ; CHECK-NEXT: Bcc 8, %bb.3, implicit $nzcv ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir index afc5ea2e64b7e..8b1f73ec11937 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir @@ -61,7 +61,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def dead $nzcv ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[SUBSWri]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv ; CHECK-NEXT: Bcc 8, %bb.4, implicit $nzcv ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir index 79b0e678a62de..6526cd977eb55 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir @@ -22,7 +22,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDAXRB:%[0-9]+]]:gpr32 = LDAXRB [[COPY]] :: (volatile load (s8) from %ir.addr) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDAXRB]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDAXRB]], %subreg.sub_32 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x1 %0:gpr(p0) = COPY $x0 @@ -45,7 +45,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDAXRH:%[0-9]+]]:gpr32 = LDAXRH [[COPY]] :: (volatile load (s16) from %ir.addr) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDAXRH]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDAXRH]], %subreg.sub_32 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x1 %0:gpr(p0) = COPY $x0 @@ -68,7 +68,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDAXRW:%[0-9]+]]:gpr32 = LDAXRW [[COPY]] :: (volatile load (s32) from %ir.addr) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDAXRW]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDAXRW]], %subreg.sub_32 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x1 %0:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir index 93d3aec10235f..1eaafd517d986 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir @@ -21,7 +21,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDXRB:%[0-9]+]]:gpr32 = LDXRB [[COPY]] :: (volatile load (s8) from %ir.addr) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRB]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDXRB]], %subreg.sub_32 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x1 %0:gpr(p0) = COPY $x0 @@ -44,7 +44,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDXRH:%[0-9]+]]:gpr32 = LDXRH [[COPY]] :: (volatile load (s16) from %ir.addr) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRH]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDXRH]], %subreg.sub_32 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x1 %0:gpr(p0) = COPY $x0 @@ -67,7 +67,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDXRW:%[0-9]+]]:gpr32 = LDXRW [[COPY]] :: (volatile load (s32) from %ir.addr) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRW]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDXRW]], %subreg.sub_32 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x1 %0:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir index bd97890866fd5..bc094e7703b97 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir @@ -711,7 +711,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (s16)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[LDRHui]], %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[LDRHui]], %subreg.hsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $w0 = COPY [[COPY1]] ; CHECK-NEXT: RET_ReallyLR @@ -745,7 +745,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[LDRBui]], %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[LDRBui]], %subreg.bsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $w0 = COPY [[COPY1]] ; CHECK-NEXT: RET_ReallyLR diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir index d0314682a441c..349513158e41c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir @@ -52,7 +52,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10000 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY [[ADDXrr]] %0:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir index d2caee5683f99..87acc06df1940 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir @@ -18,7 +18,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x s8>)) ; CHECK-NEXT: [[ADDVv16i8v:%[0-9]+]]:fpr8 = ADDVv16i8v [[LDRQui]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[ADDVv16i8v]], %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[ADDVv16i8v]], %subreg.bsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $w0 = COPY [[COPY1]] ; CHECK-NEXT: RET_ReallyLR implicit $w0 @@ -49,7 +49,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x s16>)) ; CHECK-NEXT: [[ADDVv8i16v:%[0-9]+]]:fpr16 = ADDVv8i16v [[LDRQui]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[ADDVv8i16v]], %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[ADDVv8i16v]], %subreg.hsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $w0 = COPY [[COPY1]] ; CHECK-NEXT: RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir index 4e7affc12b092..3103ef512ad00 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir @@ -21,7 +21,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY1]], [[COPY]] ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[ADDWrr]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s32) = COPY $w0 @@ -48,7 +48,7 @@ body: | ; CHECK: liveins: $w0, $w1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[DEF]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[DEF]], %subreg.sub_32 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15 ; CHECK-NEXT: $x0 = COPY [[UBFMXri]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 @@ -74,7 +74,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %copy:gpr32 = COPY $w0 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %copy, 0 - ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY %zext ; CHECK-NEXT: RET_ReallyLR implicit $x0 %copy:gpr(s32) = COPY $w0 @@ -100,7 +100,7 @@ body: | ; CHECK-NEXT: %copy:gpr32all = COPY $w0 ; CHECK-NEXT: %bitcast1:gpr32 = COPY %copy ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %bitcast1, 0 - ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY %zext ; CHECK-NEXT: RET_ReallyLR implicit $x0 %copy:gpr(s32) = COPY $w0 @@ -128,7 +128,7 @@ body: | ; CHECK-NEXT: %copy:gpr64sp = COPY $x0 ; CHECK-NEXT: %trunc:gpr32common = COPY %copy.sub_32 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %trunc, 0 - ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY %zext ; CHECK-NEXT: RET_ReallyLR implicit $x0 %copy:gpr(s64) = COPY $x0 @@ -161,7 +161,7 @@ body: | ; CHECK-NEXT: bb.2: ; CHECK-NEXT: %phi:gpr32 = PHI %copy1, %bb.0, %copy2, %bb.1 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %phi, 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 ; We should have a ORRWrs here, because isDef32 disallows phis. @@ -202,7 +202,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY1]], [[COPY]] ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[ADDWrr]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s32) = COPY $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir index dc213520f320d..42b1c61949b94 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir @@ -25,8 +25,8 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY $w0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY $w1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 - ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32 ; CHECK-NEXT: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[SUBREG_TO_REG]], [[SUBREG_TO_REG1]], 32, 31 ; CHECK-NEXT: $x0 = COPY [[BFMXri]] %0(s32) = COPY $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir index 0cb95de0640be..c802914bbb981 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir @@ -193,7 +193,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 8000 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32 ; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]] @@ -220,7 +220,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 8000 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32 ; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]] diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir index e26c143135097..e36e8c8b5ab29 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir @@ -575,7 +575,7 @@ body: | ; CHECK-NEXT: %t:gpr64 = COPY $x2 ; CHECK-NEXT: %negative_one:gpr32 = MOVi32imm -1 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %negative_one, 0 - ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: %xor:gpr64 = EORXrr %reg1, %zext ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv ; CHECK-NEXT: %select:gpr64 = CSELXr %t, %xor, 1, implicit $nzcv diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir index b207c851c8ba4..33c56c4a6d044 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir @@ -25,7 +25,7 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-NEXT: STLRW [[COPY2]], [[COPY]] :: (store release (s32)) ; CHECK-NEXT: {{ $}} @@ -71,7 +71,7 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-NEXT: STLRH [[COPY2]], [[COPY]] :: (store release (s16)) ; CHECK-NEXT: {{ $}} @@ -117,7 +117,7 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-NEXT: STLRB [[COPY2]], [[COPY]] :: (store release (s8)) ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir index d3636c1380d2e..ae10f4a5b30ab 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir @@ -24,7 +24,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRBBui]], %subreg.sub_32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096 ; CHECK-NEXT: $x0 = COPY [[ANDXri]] diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir index bbf573c3a6c81..0cf16ec9f8e95 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir @@ -52,7 +52,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRWui]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRWui]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(p0) = COPY $x0 @@ -74,7 +74,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRHHui]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRHHui]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(p0) = COPY $x0 @@ -96,7 +96,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRBBui]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir index 92a37ebf87d9a..8995d2616e52b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir @@ -55,7 +55,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %reg:gpr32 = COPY $w0 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %reg, 0 - ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: TBZX %zext, 33, %bb.1 ; CHECK-NEXT: B %bb.0 ; CHECK-NEXT: {{ $}} @@ -90,7 +90,7 @@ body: | ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %reg:gpr32 = IMPLICIT_DEF - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %reg, %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG %reg, %subreg.sub_32 ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15 ; CHECK-NEXT: TBZX %zext, 33, %bb.1 ; CHECK-NEXT: B %bb.0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir index 0f430dcc8f5c8..4bf7a93239eff 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir @@ -51,7 +51,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %copy:gpr64sp = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 61440 - ; CHECK-NEXT: %cst:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: %cst:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: %load:gpr64 = LDRXroX %copy, %cst, 0, 0 :: (volatile load (s64)) ; CHECK-NEXT: RET_ReallyLR %copy:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-limit-size.mir b/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-limit-size.mir index 17c15124e787e..95ca948a30fd6 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-limit-size.mir +++ b/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-limit-size.mir @@ -13,7 +13,7 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY $x4 ; CHECK-NEXT: [[LD_i32:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], killed [[COPY1]], 0, 1 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i32]], %subreg.ssub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i32]], %subreg.ssub ; CHECK-NEXT: [[LD_LANE_1:%[0-9]+]]:fpr128 = LD1i32 [[FIRST_REG]], 1, killed [[COPY2]] ; CHECK-NEXT: [[LD_LANE_2:%[0-9]+]]:fpr128 = LD1i32 [[LD_LANE_1]], 2, killed [[COPY3]] ; CHECK-NEXT: [[LD_LANE_3:%[0-9]+]]:fpr128 = LD1i32 [[LD_LANE_2]], 3, killed [[COPY4]] @@ -25,7 +25,7 @@ body: | %3:gpr64common = COPY $x3 %4:gpr64common = COPY $x4 %5:fpr32 = LDRSroX %0, killed %1, 0, 1 - %6:fpr128 = SUBREG_TO_REG 0, killed %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG killed %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 1, killed %2 %8:fpr128 = LD1i32 %7, 2, killed %3 %9:fpr128 = LD1i32 %8, 3, killed %4 diff --git a/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-with-call.mir b/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-with-call.mir index 6b338d98afb53..dee222faf20b1 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-with-call.mir +++ b/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-with-call.mir @@ -20,7 +20,7 @@ body: | ; CHECK-NEXT: [[PTR_2:%[0-9]+]]:gpr64common = COPY $x2 ; CHECK-NEXT: [[PTR_3:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[LD_i32:%[0-9]+]]:fpr32 = LDRSroX [[BASE_REG]], killed [[PTR_1]], 0, 1 - ; CHECK-NEXT: [[LD_LANE_0:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i32]], %subreg.ssub + ; CHECK-NEXT: [[LD_LANE_0:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i32]], %subreg.ssub ; CHECK-NEXT: [[LD_LANE_1:%[0-9]+]]:fpr128 = LD1i32 [[LD_LANE_0]], 1, [[PTR_2]] ; CHECK-NEXT: $x0 = COPY [[PTR_2]] ; CHECK-NEXT: BL @external_func, csr_aarch64_aapcs, implicit-def $lr, implicit $x0, implicit-def $x0 @@ -34,7 +34,7 @@ body: | %2:gpr64common = COPY $x2 %3:gpr64common = COPY $x3 %5:fpr32 = LDRSroX %0, killed %1, 0, 1 - %6:fpr128 = SUBREG_TO_REG 0, killed %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG killed %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 1, %2 $x0 = COPY %2 BL @external_func, csr_aarch64_aapcs, implicit-def $lr, implicit $x0, implicit-def $x0 diff --git a/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir b/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir index a7570d2293f8a..be4448928fdcf 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir +++ b/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir @@ -14,10 +14,10 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY $x4 ; CHECK-NEXT: [[LD_i32:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], [[COPY1]], 0, 1 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, [[LD_i32]], %subreg.ssub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG [[LD_i32]], %subreg.ssub ; CHECK-NEXT: [[LD0_1:%[0-9]+]]:fpr128 = LD1i32 [[FIRST_REG]], 1, [[COPY2]] ; CHECK-NEXT: [[LD1_0:%[0-9]+]]:fpr32 = LDRSui [[COPY3]], 0 - ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD1_0]], %subreg.ssub + ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD1_0]], %subreg.ssub ; CHECK-NEXT: [[LD1_1:%[0-9]+]]:fpr128 = LD1i32 [[SECOND_REG]], 1, [[COPY4]] ; CHECK-NEXT: [[ZIP:%[0-9]+]]:fpr128 = ZIP1v2i64 [[LD0_1]], [[LD1_1]] ; CHECK-NEXT: $q0 = COPY [[ZIP]] @@ -28,7 +28,7 @@ body: | %3:gpr64common = COPY $x3 %4:gpr64common = COPY $x4 %5:fpr32 = LDRSroX %0, %1, 0, 1 - %6:fpr128 = SUBREG_TO_REG 0, %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 1, %2 %8:fpr128 = LD1i32 %7, 2, %3 %9:fpr128 = LD1i32 %8, 3, %4 @@ -48,10 +48,10 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY $x4 ; CHECK-NEXT: [[LD_i32:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i32]], %subreg.ssub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i32]], %subreg.ssub ; CHECK-NEXT: [[LD0_1:%[0-9]+]]:fpr128 = LD1i32 [[FIRST_REG]], 1, killed [[COPY1]] ; CHECK-NEXT: [[LD1_0:%[0-9]+]]:fpr32 = LDRSui [[COPY2]], 0 - ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD1_0]], %subreg.ssub + ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD1_0]], %subreg.ssub ; CHECK-NEXT: [[LD1_1:%[0-9]+]]:fpr128 = LD1i32 [[SECOND_REG]], 1, killed [[COPY3]] ; CHECK-NEXT: [[ZIP:%[0-9]+]]:fpr128 = ZIP1v2i64 [[LD0_1]], [[LD1_1]] ; CHECK-NEXT: $q0 = COPY [[ZIP]] @@ -62,7 +62,7 @@ body: | %3:gpr64common = COPY $x3 %4:gpr64common = COPY $x4 %5:fpr32 = LDRSui %0, 0 - %6:fpr128 = SUBREG_TO_REG 0, killed %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG killed %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 1, killed %1 %8:fpr128 = LD1i32 %7, 2, killed %2 %9:fpr128 = LD1i32 %8, 3, killed %3 @@ -86,12 +86,12 @@ body: | ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr64common = COPY $x7 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr64common = COPY $x8 ; CHECK-NEXT: [[LD_i16:%[0-9]+]]:fpr16 = LDRHroX [[COPY]], killed [[COPY1]], 0, 1 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i16]], %subreg.hsub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i16]], %subreg.hsub ; CHECK-NEXT: [[LD0_1:%[0-9]+]]:fpr128 = LD1i16 [[FIRST_REG]], 1, killed [[COPY2]] ; CHECK-NEXT: [[LD0_2:%[0-9]+]]:fpr128 = LD1i16 [[LD0_1]], 2, killed [[COPY3]] ; CHECK-NEXT: [[LD0_3:%[0-9]+]]:fpr128 = LD1i16 [[LD0_2]], 3, killed [[COPY4]] ; CHECK-NEXT: [[LD1_0:%[0-9]+]]:fpr16 = LDRHui [[COPY5]], 0 - ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD1_0]], %subreg.hsub + ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD1_0]], %subreg.hsub ; CHECK-NEXT: [[LD1_1:%[0-9]+]]:fpr128 = LD1i16 [[SECOND_REG]], 1, killed [[COPY6]] ; CHECK-NEXT: [[LD1_2:%[0-9]+]]:fpr128 = LD1i16 [[LD1_1]], 2, killed [[COPY7]] ; CHECK-NEXT: [[LD1_3:%[0-9]+]]:fpr128 = LD1i16 [[LD1_2]], 3, killed [[COPY8]] @@ -108,7 +108,7 @@ body: | %7:gpr64common = COPY $x7 %8:gpr64common = COPY $x8 %9:fpr16 = LDRHroX %0, killed %1, 0, 1 - %10:fpr128 = SUBREG_TO_REG 0, killed %9, %subreg.hsub + %10:fpr128 = SUBREG_TO_REG killed %9, %subreg.hsub %11:fpr128 = LD1i16 %10, 1, killed %2 %12:fpr128 = LD1i16 %11, 2, killed %3 %13:fpr128 = LD1i16 %12, 3, killed %4 @@ -136,12 +136,12 @@ body: | ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr64common = COPY $x7 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr64common = COPY $x8 ; CHECK-NEXT: [[LD_i16:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i16]], %subreg.hsub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i16]], %subreg.hsub ; CHECK-NEXT: [[LD0_1:%[0-9]+]]:fpr128 = LD1i16 [[FIRST_REG]], 1, killed [[COPY1]] ; CHECK-NEXT: [[LD0_2:%[0-9]+]]:fpr128 = LD1i16 [[LD0_1]], 2, killed [[COPY2]] ; CHECK-NEXT: [[LD0_3:%[0-9]+]]:fpr128 = LD1i16 [[LD0_2]], 3, killed [[COPY3]] ; CHECK-NEXT: [[LD1_0:%[0-9]+]]:fpr16 = LDRHui [[COPY4]], 0 - ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD1_0]], %subreg.hsub + ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD1_0]], %subreg.hsub ; CHECK-NEXT: [[LD1_1:%[0-9]+]]:fpr128 = LD1i16 [[SECOND_REG]], 1, killed [[COPY5]] ; CHECK-NEXT: [[LD1_2:%[0-9]+]]:fpr128 = LD1i16 [[LD1_1]], 2, killed [[COPY6]] ; CHECK-NEXT: [[LD1_3:%[0-9]+]]:fpr128 = LD1i16 [[LD1_2]], 3, killed [[COPY7]] @@ -158,7 +158,7 @@ body: | %7:gpr64common = COPY $x7 %8:gpr64common = COPY $x8 %9:fpr16 = LDRHui %0, 0 - %10:fpr128 = SUBREG_TO_REG 0, killed %9, %subreg.hsub + %10:fpr128 = SUBREG_TO_REG killed %9, %subreg.hsub %11:fpr128 = LD1i16 %10, 1, killed %1 %12:fpr128 = LD1i16 %11, 2, killed %2 %13:fpr128 = LD1i16 %12, 3, killed %3 @@ -194,7 +194,7 @@ body: | ; CHECK-NEXT: [[COPY15:%[0-9]+]]:gpr64common = COPY $x15 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:gpr64common = COPY $x16 ; CHECK-NEXT: [[LD_i8:%[0-9]+]]:fpr8 = LDRBroX [[COPY]], killed [[COPY1]], 0, 0 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i8]], %subreg.bsub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i8]], %subreg.bsub ; CHECK-NEXT: [[LD0_1:%[0-9]+]]:fpr128 = LD1i8 [[FIRST_REG]], 1, killed [[COPY2]] ; CHECK-NEXT: [[LD0_2:%[0-9]+]]:fpr128 = LD1i8 [[LD0_1]], 2, killed [[COPY3]] ; CHECK-NEXT: [[LD0_3:%[0-9]+]]:fpr128 = LD1i8 [[LD0_2]], 3, killed [[COPY4]] @@ -203,7 +203,7 @@ body: | ; CHECK-NEXT: [[LD0_6:%[0-9]+]]:fpr128 = LD1i8 [[LD0_5]], 6, killed [[COPY7]] ; CHECK-NEXT: [[LD0_7:%[0-9]+]]:fpr128 = LD1i8 [[LD0_6]], 7, killed [[COPY8]] ; CHECK-NEXT: [[LD1_0:%[0-9]+]]:fpr8 = LDRBui [[COPY9]], 0 - ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD1_0]], %subreg.bsub + ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD1_0]], %subreg.bsub ; CHECK-NEXT: [[LD1_1:%[0-9]+]]:fpr128 = LD1i8 [[SECOND_REG]], 1, killed [[COPY10]] ; CHECK-NEXT: [[LD1_2:%[0-9]+]]:fpr128 = LD1i8 [[LD1_1]], 2, killed [[COPY11]] ; CHECK-NEXT: [[LD1_3:%[0-9]+]]:fpr128 = LD1i8 [[LD1_2]], 3, killed [[COPY12]] @@ -232,7 +232,7 @@ body: | %15:gpr64common = COPY $x15 %16:gpr64common = COPY $x16 %17:fpr8 = LDRBroX %0, killed %1, 0, 0 - %18:fpr128 = SUBREG_TO_REG 0, killed %17, %subreg.bsub + %18:fpr128 = SUBREG_TO_REG killed %17, %subreg.bsub %19:fpr128 = LD1i8 %18, 1, killed %2 %20:fpr128 = LD1i8 %19, 2, killed %3 %21:fpr128 = LD1i8 %20, 3, killed %4 @@ -280,10 +280,10 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY $x4 ; CHECK-NEXT: [[LD_i32:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], killed [[COPY1]], 0, 1 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i32]], %subreg.ssub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i32]], %subreg.ssub ; CHECK-NEXT: [[LD0_1:%[0-9]+]]:fpr128 = LD1i32 [[FIRST_REG]], 1, killed [[COPY3]] ; CHECK-NEXT: [[LD1_0:%[0-9]+]]:fpr32 = LDRSui [[COPY2]], 0 - ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD1_0]], %subreg.ssub + ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD1_0]], %subreg.ssub ; CHECK-NEXT: [[LD1_1:%[0-9]+]]:fpr128 = LD1i32 [[SECOND_REG]], 1, killed [[COPY4]] ; CHECK-NEXT: [[ZIP:%[0-9]+]]:fpr128 = ZIP1v2i64 [[LD0_1]], [[LD1_1]] ; CHECK-NEXT: $q0 = COPY [[ZIP]] @@ -294,7 +294,7 @@ body: | %3:gpr64common = COPY $x3 %4:gpr64common = COPY $x4 %5:fpr32 = LDRSroX %0, killed %1, 0, 1 - %6:fpr128 = SUBREG_TO_REG 0, killed %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG killed %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 2, killed %2 %8:fpr128 = LD1i32 %7, 1, killed %3 %9:fpr128 = LD1i32 %8, 3, killed %4 @@ -342,7 +342,7 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY $x4 ; CHECK-NEXT: [[LD_i32:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], killed [[COPY1]], 0, 1 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i32]], %subreg.ssub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i32]], %subreg.ssub ; CHECK-NEXT: [[LD_LANE_1:%[0-9]+]]:fpr128 = LD1i32 [[FIRST_REG]], 1, killed [[COPY2]] ; CHECK-NEXT: [[LD_LANE_2:%[0-9]+]]:fpr128 = LD1i32 [[LD_LANE_1]], 2, killed [[COPY3]] ; CHECK-NEXT: [[LD_LANE_3:%[0-9]+]]:fpr128 = LD1i32 [[LD_LANE_2]], 3, killed [[COPY4]] @@ -355,7 +355,7 @@ body: | %3:gpr64common = COPY $x3 %4:gpr64common = COPY $x4 %5:fpr32 = LDRSroX %0, killed %1, 0, 1 - %6:fpr128 = SUBREG_TO_REG 0, killed %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG killed %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 1, killed %2 %8:fpr128 = LD1i32 %7, 2, killed %3 %9:fpr128 = LD1i32 %8, 3, killed %4 @@ -377,7 +377,7 @@ body: | ; CHECK-NEXT: [[ALIAS_ADDR:%[0-9]+]]:gpr64common = COPY $x2 ; CHECK-NEXT: [[OTHER_ADDR:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[LOAD0:%[0-9]+]]:fpr32 = LDRSroX [[BASE_PTR]], killed [[OFFSET_PTR]], 0, 1 - ; CHECK-NEXT: [[VEC0:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LOAD0]], %subreg.ssub + ; CHECK-NEXT: [[VEC0:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LOAD0]], %subreg.ssub ; CHECK-NEXT: [[VEC1:%[0-9]+]]:fpr128 = LD1i32 [[VEC0]], 1, [[ALIAS_ADDR]] ; CHECK-NEXT: [[CONST:%[0-9]+]]:gpr32 = MOVi32imm 99 ; CHECK-NEXT: STRWui [[CONST]], [[ALIAS_ADDR]], 0 @@ -390,7 +390,7 @@ body: | %2:gpr64common = COPY $x2 %3:gpr64common = COPY $x3 %5:fpr32 = LDRSroX %0, killed %1, 0, 1 - %6:fpr128 = SUBREG_TO_REG 0, killed %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG killed %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 1, %2 %10:gpr32 = MOVi32imm 99 STRWui %10, %2, 0 diff --git a/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mir b/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mir index 431e457ad38a3..851944b1beec0 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mir +++ b/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mir @@ -15,7 +15,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $xzr ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[COPY1]] ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64sp = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.13: ; CHECK-NEXT: successors: %bb.14(0x80000000), %bb.15(0x00000000) @@ -23,7 +23,7 @@ body: | ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = nsw SUBSXri [[SUBREG_TO_REG]], 1, 0, implicit-def $nzcv ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64all = COPY [[SUBSXri]] - ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: Bcc 0, %bb.15, implicit $nzcv ; CHECK-NEXT: B %bb.14 ; CHECK-NEXT: {{ $}} @@ -36,7 +36,7 @@ body: | ; CHECK-NEXT: STRDui [[PHI2]], [[COPY]], 0 ; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 ; CHECK-NEXT: [[SUBSXri1:%[0-9]+]]:gpr64 = nsw SUBSXri [[PHI]], 1, 0, implicit-def $nzcv - ; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64all = COPY [[SUBSXri1]] ; CHECK-NEXT: Bcc 1, %bb.14, implicit $nzcv ; CHECK-NEXT: B %bb.15 @@ -170,7 +170,7 @@ body: | %1:gpr64sp = COPY $xzr %2:gpr64all = COPY %1 %3:gpr32 = MOVi32imm 1 - %4:gpr64all = SUBREG_TO_REG 0, %3, %subreg.sub_32 + %4:gpr64all = SUBREG_TO_REG %3, %subreg.sub_32 bb.1: successors: %bb.2(0x04000000), %bb.1(0x7c000000) @@ -181,7 +181,7 @@ body: | STRDui killed %9, %0, 0 %10:gpr64 = nsw SUBSXri %5, 1, 0, implicit-def $nzcv %6:gpr64all = COPY %10 - %8:gpr64all = SUBREG_TO_REG 0, %3, %subreg.sub_32 + %8:gpr64all = SUBREG_TO_REG %3, %subreg.sub_32 Bcc 1, %bb.1, implicit $nzcv B %bb.2 diff --git a/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir b/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir index 48f02452e3597..fae2bdcd5e073 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir +++ b/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir @@ -14,7 +14,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 ; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64sp = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.7(0x40000000) @@ -80,7 +80,7 @@ body: | %0:gpr64common = COPY $x0 %1:fpr64 = FMOVD0 %2:gpr32 = MOVi32imm 1 - %3:gpr64all = SUBREG_TO_REG 0, killed %2, %subreg.sub_32 + %3:gpr64all = SUBREG_TO_REG killed %2, %subreg.sub_32 bb.1: successors: %bb.2(0x04000000), %bb.1(0x7c000000) diff --git a/llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir b/llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir index f6c0ec083096e..8f01a17568cda 100644 --- a/llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir +++ b/llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir @@ -38,12 +38,12 @@ body: | ; CHECK-NEXT: [[ADDXri1:%[0-9]+]]:gpr64common = ADDXri [[ADDXri]], 3549, 0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ADDXri1]].sub_32 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 28, 31 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UBFMWri]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[UBFMWri]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr64 = COPY $x0 %1:gpr32 = MOVi32imm 1121757 - %2:gpr64 = SUBREG_TO_REG 0, %1, %subreg.sub_32 + %2:gpr64 = SUBREG_TO_REG %1, %subreg.sub_32 %3:gpr64 = ADDXrr %0, killed %2 %4:gpr64 = UBFMXri %3, 28, 31 $x0 = COPY %4 @@ -62,7 +62,7 @@ body: | ; CHECK-NEXT: [[SUBXri1:%[0-9]+]]:gpr64common = SUBXri [[SUBXri]], 3549, 0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[SUBXri1]].sub_32 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 28, 31 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UBFMWri]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[UBFMWri]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr64 = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/addsub.ll b/llvm/test/CodeGen/AArch64/addsub.ll index bb0d38aff1eb1..b8e5884866476 100644 --- a/llvm/test/CodeGen/AArch64/addsub.ll +++ b/llvm/test/CodeGen/AArch64/addsub.ll @@ -379,7 +379,7 @@ define i1 @uadd_add(i8 %a, i8 %b, ptr %p) { ; This is a unique edge case that will generate the following MIR ; MOVi32imm -1000000 -; SUBREG_TO_REG 0, killed %1, %subreg.sub_32 +; SUBREG_TO_REG killed %1, %subreg.sub_32 ; When using a 64-bit unsigned for the "-1000000" immediate, the code ; must make sure to zero out the top 32 bits since SUBREG_TO_REG is ; zero extending the value diff --git a/llvm/test/CodeGen/AArch64/bf16_fast_math.ll b/llvm/test/CodeGen/AArch64/bf16_fast_math.ll index e52c76fcc3f20..c01b12b0ff202 100644 --- a/llvm/test/CodeGen/AArch64/bf16_fast_math.ll +++ b/llvm/test/CodeGen/AArch64/bf16_fast_math.ll @@ -12,10 +12,10 @@ define bfloat @normal_fadd(bfloat %x, bfloat %y) { ; CHECK-NOBF16-NEXT: {{ $}} ; CHECK-NOBF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NOBF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-NOBF16-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr @@ -36,10 +36,10 @@ define bfloat @normal_fadd(bfloat %x, bfloat %y) { ; CHECK-BF16-NEXT: {{ $}} ; CHECK-BF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-BF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-BF16-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-BF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-BF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr @@ -58,10 +58,10 @@ define bfloat @fast_fadd(bfloat %x, bfloat %y) { ; CHECK-NOBF16-NEXT: {{ $}} ; CHECK-NOBF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NOBF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-NOBF16-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr @@ -82,10 +82,10 @@ define bfloat @fast_fadd(bfloat %x, bfloat %y) { ; CHECK-BF16-NEXT: {{ $}} ; CHECK-BF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-BF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-BF16-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-BF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-BF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr @@ -104,10 +104,10 @@ define bfloat @ninf_fadd(bfloat %x, bfloat %y) { ; CHECK-NOBF16-NEXT: {{ $}} ; CHECK-NOBF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NOBF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-NOBF16-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr @@ -128,10 +128,10 @@ define bfloat @ninf_fadd(bfloat %x, bfloat %y) { ; CHECK-BF16-NEXT: {{ $}} ; CHECK-BF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-BF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-BF16-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-BF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-BF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr @@ -154,10 +154,10 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h2 ; CHECK-NOBF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NOBF16-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY2]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr @@ -169,10 +169,10 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31 ; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]] ; CHECK-NOBF16-NEXT: [[COPY7:%[0-9]+]]:fpr16 = COPY [[COPY6]].hsub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[COPY7]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG killed [[COPY7]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]] ; CHECK-NOBF16-NEXT: [[COPY8:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_2]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]] ; CHECK-NOBF16-NEXT: [[COPY9:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY8]], killed [[COPY9]], implicit $fpcr @@ -193,18 +193,18 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-BF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h2 ; CHECK-BF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-BF16-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-BF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY2]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-BF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-BF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr ; CHECK-BF16-NEXT: [[BFCVT:%[0-9]+]]:fpr16 = nofpexcept BFCVT killed [[FADDSrr]], implicit $fpcr - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[BFCVT]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG killed [[BFCVT]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]] ; CHECK-BF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_2]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]] ; CHECK-BF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub ; CHECK-BF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY5]], killed [[COPY6]], implicit $fpcr @@ -225,10 +225,10 @@ define bfloat @nnan_ninf_contract_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) ; CHECK-NOBF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h2 ; CHECK-NOBF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NOBF16-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY2]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf contract nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr @@ -240,10 +240,10 @@ define bfloat @nnan_ninf_contract_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) ; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31 ; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]] ; CHECK-NOBF16-NEXT: [[COPY7:%[0-9]+]]:fpr16 = COPY [[COPY6]].hsub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[COPY7]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG killed [[COPY7]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]] ; CHECK-NOBF16-NEXT: [[COPY8:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_2]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]] ; CHECK-NOBF16-NEXT: [[COPY9:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = nnan ninf contract nofpexcept FADDSrr killed [[COPY8]], killed [[COPY9]], implicit $fpcr @@ -264,14 +264,14 @@ define bfloat @nnan_ninf_contract_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) ; CHECK-BF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h2 ; CHECK-BF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-BF16-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-BF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY2]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-BF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-BF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf contract nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]] ; CHECK-BF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_2]].ssub ; CHECK-BF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = nnan ninf contract nofpexcept FADDSrr killed [[FADDSrr]], killed [[COPY5]], implicit $fpcr @@ -292,10 +292,10 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h2 ; CHECK-NOBF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NOBF16-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY2]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr @@ -307,10 +307,10 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31 ; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]] ; CHECK-NOBF16-NEXT: [[COPY7:%[0-9]+]]:fpr16 = COPY [[COPY6]].hsub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[COPY7]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG killed [[COPY7]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]] ; CHECK-NOBF16-NEXT: [[COPY8:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_2]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]] ; CHECK-NOBF16-NEXT: [[COPY9:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY8]], killed [[COPY9]], implicit $fpcr @@ -331,18 +331,18 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-BF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h2 ; CHECK-BF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-BF16-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-BF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY2]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-BF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-BF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr ; CHECK-BF16-NEXT: [[BFCVT:%[0-9]+]]:fpr16 = ninf nofpexcept BFCVT killed [[FADDSrr]], implicit $fpcr - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[BFCVT]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG killed [[BFCVT]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]] ; CHECK-BF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_2]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]] ; CHECK-BF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub ; CHECK-BF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY5]], killed [[COPY6]], implicit $fpcr diff --git a/llvm/test/CodeGen/AArch64/coalescer-drop-subreg-to-reg-imm-ops.mir b/llvm/test/CodeGen/AArch64/coalescer-drop-subreg-to-reg-imm-ops.mir index b60f4ffdd880b..1a27c6216af6b 100644 --- a/llvm/test/CodeGen/AArch64/coalescer-drop-subreg-to-reg-imm-ops.mir +++ b/llvm/test/CodeGen/AArch64/coalescer-drop-subreg-to-reg-imm-ops.mir @@ -86,7 +86,7 @@ body: | %8:gpr64 = COPY killed $x0 %9:gpr64 = IMPLICIT_DEF %10:gpr64 = IMPLICIT_DEF - %11:gpr64 = SUBREG_TO_REG 0, killed undef %1, %subreg.sub_32 + %11:gpr64 = SUBREG_TO_REG killed undef %1, %subreg.sub_32 ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp BL @_ZL9testScanfPKcjz, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp diff --git a/llvm/test/CodeGen/AArch64/instr-ref-ldv.ll b/llvm/test/CodeGen/AArch64/instr-ref-ldv.ll index fa00c75e2928b..f12fe1f8c0c0d 100644 --- a/llvm/test/CodeGen/AArch64/instr-ref-ldv.ll +++ b/llvm/test/CodeGen/AArch64/instr-ref-ldv.ll @@ -9,7 +9,7 @@ ; Before aarch64-isel ; %11:gpr32 = ORRWrr $wzr, killed %10:gpr32, debug-location !5; :0 -; %0:gpr64all = SUBREG_TO_REG 0, killed %11:gpr32, %subreg.sub_32, debug-location !5; :0 +; %0:gpr64all = SUBREG_TO_REG killed %11:gpr32, %subreg.sub_32, debug-location !5; :0 ; DBG_INSTR_REF !7, !DIExpression(DW_OP_LLVM_arg, 0), %0:gpr64all, debug-location !11; :0 @[ :0 ] line no:0 ; Before livedebugvalues diff --git a/llvm/test/CodeGen/AArch64/loop-sink.mir b/llvm/test/CodeGen/AArch64/loop-sink.mir index 7e081ecf4c6f5..fcade6c451625 100644 --- a/llvm/test/CodeGen/AArch64/loop-sink.mir +++ b/llvm/test/CodeGen/AArch64/loop-sink.mir @@ -338,7 +338,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr64sp = PHI [[COPY2]], %bb.0, %7, %bb.9 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[PHI]], 0 :: (load (s8) from %ir.lsr.iv) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, killed [[LDRBBui]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG killed [[LDRBBui]], %subreg.sub_32 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32sp = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri killed [[COPY3]], 50, 0, implicit-def $nzcv ; CHECK-NEXT: Bcc 8, %bb.9, implicit $nzcv @@ -433,7 +433,7 @@ body: | %6:gpr64sp = PHI %5, %bb.0, %7, %bb.8 %17:gpr32 = LDRBBui %6, 0 :: (load (s8) from %ir.lsr.iv) - %16:gpr64 = SUBREG_TO_REG 0, killed %17, %subreg.sub_32 + %16:gpr64 = SUBREG_TO_REG killed %17, %subreg.sub_32 %18:gpr32sp = COPY %16.sub_32 %19:gpr32 = SUBSWri killed %18, 50, 0, implicit-def $nzcv Bcc 8, %bb.8, implicit $nzcv diff --git a/llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir b/llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir index 0ebdedadb2b7c..4b3d1e0af73fa 100644 --- a/llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir +++ b/llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir @@ -44,7 +44,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w0 ; CHECK-NEXT: [[SUBWri:%[0-9]+]]:gpr32common = SUBWri [[COPY]], 1, 0 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, killed [[SUBWri]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG killed [[SUBWri]], %subreg.sub_32 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = nuw nsw UBFMXri killed [[SUBREG_TO_REG]], 63, 31 ; CHECK-NEXT: $x0 = COPY [[UBFMXri]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 diff --git a/llvm/test/CodeGen/AArch64/peephole-movd.mir b/llvm/test/CodeGen/AArch64/peephole-movd.mir index bd7f0ab3f044e..3e4224dc29f38 100644 --- a/llvm/test/CodeGen/AArch64/peephole-movd.mir +++ b/llvm/test/CodeGen/AArch64/peephole-movd.mir @@ -13,7 +13,7 @@ body: | ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub ; CHECK-NEXT: [[UQSHLv8i8_shift:%[0-9]+]]:fpr64 = UQSHLv8i8_shift killed [[COPY]], 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, [[UQSHLv8i8_shift]], %subreg.dsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG [[UQSHLv8i8_shift]], %subreg.dsub ; CHECK-NEXT: [[TBLv8i8One:%[0-9]+]]:fpr64 = TBLv8i8One killed [[SUBREG_TO_REG]], [[UQSHLv8i8_shift]] ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[UQSHLv8i8_shift]], %subreg.dsub @@ -22,7 +22,7 @@ body: | %1:fpr64 = COPY %0.dsub:fpr128 %2:fpr64 = UQSHLv8i8_shift killed %1:fpr64, 1 %3:fpr64 = FMOVDr %2:fpr64 - %4:fpr128 = SUBREG_TO_REG 0, killed %3:fpr64, %subreg.dsub + %4:fpr128 = SUBREG_TO_REG killed %3:fpr64, %subreg.dsub %5:fpr64 = TBLv8i8One killed %4:fpr128, %2:fpr64 %7:fpr128 = IMPLICIT_DEF %6:fpr128 = INSERT_SUBREG %7:fpr128, killed %2:fpr64, %subreg.dsub @@ -40,7 +40,7 @@ body: | ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub ; CHECK-NEXT: [[UQSHLv8i8_shift:%[0-9]+]]:fpr64 = UQSHLv8i8_shift killed [[COPY]], 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, [[UQSHLv8i8_shift]], %subreg.dsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG [[UQSHLv8i8_shift]], %subreg.dsub ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[UQSHLv8i8_shift]], %subreg.dsub ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF @@ -50,7 +50,7 @@ body: | %1:fpr64 = COPY %0.dsub:fpr128 %2:fpr64 = UQSHLv8i8_shift killed %1:fpr64, 1 %3:fpr64 = FMOVDr %2:fpr64 - %4:fpr128 = SUBREG_TO_REG 0, %3:fpr64, %subreg.dsub + %4:fpr128 = SUBREG_TO_REG %3:fpr64, %subreg.dsub %7:fpr128 = IMPLICIT_DEF %6:fpr128 = INSERT_SUBREG %7:fpr128, killed %2:fpr64, %subreg.dsub %9:fpr128 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AArch64/peephole-sxtw.mir b/llvm/test/CodeGen/AArch64/peephole-sxtw.mir index b57b2b71dc707..a71c6bc09eb2d 100644 --- a/llvm/test/CodeGen/AArch64/peephole-sxtw.mir +++ b/llvm/test/CodeGen/AArch64/peephole-sxtw.mir @@ -59,7 +59,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK-NEXT: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY2]], [[COPY1]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBWrr]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[SUBWrr]], %subreg.sub_32 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) @@ -83,7 +83,7 @@ body: | %8:gpr32 = COPY $wzr %9:gpr32 = SUBWrr %8, %7 %10:gpr32 = ORRWrs $wzr, %9, 0 - %1:gpr64 = SUBREG_TO_REG 0, %10, %subreg.sub_32 + %1:gpr64 = SUBREG_TO_REG %10, %subreg.sub_32 bb.1: successors: %bb.2(0x80000000) @@ -113,7 +113,7 @@ body: | %0:gpr64 = COPY $x0 %1:gpr32 = COPY %0.sub_32 %2:gpr32 = ORRWrr $wzr, %1 - %3:gpr64 = SUBREG_TO_REG 0, %2, %subreg.sub_32 + %3:gpr64 = SUBREG_TO_REG %2, %subreg.sub_32 %4:gpr32sp = COPY %3.sub_32 %5:gpr32sp = ADDWri %4, 1, 0 $w0 = COPY %5 @@ -131,7 +131,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32 ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr $wzr, [[COPY1]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrr]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrr]], %subreg.sub_32 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32sp = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY2]], 1, 0 ; CHECK-NEXT: $w0 = COPY [[ADDWri]] @@ -140,7 +140,7 @@ body: | %0:gpr64 = COPY $x0 %1:gpr32 = COPY %0.sub_32 %2:gpr32 = ORRWrr $wzr, %1 - %3:gpr64 = SUBREG_TO_REG 0, %2, %subreg.sub_32 + %3:gpr64 = SUBREG_TO_REG %2, %subreg.sub_32 %4:gpr32sp = COPY %3.sub_32 %5:gpr32sp = ADDWri %4, 1, 0 $w0 = COPY %5 diff --git a/llvm/test/CodeGen/AArch64/ptrauth-isel.ll b/llvm/test/CodeGen/AArch64/ptrauth-isel.ll index 6ecfb5852f790..91e8be706ba38 100644 --- a/llvm/test/CodeGen/AArch64/ptrauth-isel.ll +++ b/llvm/test/CodeGen/AArch64/ptrauth-isel.ll @@ -29,7 +29,7 @@ define i64 @small_imm_disc_optimized(i64 %addr) { ; DAGISEL-NEXT: {{ $}} ; DAGISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; DAGISEL-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 - ; DAGISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, killed [[MOVi32imm]], %subreg.sub_32 + ; DAGISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG killed [[MOVi32imm]], %subreg.sub_32 ; DAGISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 42, killed $noreg, implicit-def dead $x16, implicit-def dead $x17 ; DAGISEL-NEXT: $x0 = COPY [[PAC]] ; DAGISEL-NEXT: RET_ReallyLR implicit $x0 @@ -40,7 +40,7 @@ define i64 @small_imm_disc_optimized(i64 %addr) { ; GISEL-NEXT: {{ $}} ; GISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; GISEL-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 - ; GISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; GISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; GISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 42, $noreg, implicit-def dead $x16, implicit-def dead $x17 ; GISEL-NEXT: $x0 = COPY [[PAC]] ; GISEL-NEXT: RET_ReallyLR implicit $x0 @@ -58,7 +58,7 @@ define i64 @small_imm_disc_non_optimized(i64 %addr) noinline optnone { ; DAGISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; DAGISEL-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY killed [[COPY]] ; DAGISEL-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 - ; DAGISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, killed [[MOVi32imm]], %subreg.sub_32 + ; DAGISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG killed [[MOVi32imm]], %subreg.sub_32 ; DAGISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY1]], 2, 42, killed $noreg, implicit-def dead $x16, implicit-def dead $x17 ; DAGISEL-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[PAC]] ; DAGISEL-NEXT: $x0 = COPY [[COPY2]] @@ -85,7 +85,7 @@ define i64 @large_imm_disc_wreg(i64 %addr) { ; DAGISEL-NEXT: {{ $}} ; DAGISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; DAGISEL-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 12345678 - ; DAGISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, killed [[MOVi32imm]], %subreg.sub_32 + ; DAGISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG killed [[MOVi32imm]], %subreg.sub_32 ; DAGISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 0, killed [[SUBREG_TO_REG]], implicit-def dead $x16, implicit-def dead $x17 ; DAGISEL-NEXT: $x0 = COPY [[PAC]] ; DAGISEL-NEXT: RET_ReallyLR implicit $x0 @@ -96,7 +96,7 @@ define i64 @large_imm_disc_wreg(i64 %addr) { ; GISEL-NEXT: {{ $}} ; GISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; GISEL-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 12345678 - ; GISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; GISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; GISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 0, [[SUBREG_TO_REG]], implicit-def dead $x16, implicit-def dead $x17 ; GISEL-NEXT: $x0 = COPY [[PAC]] ; GISEL-NEXT: RET_ReallyLR implicit $x0 diff --git a/llvm/test/CodeGen/AArch64/ptrauth-isel.mir b/llvm/test/CodeGen/AArch64/ptrauth-isel.mir index 1a155887059e3..659910b27a941 100644 --- a/llvm/test/CodeGen/AArch64/ptrauth-isel.mir +++ b/llvm/test/CodeGen/AArch64/ptrauth-isel.mir @@ -169,13 +169,13 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, killed [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG killed [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 42, killed $noreg, implicit-def dead $x16, implicit-def dead $x17 ; CHECK-NEXT: $x0 = COPY [[PAC]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr64 = COPY $x0 %1:gpr32 = MOVi32imm 42 - %2:gpr64noip = SUBREG_TO_REG 0, killed %1, %subreg.sub_32 + %2:gpr64noip = SUBREG_TO_REG killed %1, %subreg.sub_32 %3:gpr64 = PAC %0, 2, 0, killed %2, implicit-def dead $x16, implicit-def dead $x17 $x0 = COPY %3 RET_ReallyLR implicit $x0 @@ -192,13 +192,13 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm target-flags(aarch64-pageoff, aarch64-nc) @globalvar - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, killed [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG killed [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 0, killed [[SUBREG_TO_REG]], implicit-def dead $x16, implicit-def dead $x17 ; CHECK-NEXT: $x0 = COPY [[PAC]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr64 = COPY $x0 %1:gpr32 = MOVi32imm target-flags(aarch64-pageoff, aarch64-nc) @globalvar - %2:gpr64noip = SUBREG_TO_REG 0, killed %1, %subreg.sub_32 + %2:gpr64noip = SUBREG_TO_REG killed %1, %subreg.sub_32 %3:gpr64 = PAC %0, 2, 0, killed %2, implicit-def dead $x16, implicit-def dead $x17 $x0 = COPY %3 RET_ReallyLR implicit $x0 diff --git a/llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir b/llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir index 37540dde048fa..2ec7ec94e2ebb 100644 --- a/llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir +++ b/llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir @@ -27,7 +27,7 @@ body: | ; CHECK-NOT: %3:gpr32 = ORRWrs $wzr, %2, 0 ; The ORRWrs should be removed. %3:gpr32 = ORRWrs $wzr, %2, 0 - %4:gpr64 = SUBREG_TO_REG 0, %3, %subreg.sub_32 + %4:gpr64 = SUBREG_TO_REG %3, %subreg.sub_32 B %bb.3 bb.3: @@ -60,7 +60,7 @@ body: | ; CHECK: %2:gpr32 = ORRWrs $wzr, %1, 0 ; The ORRWrs should not be removed. %2:gpr32 = ORRWrs $wzr, %1, 0 - %3:gpr64 = SUBREG_TO_REG 0, %2, %subreg.sub_32 + %3:gpr64 = SUBREG_TO_REG %2, %subreg.sub_32 B %bb.3 bb.3: diff --git a/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir b/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir index 08fc47d9480ce..2861933350d2e 100644 --- a/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir +++ b/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir @@ -29,7 +29,7 @@ body: | %1:gpr64sp = ADDXri %stack.0, 0, 0 %2:gpr64common = nuw ADDXri killed %1, 64, 0 %3:gpr32 = MOVi32imm 64 - %4:gpr64 = SUBREG_TO_REG 0, killed %3, %subreg.sub_32 + %4:gpr64 = SUBREG_TO_REG killed %3, %subreg.sub_32 %6:gpr64 = COPY %4 %5:gpr64common = COPY killed %2 dead %5:gpr64common, dead early-clobber %6:gpr64 = MOPSMemorySetPseudo %5, %6, %4, implicit-def dead $nzcv @@ -57,7 +57,7 @@ body: | bb.1: bb.2: - %3:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + %3:gpr64all = SUBREG_TO_REG %0, %subreg.sub_32 bb.3: $nzcv = IMPLICIT_DEF @@ -69,7 +69,7 @@ body: | Bcc 1, %bb.6, implicit killed $nzcv bb.5: - %5:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + %5:gpr64all = SUBREG_TO_REG %0, %subreg.sub_32 %4:gpr64 = COPY killed %5 B %bb.7 @@ -103,7 +103,7 @@ body: | bb.1: bb.2: - %3:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + %3:gpr64all = SUBREG_TO_REG %0, %subreg.sub_32 bb.3: $nzcv = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir b/llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir index 1303776230f1a..be99e5b46a10a 100644 --- a/llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir +++ b/llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir @@ -92,7 +92,7 @@ body: | %1:gpr64common = COPY $x0 %3:gpr32common = ADDWri %2, 1, 0 %4:gpr32 = ORRWrs $wzr, killed %3, 0 - %0:gpr64 = SUBREG_TO_REG 0, killed %4, %subreg.sub_32 + %0:gpr64 = SUBREG_TO_REG killed %4, %subreg.sub_32 bb.1.A: successors: %bb.2(0x30000000), %bb.1(0x50000000) diff --git a/llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir b/llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir index c552da3eca0c8..7f28610a312c5 100644 --- a/llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir +++ b/llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir @@ -53,7 +53,7 @@ body: | bb.1.for.body.preheader: %11:gpr32 = ORRWrs $wzr, %9, 0 - %0:gpr64all = SUBREG_TO_REG 0, killed %11, %subreg.sub_32 + %0:gpr64all = SUBREG_TO_REG killed %11, %subreg.sub_32 %14:fpr32 = FMOVSi 112 B %bb.3 diff --git a/llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir b/llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir index 6171abc52bb93..84fe0f6b032dc 100644 --- a/llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir +++ b/llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir @@ -53,7 +53,7 @@ body: | bb.1.for.body.preheader: %11:gpr32 = ORRWrs $wzr, %9, 0 - %0:gpr64all = SUBREG_TO_REG 0, killed %11, %subreg.sub_32 + %0:gpr64all = SUBREG_TO_REG killed %11, %subreg.sub_32 %14:fpr32 = FMOVSi 112 B %bb.3 diff --git a/llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir b/llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir index 630a89364c8c9..7a88bb1363d46 100644 --- a/llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir +++ b/llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir @@ -59,7 +59,7 @@ body: | bb.1.for.body.preheader: %7:gpr32common = SUBWri %5, 1, 0 %9:gpr64all = IMPLICIT_DEF - %8:gpr64 = SUBREG_TO_REG 0, killed %7, %subreg.sub_32 + %8:gpr64 = SUBREG_TO_REG killed %7, %subreg.sub_32 %10:gpr64 = SBFMXri killed %8, 0, 31 %0:gpr64all = COPY %10 %12:fpr32 = FMOVSi 112 diff --git a/llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir b/llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir index cb0b1e3028753..1c0e1cc5aa41f 100644 --- a/llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir +++ b/llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir @@ -59,7 +59,7 @@ body: | bb.1.for.body.preheader: %7:gpr32common = SUBWri %5, 1, 0 %9:gpr64all = IMPLICIT_DEF - %8:gpr64 = SUBREG_TO_REG 0, killed %7, %subreg.sub_32 + %8:gpr64 = SUBREG_TO_REG killed %7, %subreg.sub_32 %10:gpr64 = SBFMXri killed %8, 0, 31 %0:gpr64all = COPY %10 %12:fpr32 = FMOVSi 112 diff --git a/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir b/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir index c1014b296cad3..120ea5dc3ef16 100644 --- a/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir +++ b/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir @@ -178,7 +178,7 @@ body: | successors: %bb.12, %bb.2 %48:gpr32 = ORRWrs $wzr, %45, 0 - %0:gpr64 = SUBREG_TO_REG 0, killed %48, %subreg.sub_32 + %0:gpr64 = SUBREG_TO_REG killed %48, %subreg.sub_32 dead $wzr = SUBSWri %45, 8, 0, implicit-def $nzcv Bcc 2, %bb.2, implicit $nzcv diff --git a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir index bcc6a3ea9b285..e5b9ed9dae143 100644 --- a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir +++ b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir @@ -81,7 +81,7 @@ body: | bb.1.for.body.preheader: %8:gpr32 = ORRWrs $wzr, %5, 0 - %0:gpr64 = SUBREG_TO_REG 0, killed %8, %subreg.sub_32 + %0:gpr64 = SUBREG_TO_REG killed %8, %subreg.sub_32 %9:gpr64all = COPY $xzr %7:gpr64all = COPY %9 %13:gpr64common = ADRP target-flags(aarch64-page) @x diff --git a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir index 6116f15811ec7..b7bda43a75aa1 100644 --- a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir +++ b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir @@ -71,7 +71,7 @@ body: | bb.1.for.body.preheader: %13:gpr32 = ORRWrs $wzr, %9, 0 - %1:gpr64 = SUBREG_TO_REG 0, killed %13, %subreg.sub_32 + %1:gpr64 = SUBREG_TO_REG killed %13, %subreg.sub_32 %14:gpr64all = COPY $xzr %12:gpr64all = COPY %14 B %bb.3 diff --git a/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir b/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir index 61e3c73a3ee53..5eb174c433b8a 100644 --- a/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir +++ b/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir @@ -237,7 +237,7 @@ body: | %2:gpr64sp = PHI %17, %bb.0, %13, %bb.3 %4:zpr = DUP_ZR_D %2 %22:zpr = COPY %21 - %20:gpr64all = SUBREG_TO_REG 0, %23, %subreg.sub_32 + %20:gpr64all = SUBREG_TO_REG %23, %subreg.sub_32 bb.2.vector.body: successors: %bb.3(0x04000000), %bb.2(0x7c000000) diff --git a/llvm/test/CodeGen/AArch64/sms-regpress.mir b/llvm/test/CodeGen/AArch64/sms-regpress.mir index c75eba5aab888..0e126ccf87cbe 100644 --- a/llvm/test/CodeGen/AArch64/sms-regpress.mir +++ b/llvm/test/CodeGen/AArch64/sms-regpress.mir @@ -102,7 +102,7 @@ body: | %0:fpr64 = LDRDui %10, 0 :: (load (s64) from %ir.a) %1:fpr64 = LDRDui %10, 1 :: (load (s64) from %ir.arrayidx1) %16:gpr32 = ORRWrs $wzr, %12, 0 - %2:gpr64all = SUBREG_TO_REG 0, killed %16, %subreg.sub_32 + %2:gpr64all = SUBREG_TO_REG killed %16, %subreg.sub_32 %15:fpr64 = FMOVD0 B %bb.3 diff --git a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir index 42774732ecbad..8a9ccee3565af 100644 --- a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir +++ b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir @@ -53,7 +53,7 @@ body: | bb.1.for.body.preheader: %11:gpr32 = ORRWrs $wzr, %9, 0 - %0:gpr64all = SUBREG_TO_REG 0, killed %11, %subreg.sub_32 + %0:gpr64all = SUBREG_TO_REG killed %11, %subreg.sub_32 %14:fpr32 = FMOVSi 112 B %bb.3 diff --git a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir index 4f5b85f05e1c2..2b7d78b1d3daf 100644 --- a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir +++ b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir @@ -56,7 +56,7 @@ body: | bb.1.for.body.preheader: %7:gpr32common = SUBWri %5, 1, 0 %9:gpr64all = IMPLICIT_DEF - %8:gpr64 = SUBREG_TO_REG 0, killed %7, %subreg.sub_32 + %8:gpr64 = SUBREG_TO_REG killed %7, %subreg.sub_32 %10:gpr64 = SBFMXri killed %8, 0, 31 %0:gpr64all = COPY %10 %12:fpr32 = FMOVSi 112 diff --git a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir index fb28174a79a4a..769fc21266b09 100644 --- a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir +++ b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir @@ -59,7 +59,7 @@ body: | bb.1.for.body.preheader: %11:gpr32 = ORRWrs $wzr, %9, 0 - %0:gpr64all = SUBREG_TO_REG 0, killed %11, %subreg.sub_32 + %0:gpr64all = SUBREG_TO_REG killed %11, %subreg.sub_32 %14:fpr32 = FMOVSi 0 %15:fpr32 = FMOVSi 112 B %bb.3 diff --git a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir index 290f7027244f2..d40d28e0e47e6 100644 --- a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir +++ b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir @@ -60,7 +60,7 @@ body: | bb.1.for.body.preheader: %7:gpr32common = SUBWri %5, 1, 0 %9:gpr64all = IMPLICIT_DEF - %8:gpr64 = SUBREG_TO_REG 0, killed %7, %subreg.sub_32 + %8:gpr64 = SUBREG_TO_REG killed %7, %subreg.sub_32 %10:gpr64 = SBFMXri killed %8, 0, 31 %0:gpr64all = COPY %10 %12:fpr32 = FMOVSi 112 diff --git a/llvm/test/CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir b/llvm/test/CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir index b8fa4a2fef901..7a94a9b74d54a 100644 --- a/llvm/test/CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir +++ b/llvm/test/CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir @@ -26,7 +26,7 @@ body: | %0:gpr64 = COPY killed $x1 %1:gpr32 = COPY %0.sub_32:gpr64 %2:gpr32 = ORRWrr $wzr, killed %1:gpr32 - %3:gpr64all = SUBREG_TO_REG 0, killed %2:gpr32, %subreg.sub_32 + %3:gpr64all = SUBREG_TO_REG killed %2:gpr32, %subreg.sub_32 $x0 = COPY killed %0:gpr64 $x1 = COPY killed %3:gpr64all RET_ReallyLR implicit $x1, implicit $x0 diff --git a/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir b/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir index 566753b7d4d10..3b72e760c54fb 100644 --- a/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir +++ b/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir @@ -26,7 +26,7 @@ body: | %0:gpr32 = COPY %3.sub_32 ; CHECK: {{.*}}.sub_32:gpr64 = COPY {{.*}}.sub_32 STRBBui %1, %2, target-flags(aarch64-pageoff, aarch64-nc) @c :: (store (s8) into @c, align 4) - %8:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + %8:gpr64all = SUBREG_TO_REG %0, %subreg.sub_32 $x0 = COPY %8 ; CHECK: $x0 = COPY RET_ReallyLR implicit $x0 diff --git a/llvm/test/CodeGen/PowerPC/mi-simplify-code.mir b/llvm/test/CodeGen/PowerPC/mi-simplify-code.mir index 0cfeb944a5dbc..d32fad49b37a5 100644 --- a/llvm/test/CodeGen/PowerPC/mi-simplify-code.mir +++ b/llvm/test/CodeGen/PowerPC/mi-simplify-code.mir @@ -14,10 +14,10 @@ body: | %2:g8rc = RLDICR %1, 2, 61 %3:f8rc, %4:g8rc_and_g8rc_nox0 = LFSUX %0, killed %2 %5:f4rc = FRSP killed %3, implicit $rm - %22:vslrc = SUBREG_TO_REG 1, %5, %subreg.sub_64 + %22:vslrc = SUBREG_TO_REG %5, %subreg.sub_64 %7:g8rc = LI8 8 %8:vssrc = XFLOADf32 %4, killed %7 - %23:vslrc = SUBREG_TO_REG 1, %8, %subreg.sub_64 + %23:vslrc = SUBREG_TO_REG %8, %subreg.sub_64 %10:vsrc = XXPERMDI %23, %22, 0 %11:vrrc = XVCVDPSP killed %10, implicit $rm $v2 = COPY %11 @@ -44,10 +44,10 @@ body: | %2:g8rc = RLDICR %1, 2, 61 %3:f8rc, %4:g8rc_and_g8rc_nox0 = LFSUX %0, killed %2 %5:vssrc = XSRSP killed %3 - %22:vslrc = SUBREG_TO_REG 1, %5, %subreg.sub_64 + %22:vslrc = SUBREG_TO_REG %5, %subreg.sub_64 %7:g8rc = LI8 8 %8:vssrc = XFLOADf32 %4, killed %7 - %23:vslrc = SUBREG_TO_REG 1, %8, %subreg.sub_64 + %23:vslrc = SUBREG_TO_REG %8, %subreg.sub_64 %10:vsrc = XXPERMDI %23, %22, 0 %11:vrrc = XVCVDPSP killed %10, implicit $rm $v2 = COPY %11 diff --git a/llvm/test/CodeGen/PowerPC/subreg-coalescer.mir b/llvm/test/CodeGen/PowerPC/subreg-coalescer.mir index 31407e0d44cfb..df47ff9b3a19d 100644 --- a/llvm/test/CodeGen/PowerPC/subreg-coalescer.mir +++ b/llvm/test/CodeGen/PowerPC/subreg-coalescer.mir @@ -26,7 +26,7 @@ body: | %0:g8rc_and_g8rc_nox0 = COPY $x3 %1:f8rc, %2:g8rc_and_g8rc_nox0 = LFSUX %0, %0 %3:f4rc = FRSP killed %1, implicit $rm - %4:vslrc = SUBREG_TO_REG 1, %3, %subreg.sub_64 + %4:vslrc = SUBREG_TO_REG %3, %subreg.sub_64 %5:vrrc = XVCVDPSP killed %4, implicit $rm $v2 = COPY %5 BLR8 implicit $lr8, implicit $rm, implicit $v2 diff --git a/llvm/test/CodeGen/PowerPC/xxinsertw.ll b/llvm/test/CodeGen/PowerPC/xxinsertw.ll index f944b5a175be4..205e982be05b4 100644 --- a/llvm/test/CodeGen/PowerPC/xxinsertw.ll +++ b/llvm/test/CodeGen/PowerPC/xxinsertw.ll @@ -13,16 +13,16 @@ define <4 x i1> @foo(i1 %c1, i1 %c2, i1 %c3) { ; CHECK-NEXT: [[COPY2:%[0-9]+]]:g8rc = COPY $x3 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY [[COPY1]].sub_32 ; CHECK-NEXT: [[MTVSRWZ:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY3]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:vrrc = SUBREG_TO_REG 1, killed [[MTVSRWZ]], %subreg.sub_64 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:vrrc = SUBREG_TO_REG killed [[MTVSRWZ]], %subreg.sub_64 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY2]].sub_32 ; CHECK-NEXT: [[MTVSRWZ1:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY4]] - ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:vrrc = SUBREG_TO_REG 1, killed [[MTVSRWZ1]], %subreg.sub_64 + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:vrrc = SUBREG_TO_REG killed [[MTVSRWZ1]], %subreg.sub_64 ; CHECK-NEXT: [[VMRGOW:%[0-9]+]]:vrrc = VMRGOW killed [[SUBREG_TO_REG1]], killed [[SUBREG_TO_REG]] ; CHECK-NEXT: [[LDtocCPT:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocCPT %const.0, $x2 :: (load (s64) from got) ; CHECK-NEXT: [[LXV:%[0-9]+]]:vsrc = LXV 0, killed [[LDtocCPT]] :: (load (s128) from constant-pool) ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32 ; CHECK-NEXT: [[MTVSRWZ2:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY5]] - ; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:vsrc = SUBREG_TO_REG 1, killed [[MTVSRWZ2]], %subreg.sub_64 + ; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:vsrc = SUBREG_TO_REG killed [[MTVSRWZ2]], %subreg.sub_64 ; CHECK-NEXT: [[XXPERM:%[0-9]+]]:vsrc = XXPERM killed [[VMRGOW]], [[SUBREG_TO_REG2]], killed [[LXV]] ; CHECK-NEXT: [[XXINSERTW:%[0-9]+]]:vsrc = XXINSERTW [[XXPERM]], [[XXPERM]], 8 ; CHECK-NEXT: $v2 = COPY [[XXINSERTW]] diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir index 60171e5bee1f6..d204e09dd9ef1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir @@ -112,7 +112,7 @@ body: | ; ALL-LABEL: name: anyext_s64_from_s1 ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit ; ALL: $rax = COPY [[SUBREG_TO_REG]] ; ALL: RET 0, implicit $rax %0(s64) = COPY $rdi @@ -138,7 +138,7 @@ body: | ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit ; ALL: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]] - ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOVZX32rr8_]], %subreg.sub_32bit + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOVZX32rr8_]], %subreg.sub_32bit ; ALL: $rax = COPY [[SUBREG_TO_REG]] ; ALL: RET 0, implicit $rax %0(s64) = COPY $rdi @@ -164,7 +164,7 @@ body: | ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit ; ALL: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]] - ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOVZX32rr16_]], %subreg.sub_32bit + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOVZX32rr16_]], %subreg.sub_32bit ; ALL: $rax = COPY [[SUBREG_TO_REG]] ; ALL: RET 0, implicit $rax %0(s64) = COPY $rdi diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir index 44daf22b00a3c..0805a486a76a8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir @@ -316,13 +316,13 @@ body: | ; X86-LABEL: name: test_anyext_i1toi16 ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; X86-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr16 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit + ; X86-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr16 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit ; X86-NEXT: $ax = COPY [[SUBREG_TO_REG]] ; X86-NEXT: RET 0, implicit $ax ; X64-LABEL: name: test_anyext_i1toi16 ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; X64-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr16 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit + ; X64-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr16 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit ; X64-NEXT: $ax = COPY [[SUBREG_TO_REG]] ; X64-NEXT: RET 0, implicit $ax %0(s32) = COPY $edi @@ -348,13 +348,13 @@ body: | ; X86-LABEL: name: test_anyext_i1toi32 ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; X86-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit + ; X86-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit ; X86-NEXT: $eax = COPY [[SUBREG_TO_REG]] ; X86-NEXT: RET 0, implicit $eax ; X64-LABEL: name: test_anyext_i1toi32 ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; X64-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit + ; X64-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit ; X64-NEXT: $eax = COPY [[SUBREG_TO_REG]] ; X64-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir index 2657482cd9e3c..a685b417a9b52 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir @@ -364,7 +364,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; CHECK-NEXT: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOV32rr]], %subreg.sub_32bit ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET 0, implicit $rax %0:gpr(s32) = COPY $edi diff --git a/llvm/test/CodeGen/X86/apx/foldimmediate.mir b/llvm/test/CodeGen/X86/apx/foldimmediate.mir index 310fc64841f7a..ffe544d2a1a00 100644 --- a/llvm/test/CodeGen/X86/apx/foldimmediate.mir +++ b/llvm/test/CodeGen/X86/apx/foldimmediate.mir @@ -40,7 +40,7 @@ body: | ; CHECK-NEXT: NOOP implicit $eflags ; CHECK-NEXT: CCMP32ri [[COPY]], 81, 2, 10, implicit-def $eflags, implicit $eflags ; CHECK-NEXT: NOOP implicit $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32ri]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32ri]], %subreg.sub_32bit ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi ; CHECK-NEXT: CTEST64ri32 [[COPY1]], 81, 2, 10, implicit-def $eflags, implicit $eflags ; CHECK-NEXT: NOOP implicit $eflags @@ -57,7 +57,7 @@ body: | CCMP32rr %1, %0, 2, 10, implicit-def $eflags, implicit $eflags NOOP implicit $eflags - %7 = SUBREG_TO_REG 0, killed %0:gr32, %subreg.sub_32bit + %7 = SUBREG_TO_REG killed %0:gr32, %subreg.sub_32bit %8 = COPY $rsi CTEST64rr %8, %7, 2, 10, implicit-def $eflags, implicit $eflags diff --git a/llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir b/llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir index eec92f059082f..a56237e160c31 100644 --- a/llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir +++ b/llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir @@ -35,7 +35,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY killed $edi ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY killed [[COPY]].sub_8bit ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32r0_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32r0_]], %subreg.sub_32bit ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY killed [[SUBREG_TO_REG]] ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1.loop (inlineasm-br-indirect-target): @@ -65,7 +65,7 @@ body: | %2:gr32 = COPY killed $edi %3:gr8 = COPY killed %2.sub_8bit %5:gr32 = MOV32r0 implicit-def dead $eflags - %4:gr64 = SUBREG_TO_REG 0, killed %5, %subreg.sub_32bit + %4:gr64 = SUBREG_TO_REG killed %5, %subreg.sub_32bit bb.1.loop (inlineasm-br-indirect-target): successors: %bb.2(0x40000000), %bb.1(0x40000000) diff --git a/llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll b/llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll index 433bd254317e6..77f4138788197 100644 --- a/llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll +++ b/llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll @@ -341,7 +341,7 @@ define i64 @condition_code() { ; CHECK-NEXT: INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %1, 13 /* imm */, %bb.2 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOVZX32rr8_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOVZX32rr8_]], %subreg.sub_32bit ; CHECK-NEXT: JMP_1 %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1.b: @@ -351,7 +351,7 @@ define i64 @condition_code() { ; CHECK-NEXT: bb.2.c (inlineasm-br-indirect-target): ; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags ; CHECK-NEXT: [[MOVZX32rr8_1:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr1]] - ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOVZX32rr8_1]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOVZX32rr8_1]], %subreg.sub_32bit ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG1]] ; CHECK-NEXT: RET 0, $rax %a = callbr i64 asm "", "={@ccz},!i"() diff --git a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir index 8241a1757af52..a5f1f3d6d6268 100644 --- a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir +++ b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir @@ -40,7 +40,7 @@ body: | %0:gr32 = MOV32r0 implicit-def dead $eflags %1:gr8 = COPY %0.sub_8bit - %2:gr64 = SUBREG_TO_REG 0, killed %0, %subreg.sub_32bit + %2:gr64 = SUBREG_TO_REG killed %0, %subreg.sub_32bit JCC_1 %bb.2, 5, implicit killed undef $eflags bb.1: diff --git a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.mir b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.mir index 722d9b60841a2..e49a449926124 100644 --- a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.mir +++ b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.mir @@ -11,7 +11,7 @@ body: | %0:gr32 = MOV32r0 implicit-def dead $eflags %1:gr8 = COPY %0.sub_8bit - %2:gr64 = SUBREG_TO_REG 0, killed %0, %subreg.sub_32bit + %2:gr64 = SUBREG_TO_REG killed %0, %subreg.sub_32bit JCC_1 %bb.2, 5, implicit killed undef $eflags bb.1: diff --git a/llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir b/llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir index ffc3fd6ce0d89..d3db88a6c29f4 100644 --- a/llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir +++ b/llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir @@ -7,5 +7,5 @@ body: | liveins: $eax ; CHECK-NOT: dead $rax = KILL {{[0-9]+}} ; CHECK: dead $rax = KILL killed $eax - dead $rax = SUBREG_TO_REG 0, killed $eax, %subreg.sub_32bit + dead $rax = SUBREG_TO_REG killed $eax, %subreg.sub_32bit ... diff --git a/llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir b/llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir index 37a90a2f16d67..b26dd5a959967 100644 --- a/llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir +++ b/llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir @@ -188,7 +188,7 @@ body: | %0:gr32 = COPY $edi %1:gr32 = MOV32rm %stack.0.a.addr, 1, $noreg, 0, $noreg, debug-location !13 :: (dereferenceable load (s32) from %ir.a.addr) - %2:gr64_nosp = SUBREG_TO_REG 0, killed %1, %subreg.sub_32bit, debug-location !13 + %2:gr64_nosp = SUBREG_TO_REG killed %1, %subreg.sub_32bit, debug-location !13 ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !14 %3:gr64 = COPY $rsp, debug-location !14 $rsp = COPY %3, debug-location !14 diff --git a/llvm/test/CodeGen/X86/foldimmediate.mir b/llvm/test/CodeGen/X86/foldimmediate.mir index 5fd5ae9c1ca9f..82f99655264de 100644 --- a/llvm/test/CodeGen/X86/foldimmediate.mir +++ b/llvm/test/CodeGen/X86/foldimmediate.mir @@ -54,7 +54,7 @@ body: | ; CHECK-NEXT: NOOP implicit [[ADC32ri]] ; CHECK-NEXT: [[SBB32ri:%[0-9]+]]:gr32 = SBB32ri [[COPY]], 81, implicit-def $eflags, implicit $eflags ; CHECK-NEXT: NOOP implicit [[SBB32ri]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32ri]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32ri]], %subreg.sub_32bit ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi ; CHECK-NEXT: [[ADD64ri32_:%[0-9]+]]:gr64 = ADD64ri32 [[COPY1]], 81, implicit-def $eflags ; CHECK-NEXT: NOOP implicit [[ADD64ri32_]] @@ -107,7 +107,7 @@ body: | %18 = SBB32rr %1, %0, implicit-def $eflags, implicit $eflags NOOP implicit %18 - %7 = SUBREG_TO_REG 0, killed %0:gr32, %subreg.sub_32bit + %7 = SUBREG_TO_REG killed %0:gr32, %subreg.sub_32bit %8 = COPY $rsi %9 = ADD64rr %7, %8, implicit-def $eflags NOOP implicit %9 diff --git a/llvm/test/CodeGen/X86/opt_phis2.mir b/llvm/test/CodeGen/X86/opt_phis2.mir index 421a986d2601b..dedeb741e053c 100644 --- a/llvm/test/CodeGen/X86/opt_phis2.mir +++ b/llvm/test/CodeGen/X86/opt_phis2.mir @@ -29,7 +29,7 @@ body: | %13:gr32 = ADD32rr %7, killed %12, implicit-def dead $eflags %14:gr32 = AND32ri8 %13, -4, implicit-def dead $eflags %15:gr32 = SUB32rr %7, %14, implicit-def dead $eflags - %10:gr64_nosp = SUBREG_TO_REG 0, %15, %subreg.sub_32bit + %10:gr64_nosp = SUBREG_TO_REG %15, %subreg.sub_32bit %16:gr32 = SUB32ri8 %15, 3, implicit-def $eflags JCC_1 %bb.8, 7, implicit $eflags diff --git a/llvm/test/CodeGen/X86/peephole-test-after-add.mir b/llvm/test/CodeGen/X86/peephole-test-after-add.mir index 675c8f4720bc9..0490bf8e508b6 100644 --- a/llvm/test/CodeGen/X86/peephole-test-after-add.mir +++ b/llvm/test/CodeGen/X86/peephole-test-after-add.mir @@ -116,7 +116,7 @@ body: | ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.0) ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[MOV64rm]].sub_32bit ; CHECK-NEXT: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY2]], 3, implicit-def $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[AND32ri8_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[AND32ri8_]], %subreg.sub_32bit ; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[SUBREG_TO_REG]], [[COPY]], 4, implicit $eflags ; CHECK-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, killed [[CMOV64rr]] :: (store (s64) into %ir.0) ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]] @@ -126,7 +126,7 @@ body: | %3:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.0) %4:gr32 = COPY %3.sub_32bit %5:gr32 = AND32ri8 %4, 3, implicit-def dead $eflags - %6:gr64 = SUBREG_TO_REG 0, killed %5, %subreg.sub_32bit + %6:gr64 = SUBREG_TO_REG killed %5, %subreg.sub_32bit TEST64rr %6, %6, implicit-def $eflags %7:gr64 = CMOV64rr %6, %1, 4, implicit $eflags MOV64mr %0, 1, $noreg, 0, $noreg, killed %7 :: (store (s64) into %ir.0) @@ -164,7 +164,7 @@ body: | ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.0) ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[MOV64rm]].sub_32bit ; CHECK-NEXT: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY2]], 3, implicit-def dead $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[AND32ri8_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[AND32ri8_]], %subreg.sub_32bit ; CHECK-NEXT: TEST64rr [[SUBREG_TO_REG]], [[SUBREG_TO_REG]], implicit-def $eflags ; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[SUBREG_TO_REG]], [[COPY]], 8, implicit $eflags ; CHECK-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, killed [[CMOV64rr]] :: (store (s64) into %ir.0) @@ -175,7 +175,7 @@ body: | %4:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.0) %5:gr32 = COPY %4.sub_32bit %6:gr32 = AND32ri8 %5, 3, implicit-def dead $eflags - %7:gr64 = SUBREG_TO_REG 0, killed %6, %subreg.sub_32bit + %7:gr64 = SUBREG_TO_REG killed %6, %subreg.sub_32bit TEST64rr %7, %7, implicit-def $eflags %8:gr64 = CMOV64rr %7, %1, 8, implicit $eflags MOV64mr %0, 1, $noreg, 0, $noreg, killed %8 :: (store (s64) into %ir.0) @@ -219,7 +219,7 @@ body: | ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY3]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.0) ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr32 = COPY [[MOV64rm]].sub_32bit ; CHECK-NEXT: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY4]], 3, implicit-def dead $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[AND32ri8_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[AND32ri8_]], %subreg.sub_32bit ; CHECK-NEXT: [[XOR64ri8_:%[0-9]+]]:gr64 = XOR64ri8 [[COPY1]], 5, implicit-def dead $eflags ; CHECK-NEXT: TEST64rr [[SUBREG_TO_REG]], [[SUBREG_TO_REG]], implicit-def $eflags ; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[SUBREG_TO_REG]], [[COPY2]], 4, implicit $eflags @@ -233,7 +233,7 @@ body: | %5:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.0) %6:gr32 = COPY %5.sub_32bit %7:gr32 = AND32ri8 %6, 3, implicit-def dead $eflags - %8:gr64 = SUBREG_TO_REG 0, killed %7, %subreg.sub_32bit + %8:gr64 = SUBREG_TO_REG killed %7, %subreg.sub_32bit %9:gr64 = XOR64ri8 %3, 5, implicit-def dead $eflags TEST64rr %8, %8, implicit-def $eflags %10:gr64 = CMOV64rr %8, %1, 4, implicit $eflags diff --git a/llvm/test/CodeGen/X86/peephole.mir b/llvm/test/CodeGen/X86/peephole.mir index 23b4062c3e039..efcb1582e19cc 100644 --- a/llvm/test/CodeGen/X86/peephole.mir +++ b/llvm/test/CodeGen/X86/peephole.mir @@ -30,11 +30,11 @@ body: | ; CHECK: %4:fr32 = VMOVDI2SSrr %3 ; CHECK-NOT: COPY ; CHECK: %5:gr32 = MOVSS2DIrr %4 - ; CHECK: %6:gr64 = SUBREG_TO_REG 0, %5, %subreg.sub_32bit + ; CHECK: %6:gr64 = SUBREG_TO_REG %5, %subreg.sub_32bit ; CHECK: NOOP implicit %6 %3 = MOV32ri 42 %4 = VMOVDI2SSrr %3 %5 = MOVSS2DIrr %4 - %6 = SUBREG_TO_REG 0, %5, %subreg.sub_32bit + %6 = SUBREG_TO_REG %5, %subreg.sub_32bit NOOP implicit %6 ... diff --git a/llvm/test/CodeGen/X86/pr57673.ll b/llvm/test/CodeGen/X86/pr57673.ll index 24862539ca637..4cb8450e85c25 100644 --- a/llvm/test/CodeGen/X86/pr57673.ll +++ b/llvm/test/CodeGen/X86/pr57673.ll @@ -46,7 +46,7 @@ define void @foo() { ; NORMAL-NEXT: successors: %bb.1(0x80000000) ; NORMAL-NEXT: {{ $}} ; NORMAL-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp - ; NORMAL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32r0_1]], %subreg.sub_32bit + ; NORMAL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOV32r0_1]], %subreg.sub_32bit ; NORMAL-NEXT: $rdi = COPY [[SUBREG_TO_REG]] ; NORMAL-NEXT: $rsi = COPY [[SUBREG_TO_REG]] ; NORMAL-NEXT: $rdx = COPY [[SUBREG_TO_REG]] @@ -86,7 +86,7 @@ define void @foo() { ; INSTRREF-NEXT: successors: %bb.1(0x80000000) ; INSTRREF-NEXT: {{ $}} ; INSTRREF-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp - ; INSTRREF-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32r0_1]], %subreg.sub_32bit + ; INSTRREF-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOV32r0_1]], %subreg.sub_32bit ; INSTRREF-NEXT: $rdi = COPY [[SUBREG_TO_REG]] ; INSTRREF-NEXT: $rsi = COPY [[SUBREG_TO_REG]] ; INSTRREF-NEXT: $rdx = COPY [[SUBREG_TO_REG]] diff --git a/llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir b/llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir index 143b6864b1191..1325af8a46b3b 100644 --- a/llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir +++ b/llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir @@ -24,14 +24,14 @@ body: | ; CHECK: successors: %bb.3(0x80000000) ; CHECK: $rcx = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %stack.1) ; CHECK: renamable $eax = MOV32r0 implicit-def dead $eflags - ; CHECK: renamable $rax = SUBREG_TO_REG 0, killed renamable $eax, %subreg.sub_32bit + ; CHECK: renamable $rax = SUBREG_TO_REG killed renamable $eax, %subreg.sub_32bit ; CHECK: MOV64mi32 killed renamable $rcx, 1, $noreg, 0, $noreg, 0 :: (volatile store (s64)) ; CHECK: MOV64mr %stack.0, 1, $noreg, 0, $noreg, killed $rax :: (store (s64) into %stack.0) ; CHECK: bb.3: ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: $rax = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %stack.0) ; CHECK: renamable $ecx = MOV32r0 implicit-def dead $eflags - ; CHECK: renamable $rcx = SUBREG_TO_REG 0, killed renamable $ecx, %subreg.sub_32bit + ; CHECK: renamable $rcx = SUBREG_TO_REG killed renamable $ecx, %subreg.sub_32bit ; CHECK: MOV64mr %stack.1, 1, $noreg, 0, $noreg, killed $rcx :: (store (s64) into %stack.1) ; CHECK: JMP64r killed renamable $rax bb.0: @@ -50,7 +50,7 @@ body: | bb.2: %0:gr64 = COPY %12 %10:gr32 = MOV32r0 implicit-def $eflags - %11:gr64 = SUBREG_TO_REG 0, %10, %subreg.sub_32bit + %11:gr64 = SUBREG_TO_REG %10, %subreg.sub_32bit MOV64mi32 %0, 1, $noreg, 0, $noreg, 0 :: (volatile store (s64)) %13:gr64 = COPY %11 @@ -59,7 +59,7 @@ body: | %1:gr64 = COPY %13 %9:gr32 = MOV32r0 implicit-def dead $eflags - %8:gr64 = SUBREG_TO_REG 0, killed %9, %subreg.sub_32bit + %8:gr64 = SUBREG_TO_REG killed %9, %subreg.sub_32bit %12:gr64 = COPY %8 JMP64r %1 diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir index 0c5c3669268c0..62f7ee096a3ff 100644 --- a/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir +++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir @@ -285,7 +285,7 @@ body: | ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp %22:gr32 = MOV32r0 implicit-def dead $eflags - %21:gr64 = SUBREG_TO_REG 0, %22, %subreg.sub_32bit + %21:gr64 = SUBREG_TO_REG %22, %subreg.sub_32bit $rdi = COPY %21 STATEPOINT 2, 5, 2, undef %24:gr64, killed $rdi, undef $rsi, 2, 0, 2, 0, 2, 37, 2, 0, 2, 2, 2, 0, 2, 43, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 10, 2, 1, 2, 6, 2, 0, 2, 4, 2, 1, 2, 0, 2, 0, 2, 7, 2, 0, 2, 0, 2, 0, 2, 7, 2, 0, 2, 0, 2, 0, 2, 2, 2, 4, 2, 5, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 1, 2, 0, 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir index 5ce76a3e46f66..ae0a1e03e78e3 100644 --- a/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir +++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir @@ -235,7 +235,7 @@ body: | EH_LABEL ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp %20:gr32 = MOV32r0 implicit-def dead $eflags - %21:gr64 = SUBREG_TO_REG 0, %20, %subreg.sub_32bit + %21:gr64 = SUBREG_TO_REG %20, %subreg.sub_32bit $edi = COPY %20 $rsi = COPY killed %21 $ecx = COPY %7 diff --git a/llvm/test/CodeGen/X86/statepoint-vreg-details.ll b/llvm/test/CodeGen/X86/statepoint-vreg-details.ll index a33993444d023..2a0710e3249a6 100644 --- a/llvm/test/CodeGen/X86/statepoint-vreg-details.ll +++ b/llvm/test/CodeGen/X86/statepoint-vreg-details.ll @@ -50,7 +50,7 @@ define void @test_mixed(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace( ; CHECK-VREG: %0:gr64 = COPY $rdi ; CHECK-VREG: %3:gr64, %4:gr64, %5:gr64 = STATEPOINT 0, 0, 0, @func, 2, 0, 2, 0, 2, 0, 2, 4, %2(tied-def 0), 2, 0, %1(tied-def 1), %0(tied-def 2), 2, 0, 2, 4, 0, 0, 1, 1, 2, 2, 3, 3, csr_64, implicit-def $rsp, implicit-def $ssp ; CHECK-VREG: %6:gr32 = MOV32r0 implicit-def dead $eflags -; CHECK-VREG: %7:gr64 = SUBREG_TO_REG 0, killed %6, %subreg.sub_32bit +; CHECK-VREG: %7:gr64 = SUBREG_TO_REG killed %6, %subreg.sub_32bit ; CHECK-VREG: $rdi = COPY %5 ; CHECK-VREG: $rsi = COPY %7 ; CHECK-VREG: $rdx = COPY %4 @@ -361,7 +361,7 @@ define ptr addrspace(1) @test_isel_sched(ptr addrspace(1) %0, ptr addrspace(1) % ;CHECK-VREG: TEST32rr %2, %2, implicit-def $eflags ;CHECK-VREG: %3:gr64 = CMOV64rr %1, %0, 4, implicit $eflags ;CHECK-VREG: %4:gr32 = MOV32r0 implicit-def dead $eflags -;CHECK-VREG: %5:gr64 = SUBREG_TO_REG 0, killed %4, %subreg.sub_32bit +;CHECK-VREG: %5:gr64 = SUBREG_TO_REG killed %4, %subreg.sub_32bit ;CHECK-VREG: $rdi = COPY %5 ;CHECK-VREG: $rsi = COPY %3 ;CHECK-VREG: %6:gr64, %7:gr64 = STATEPOINT 10, 0, 2, @bar, $rdi, $rsi, 2, 0, 2, 0, 2, 0, 2, 2, %1(tied-def 0), %0(tied-def 1), 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp diff --git a/llvm/test/CodeGen/X86/subreg-fail.mir b/llvm/test/CodeGen/X86/subreg-fail.mir index c8146f099b814..888afa8aa4915 100644 --- a/llvm/test/CodeGen/X86/subreg-fail.mir +++ b/llvm/test/CodeGen/X86/subreg-fail.mir @@ -22,9 +22,9 @@ body: | ; CHECK-NEXT: MOV32mr undef %10:gr64, 1, $noreg, 0, $noreg, [[LEA64r]].sub_32bit :: (volatile store (s32) into `ptr undef`) ; CHECK-NEXT: RET 0, undef $eax %0:gr32 = MOV32rm undef %1:gr64, 1, $noreg, 0, $noreg :: (volatile load (s32) from `ptr undef`) - %2:gr64_nosp = SUBREG_TO_REG 0, killed %0, %subreg.sub_32bit + %2:gr64_nosp = SUBREG_TO_REG killed %0, %subreg.sub_32bit %3:gr32 = MOV32rm undef %4:gr64, 1, $noreg, 0, $noreg :: (volatile load (s32) from `ptr undef`) - %5:gr64 = SUBREG_TO_REG 0, killed %3, %subreg.sub_32bit + %5:gr64 = SUBREG_TO_REG killed %3, %subreg.sub_32bit %6:gr64 = COPY killed %5 %6:gr64 = SHL64ri %6, 32, implicit-def dead $eflags %7:gr64 = LEA64r killed %6, 1, killed %2, 256, $noreg diff --git a/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll b/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll index 7ce983869ce7d..acfa5d59fcb2f 100644 --- a/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll +++ b/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll @@ -96,7 +96,7 @@ define void @ceph_con_v2_try_read(i32 %__trans_tmp_3.sroa.0.0.copyload, i1 %tobo ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32r0_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32r0_]], %subreg.sub_32bit ; CHECK-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r %stack.0.skip.i.i, 1, $noreg, 0, $noreg ; CHECK-NEXT: $rdi = COPY [[LEA64r]] ; CHECK-NEXT: CALL64r killed [[SUBREG_TO_REG]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax diff --git a/llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir b/llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir index 2f1ff76fda76c..e90d56e2d2793 100644 --- a/llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir +++ b/llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir @@ -22,7 +22,7 @@ body: | ; LIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; LIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, killed [[AND32ri]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG killed [[AND32ri]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.2: @@ -61,7 +61,7 @@ body: | ; LIMIT-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[SHR32ri3]], %bb.5, [[SHR32ri2]], %bb.4, [[SHR32ri1]], %bb.3, [[MOV32rm]], %bb.2 ; LIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri4]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, killed [[AND32ri1]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG killed [[AND32ri1]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.9: @@ -105,7 +105,7 @@ body: | ; NOLIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; NOLIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, killed [[AND32ri]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG killed [[AND32ri]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.2: @@ -114,7 +114,7 @@ body: | ; NOLIMIT-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg ; NOLIMIT-NEXT: [[SHR32ri1:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri1]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri1]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri1]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.3: @@ -124,7 +124,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri2:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm1]], 1, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri3:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri2:%[0-9]+]]:gr32 = AND32ri [[SHR32ri3]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri2]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri2]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG2]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.4: @@ -134,7 +134,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm2]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri5:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri3:%[0-9]+]]:gr32 = AND32ri [[SHR32ri5]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri3]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri3]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG3]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.5: @@ -144,7 +144,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri6:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm3]], 3, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri7:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri4:%[0-9]+]]:gr32 = AND32ri [[SHR32ri7]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri4]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri4]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG4]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.6: @@ -193,7 +193,7 @@ body: | %10:gr64 = COPY $rdi %13:gr32 = SHR32ri %11, 1, implicit-def dead $eflags %14:gr32 = AND32ri %13, 7, implicit-def dead $eflags - %12:gr64_nosp = SUBREG_TO_REG 0, killed %14, %subreg.sub_32bit + %12:gr64_nosp = SUBREG_TO_REG killed %14, %subreg.sub_32bit bb.1: successors: %bb.2, %bb.3, %bb.4, %bb.5 @@ -226,7 +226,7 @@ body: | %4:gr32 = PHI %3, %bb.5, %2, %bb.4, %1, %bb.3, %0, %bb.2 %19:gr32 = SHR32ri %11, 2, implicit-def dead $eflags %20:gr32 = AND32ri %19, 7, implicit-def dead $eflags - %18:gr64_nosp = SUBREG_TO_REG 0, killed %20, %subreg.sub_32bit + %18:gr64_nosp = SUBREG_TO_REG killed %20, %subreg.sub_32bit bb.8: successors: %bb.9, %bb.10, %bb.11, %bb.12 @@ -279,7 +279,7 @@ body: | ; LIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; LIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.2: @@ -317,7 +317,7 @@ body: | ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri4]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri1]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri1]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.9: @@ -362,7 +362,7 @@ body: | ; NOLIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; NOLIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.2: @@ -371,7 +371,7 @@ body: | ; NOLIMIT-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg ; NOLIMIT-NEXT: [[SHR32ri1:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri1]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri1]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri1]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.3: @@ -381,7 +381,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri2:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm1]], 1, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri3:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri2:%[0-9]+]]:gr32 = AND32ri [[SHR32ri3]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri2]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri2]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG2]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.4: @@ -391,7 +391,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm2]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri5:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri3:%[0-9]+]]:gr32 = AND32ri [[SHR32ri5]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri3]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri3]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG3]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.5: @@ -401,7 +401,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri6:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm3]], 3, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri7:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri4:%[0-9]+]]:gr32 = AND32ri [[SHR32ri7]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri4]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri4]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG4]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.6: @@ -446,7 +446,7 @@ body: | %10:gr64 = COPY $rdi %13:gr32 = SHR32ri %11, 1, implicit-def dead $eflags %14:gr32 = AND32ri %13, 7, implicit-def dead $eflags - %12:gr64_nosp = SUBREG_TO_REG 0, %14, %subreg.sub_32bit + %12:gr64_nosp = SUBREG_TO_REG %14, %subreg.sub_32bit bb.1: successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.9 @@ -478,7 +478,7 @@ body: | bb.7: %19:gr32 = SHR32ri %11, 2, implicit-def dead $eflags %20:gr32 = AND32ri %19, 7, implicit-def dead $eflags - %18:gr64_nosp = SUBREG_TO_REG 0, %20, %subreg.sub_32bit + %18:gr64_nosp = SUBREG_TO_REG %20, %subreg.sub_32bit bb.8: successors: %bb.9, %bb.10, %bb.11, %bb.12 @@ -534,7 +534,7 @@ body: | ; LIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; LIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, killed [[AND32ri]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG killed [[AND32ri]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.2: @@ -543,7 +543,7 @@ body: | ; LIMIT-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg ; LIMIT-NEXT: [[SHR32ri1:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri1]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri1]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri1]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.3: @@ -553,7 +553,7 @@ body: | ; LIMIT-NEXT: [[SHR32ri2:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm1]], 1, implicit-def dead $eflags ; LIMIT-NEXT: [[SHR32ri3:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri2:%[0-9]+]]:gr32 = AND32ri [[SHR32ri3]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri2]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri2]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG2]], %jump-table.1, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.4: @@ -563,7 +563,7 @@ body: | ; LIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm2]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[SHR32ri5:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri3:%[0-9]+]]:gr32 = AND32ri [[SHR32ri5]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri3]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri3]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG3]], %jump-table.1, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.5: @@ -573,7 +573,7 @@ body: | ; LIMIT-NEXT: [[SHR32ri6:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm3]], 3, implicit-def dead $eflags ; LIMIT-NEXT: [[SHR32ri7:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri4:%[0-9]+]]:gr32 = AND32ri [[SHR32ri7]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri4]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri4]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG4]], %jump-table.1, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.6: @@ -615,7 +615,7 @@ body: | ; NOLIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; NOLIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, killed [[AND32ri]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG killed [[AND32ri]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.2: @@ -624,7 +624,7 @@ body: | ; NOLIMIT-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg ; NOLIMIT-NEXT: [[SHR32ri1:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri1]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri1]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri1]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.3: @@ -634,7 +634,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri2:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm1]], 1, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri3:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri2:%[0-9]+]]:gr32 = AND32ri [[SHR32ri3]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri2]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri2]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG2]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.4: @@ -644,7 +644,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm2]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri5:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri3:%[0-9]+]]:gr32 = AND32ri [[SHR32ri5]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri3]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri3]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG3]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.5: @@ -654,7 +654,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri6:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm3]], 3, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri7:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri4:%[0-9]+]]:gr32 = AND32ri [[SHR32ri7]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri4]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri4]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG4]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.6: @@ -693,7 +693,7 @@ body: | %10:gr64 = COPY $rdi %13:gr32 = SHR32ri %11, 1, implicit-def dead $eflags %14:gr32 = AND32ri %13, 7, implicit-def dead $eflags - %12:gr64_nosp = SUBREG_TO_REG 0, killed %14, %subreg.sub_32bit + %12:gr64_nosp = SUBREG_TO_REG killed %14, %subreg.sub_32bit bb.1: successors: %bb.2, %bb.3, %bb.4, %bb.5 @@ -725,7 +725,7 @@ body: | bb.7: %19:gr32 = SHR32ri %11, 2, implicit-def dead $eflags %20:gr32 = AND32ri %19, 7, implicit-def dead $eflags - %18:gr64_nosp = SUBREG_TO_REG 0, killed %20, %subreg.sub_32bit + %18:gr64_nosp = SUBREG_TO_REG killed %20, %subreg.sub_32bit bb.8: successors: %bb.9, %bb.10, %bb.11, %bb.12 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir index e80ed2e3e8eb3..ca5dede206cd7 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir @@ -194,7 +194,7 @@ body: | JMP_1 %bb.11, debug-location !9 bb.11: - %36:gr64 = SUBREG_TO_REG 0, %27, %subreg.sub_32bit + %36:gr64 = SUBREG_TO_REG %27, %subreg.sub_32bit JMP_1 %bb.13, debug-location !9 bb.12: @@ -247,7 +247,7 @@ body: | bb.20: %43:gr32 = nsw DEC32r %5, implicit-def dead $eflags, debug-location !9 - %44:gr64_nosp = SUBREG_TO_REG 0, killed %43, %subreg.sub_32bit + %44:gr64_nosp = SUBREG_TO_REG killed %43, %subreg.sub_32bit ; Fiddled with to morph into llvm test, %8:gr64 = LEA64r $noreg, 4, killed %44, @amd64_push_arguments, $noreg, debug-location !9 %42:gr32 = MOV32ri 8 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-cmov-converter.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-cmov-converter.mir index 684b6207e4891..59270c6ef30d3 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/x86-cmov-converter.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-cmov-converter.mir @@ -127,7 +127,7 @@ body: | successors: %bb.3(0x80000000) %10:gr32 = MOV32rr %5, debug-location !13 - %0:gr64 = SUBREG_TO_REG 0, killed %10, %subreg.sub_32bit, debug-location !13 + %0:gr64 = SUBREG_TO_REG killed %10, %subreg.sub_32bit, debug-location !13 JMP_1 %bb.3 bb.2.for.cond.cleanup: diff --git a/llvm/test/DebugInfo/MIR/X86/machine-cse.mir b/llvm/test/DebugInfo/MIR/X86/machine-cse.mir index 63dc44fb705fe..19dcddd1d4fee 100644 --- a/llvm/test/DebugInfo/MIR/X86/machine-cse.mir +++ b/llvm/test/DebugInfo/MIR/X86/machine-cse.mir @@ -107,7 +107,7 @@ body: | %2:gr32 = COPY $edi %3:gr32 = MOV32rr %2 - %0:gr64 = SUBREG_TO_REG 0, killed %3, %subreg.sub_32bit + %0:gr64 = SUBREG_TO_REG killed %3, %subreg.sub_32bit %4:gr64_nosp = SHL64ri %0, 9, implicit-def dead $eflags %1:gr64 = LEA64r %4, 4, %4, 0, $noreg %5:gr32 = MOV32r0 implicit-def dead $eflags @@ -171,7 +171,7 @@ body: | %2:gr32 = COPY $edi %3:gr32 = MOV32rr %2 - %0:gr64 = SUBREG_TO_REG 0, killed %3, %subreg.sub_32bit + %0:gr64 = SUBREG_TO_REG killed %3, %subreg.sub_32bit %4:gr64_nosp = SHL64ri %0, 9, implicit-def dead $eflags %1:gr64 = LEA64r %4, 4, %4, 0, $noreg %5:gr32 = MOV32r0 implicit-def dead $eflags diff --git a/llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll b/llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll index cae8a479a5ad9..1a49b03d1af9a 100644 --- a/llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll +++ b/llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll @@ -30,7 +30,7 @@ define i64 @test_constant(ptr %rdata) { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2.land.lhs.true.i: ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32r0_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32r0_]], %subreg.sub_32bit ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET 0, $rax entry: @@ -67,7 +67,7 @@ define i64 @test_non_constant(ptr %rdata, i64 %i.194) { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2.land.lhs.true.i: ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32r0_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32r0_]], %subreg.sub_32bit ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET 0, $rax entry: diff --git a/llvm/test/TableGen/GlobalISelEmitter/Subreg.td b/llvm/test/TableGen/GlobalISelEmitter/Subreg.td index 4427c0d4bc663..777fabb8fdefb 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/Subreg.td +++ b/llvm/test/TableGen/GlobalISelEmitter/Subreg.td @@ -234,8 +234,8 @@ def : Pat<(i16 (trunc DOP:$src)), // Test that we can import SUBREG_TO_REG def : Pat<(i32 (zext SOP:$src)), - (SUBREG_TO_REG (i64 0), (SUBSOME_INSN SOP:$src), sub0)>; -// CHECK-LABEL: (zext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (SUBREG_TO_REG:{ *:[i32] } 0:{ *:[i64] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }) + (SUBREG_TO_REG (SUBSOME_INSN SOP:$src), sub0)>; +// CHECK-LABEL: (zext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (SUBREG_TO_REG:{ *:[i32] } (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), @@ -243,10 +243,9 @@ def : Pat<(i32 (zext SOP:$src)), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, // CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1, // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: // GIR_Coverage, 11, // CHECK-NEXT: GIR_EraseRootFromParent_Done, diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected index 88cb03e85204a..8c563d569fbc3 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected @@ -34,7 +34,7 @@ define i64 @test2(i32 %i) nounwind readnone { ; MIR-NEXT: {{ $}} ; MIR-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; MIR-NEXT: [[ADD32rm:%[0-9]+]]:gr32 = ADD32rm [[COPY]], %stack.0.loc, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (dereferenceable load (s32) from %ir.loc) -; MIR-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[ADD32rm]], %subreg.sub_32bit +; MIR-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[ADD32rm]], %subreg.sub_32bit ; MIR-NEXT: $rax = COPY [[SUBREG_TO_REG]] ; MIR-NEXT: RET 0, $rax %loc = alloca i32 diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected index 0175556cd17ea..ddb3e73f02cca 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected @@ -28,21 +28,21 @@ define i64 @i64_test(i64 %i) nounwind readnone { define i64 @i32_test(i32 %i) nounwind readnone { ; PIC-LABEL: i32_test: -; PIC: SelectionDAG has 15 nodes: +; PIC: SelectionDAG has 14 nodes: ; PIC-NEXT: t0: ch,glue = EntryToken ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 ; PIC-NEXT: t7: i32,i32,ch = ADD32rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; PIC-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6> +; PIC-NEXT: t8: i64 = SUBREG_TO_REG t7, TargetConstant:i32<6> ; PIC-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8 ; PIC-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 ; PIC-EMPTY: ; ; WIN-LABEL: i32_test: -; WIN: SelectionDAG has 15 nodes: +; WIN: SelectionDAG has 14 nodes: ; WIN-NEXT: t0: ch,glue = EntryToken ; WIN-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 ; WIN-NEXT: t7: i32,i32,ch = ADD32rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; WIN-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6> +; WIN-NEXT: t8: i64 = SUBREG_TO_REG t7, TargetConstant:i32<6> ; WIN-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8 ; WIN-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 ; WIN-EMPTY: @@ -55,24 +55,24 @@ define i64 @i32_test(i32 %i) nounwind readnone { define i64 @i16_test(i16 %i) nounwind readnone { ; PIC-LABEL: i16_test: -; PIC: SelectionDAG has 18 nodes: +; PIC: SelectionDAG has 17 nodes: ; PIC-NEXT: t0: ch,glue = EntryToken ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 ; PIC-NEXT: t3: i16 = EXTRACT_SUBREG t2, TargetConstant:i32<4> ; PIC-NEXT: t8: i16,i32,ch = ADD16rm t3, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; PIC-NEXT: t15: i32 = MOVZX32rr16 t8 -; PIC-NEXT: t9: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t15, TargetConstant:i32<6> +; PIC-NEXT: t14: i32 = MOVZX32rr16 t8 +; PIC-NEXT: t9: i64 = SUBREG_TO_REG t14, TargetConstant:i32<6> ; PIC-NEXT: t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9 ; PIC-NEXT: t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1 ; PIC-EMPTY: ; ; WIN-LABEL: i16_test: -; WIN: SelectionDAG has 16 nodes: +; WIN: SelectionDAG has 15 nodes: ; WIN-NEXT: t0: ch,glue = EntryToken ; WIN-NEXT: t2: i16,ch = CopyFromReg t0, Register:i16 %0 ; WIN-NEXT: t7: i16,i32,ch = ADD16rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; WIN-NEXT: t14: i32 = MOVZX32rr16 t7 -; WIN-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t14, TargetConstant:i32<6> +; WIN-NEXT: t13: i32 = MOVZX32rr16 t7 +; WIN-NEXT: t8: i64 = SUBREG_TO_REG t13, TargetConstant:i32<6> ; WIN-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8 ; WIN-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 ; WIN-EMPTY: @@ -85,24 +85,24 @@ define i64 @i16_test(i16 %i) nounwind readnone { define i64 @i8_test(i8 %i) nounwind readnone { ; PIC-LABEL: i8_test: -; PIC: SelectionDAG has 18 nodes: +; PIC: SelectionDAG has 17 nodes: ; PIC-NEXT: t0: ch,glue = EntryToken ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 ; PIC-NEXT: t3: i8 = EXTRACT_SUBREG t2, TargetConstant:i32<1> ; PIC-NEXT: t8: i8,i32,ch = ADD8rm t3, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; PIC-NEXT: t15: i32 = MOVZX32rr8 t8 -; PIC-NEXT: t9: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t15, TargetConstant:i32<6> +; PIC-NEXT: t14: i32 = MOVZX32rr8 t8 +; PIC-NEXT: t9: i64 = SUBREG_TO_REG t14, TargetConstant:i32<6> ; PIC-NEXT: t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9 ; PIC-NEXT: t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1 ; PIC-EMPTY: ; ; WIN-LABEL: i8_test: -; WIN: SelectionDAG has 16 nodes: +; WIN: SelectionDAG has 15 nodes: ; WIN-NEXT: t0: ch,glue = EntryToken ; WIN-NEXT: t2: i8,ch = CopyFromReg t0, Register:i8 %0 ; WIN-NEXT: t7: i8,i32,ch = ADD8rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; WIN-NEXT: t14: i32 = MOVZX32rr8 t7 -; WIN-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t14, TargetConstant:i32<6> +; WIN-NEXT: t13: i32 = MOVZX32rr8 t7 +; WIN-NEXT: t8: i64 = SUBREG_TO_REG t13, TargetConstant:i32<6> ; WIN-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8 ; WIN-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 ; WIN-EMPTY: diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp index 84024ec086808..15b5ae24bd5d1 100644 --- a/llvm/utils/TableGen/GlobalISelEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp @@ -1849,19 +1849,19 @@ Error GlobalISelEmitter::constrainOperands(action_iterator InsertPt, // an explicitly given register class, we'll use that. Otherwise, we will // fail. const CodeGenRegisterClass *SubClass = - inferRegClassFromPattern(Dst.getChild(1)); + inferRegClassFromPattern(Dst.getChild(0)); if (!SubClass) return failedImport( - "Cannot infer register class from SUBREG_TO_REG child #1"); + "Cannot infer register class from SUBREG_TO_REG child #0"); // We don't have a child to look at that might have a super register node. const CodeGenRegisterClass *SuperClass = - inferSuperRegisterClass(Dst.getExtType(0), Dst.getChild(2)); + inferSuperRegisterClass(Dst.getExtType(0), Dst.getChild(1)); if (!SuperClass) return failedImport( "Cannot infer register class for SUBREG_TO_REG operand #0"); M.insertAction(InsertPt, InsnID, 0, *SuperClass); - M.insertAction(InsertPt, InsnID, 2, + M.insertAction(InsertPt, InsnID, 1, *SubClass); } else if (DstIName == "REG_SEQUENCE") { const CodeGenRegisterClass *SuperClass = @@ -2004,10 +2004,10 @@ GlobalISelEmitter::inferRegClassFromInstructionPattern(const TreePatternNode &N, } if (InstName == "SUBREG_TO_REG") { - // (outs $super_dst), (ins $super_src, $sub_src, $sub_idx) + // (outs $super_dst), (ins $sub_src, $sub_idx) // Find a register class that supports both the specified sub-register // index and the type of the instruction's result. - return inferSuperRegisterClass(N.getExtType(0), N.getChild(2)); + return inferSuperRegisterClass(N.getExtType(0), N.getChild(1)); } // Handle destination record types that we can safely infer a register class