diff --git a/clang/test/CodeGen/SystemZ/systemz-ppa2.c b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
index 26b068ff03d53..f7cb5bcb1f3bf 100644
--- a/clang/test/CodeGen/SystemZ/systemz-ppa2.c
+++ b/clang/test/CodeGen/SystemZ/systemz-ppa2.c
@@ -5,23 +5,21 @@
 //     We try to cover all cases, and use substitution blocks to
 //     help write the tests. The contents of the PPA2 itself should
 //     not be different.
-//   + the [[:space:]] combines the two .byte lines into one pattern.
-//     This is necessary because if the lines were separated, the first
-//     .byte (i.e., the one for the 3) would, it seems, also match
-//     the .byte line below for the 34.
 
 // REQUIRES: systemz-registered-target
 
 // RUN: %clang_cc1 -triple s390x-ibm-zos -xc -S -o - %s | FileCheck %s --check-prefix CHECK-C
-// CHECK-C:        [[PPA2:(.L)|(L#)PPA2]]:
-// CHECK-C-NEXT:   .byte        3{{[[:space:]]*}}.byte 0
-// CHECK-C-NEXT:   .byte        34{{$}}
-// CHECK-C-NEXT:   .byte        {{4}}
-// CHECK-C-NEXT:   .long        {{(CELQSTRT)}}-[[PPA2]]
+// CHECK-C:        [[PPA2:(.L)|(L#)PPA2]] DS 0H
+// CHECK-C-NEXT:   DC  XL1'03'
+// CHECK-C-NEXT:   DC  XL1'00'
+// CHECK-C-NEXT:   DC  XL1'22'
+// CHECK-C-NEXT:   DC  XL1'04'
+// CHECK-C-NEXT:   DC AD(CELQSTRT-[[PPA2]])
 
 // RUN: %clang_cc1 -triple s390x-ibm-zos -xc++ -S -o - %s | FileCheck %s --check-prefix CHECK-CXX
-// CHECK-CXX:        [[PPA2:(.L)|(L#)PPA2]]:
-// CHECK-CXX-NEXT:   .byte      3{{[[:space:]]*}}.byte 1
-// CHECK-CXX-NEXT:   .byte      34{{$}}
-// CHECK-CXX-NEXT:   .byte      {{4}}
-// CHECK-CXX-NEXT:   .long      {{(CELQSTRT)}}-[[PPA2]]
+// CHECK-CXX:        [[PPA2:(.L)|(L#)PPA2]] DS 0H
+// CHECK-CXX-NEXT:   DC  XL1'03'
+// CHECK-CXX-NEXT:   DC  XL1'01'
+// CHECK-CXX-NEXT:   DC  XL1'22'
+// CHECK-CXX-NEXT:   DC  XL1'04'
+// CHECK-CXX-NEXT:   DC AD(CELQSTRT-[[PPA2]])
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
index faef5bb926780..4356f7ad05121 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
@@ -41,7 +41,7 @@ using namespace llvm;
 // z/OS
 static cl::opt<bool> GNUAsOnzOSCL("emit-gnuas-syntax-on-zos",
                                   cl::desc("Emit GNU Assembly Syntax on z/OS."),
-                                  cl::init(true));
+                                  cl::init(false));
 
 const unsigned SystemZMC::GR32Regs[16] = {
     SystemZ::R0L,  SystemZ::R1L,  SystemZ::R2L,  SystemZ::R3L,
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-01.ll b/llvm/test/CodeGen/SystemZ/call-zos-01.ll
index 7ad1e4c4679eb..7a2fb3f2dfc49 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-01.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-01.ll
@@ -2,14 +2,14 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
 
-; CHECK-LABEL: call_char:
+; CHECK-LABEL: call_char DS 0H
 ; CHECK: lghi  1,8
 define i8 @call_char(){
   %retval = call i8 (i8) @pass_char(i8 8)
   ret i8 %retval
 }
 
-; CHECK-LABEL: call_short:
+; CHECK-LABEL: call_short DS 0H
 ; CHECK: lghi  1,16
 define i16 @call_short() {
 entry:
@@ -17,7 +17,7 @@ entry:
   ret i16 %retval
 }
 
-; CHECK-LABEL: call_int:
+; CHECK-LABEL: call_int DS 0H
 ; CHECK: lghi  1,32
 ; CHECK: lghi  2,33
 define i32 @call_int() {
@@ -26,7 +26,7 @@ entry:
   ret i32 %retval
 }
 
-; CHECK-LABEL: call_long:
+; CHECK-LABEL: call_long DS 0H
 ; CHECK: lghi  1,64
 ; CHECK: lghi  2,65
 ; CHECK: lghi  3,66
@@ -36,7 +36,7 @@ entry:
   ret i64 %retval
 }
 
-; CHECK-LABEL: call_ptr:
+; CHECK-LABEL: call_ptr DS 0H
 ; CHECK: lgr 1,2
 define i32 @call_ptr(ptr %p1, ptr %p2) {
 entry:
@@ -44,7 +44,7 @@ entry:
   ret i32 %retval
 }
 
-; CHECK-LABEL: call_integrals:
+; CHECK-LABEL: call_integrals DS 0H
 ; CHECK: lghi  1,64
 ; CHECK: lghi  2,32
 ; CHECK: lghi  3,16
@@ -54,28 +54,28 @@ entry:
   ret i64 %retval
 }
 
-; CHECK-LABEL: pass_char:
+; CHECK-LABEL: pass_char DS 0H
 ; CHECK: lgr 3,1
 define signext i8 @pass_char(i8 signext %arg) {
 entry:
   ret i8 %arg
 }
 
-; CHECK-LABEL: pass_short:
+; CHECK-LABEL: pass_short DS 0H
 ; CHECK: lgr 3,1
 define signext i16 @pass_short(i16 signext %arg) {
 entry:
   ret i16 %arg
 }
 
-; CHECK-LABEL: pass_int:
+; CHECK-LABEL: pass_int DS 0H
 ; CHECK: lgr 3,2
 define signext i32 @pass_int(i32 signext %arg0, i32 signext %arg1) {
 entry:
   ret i32 %arg1
 }
 
-; CHECK-LABEL: pass_long:
+; CHECK-LABEL: pass_long DS 0H
 ; CHECK: agr 1,2
 ; CHECK: agr 3,1
 define signext i64 @pass_long(i64 signext %arg0, i64 signext %arg1, i64 signext %arg2) {
@@ -85,7 +85,7 @@ entry:
   ret i64 %M
 }
 
-; CHECK-LABEL: pass_integrals0:
+; CHECK-LABEL: pass_integrals0 DS 0H
 ; CHECK: ag  2,2200(4)
 ; CHECK-NEXT: lgr 3,2
 define signext i64 @pass_integrals0(i64 signext %arg0, i32 signext %arg1, i16 signext %arg2, i64 signext %arg3) {
@@ -95,7 +95,7 @@ entry:
   ret i64 %M
 }
 
-; CHECK-LABEL: call_float:
+; CHECK-LABEL: call_float DS 0H
 ; CHECK: le 0,0({{[0-9]}})
 define float @call_float() {
 entry:
@@ -103,7 +103,7 @@ entry:
   ret float %ret
 }
 
-; CHECK-LABEL: call_double:
+; CHECK-LABEL: call_double DS 0H
 ; CHECK: larl  [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
 ; CHECK-NEXT: ld  0,0([[GENREG]])
 define double @call_double() {
@@ -112,7 +112,7 @@ entry:
   ret double %ret
 }
 
-; CHECK-LABEL: call_longdouble:
+; CHECK-LABEL: call_longdouble DS 0H
 ; CHECK: larl  [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
 ; CHECK-NEXT: ld  0,0([[GENREG]])
 ; CHECK-NEXT: ld  2,8([[GENREG]])
@@ -122,7 +122,7 @@ entry:
   ret fp128 %ret
 }
 
-; CHECK-LABEL: call_floats0
+; CHECK-LABEL: call_floats0 DS 0H
 ; CHECK: larl  [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
 ; CHECK-NEXT: ld  1,0([[GENREG]])
 ; CHECK-NEXT: ld  3,8([[GENREG]])
@@ -135,7 +135,7 @@ entry:
   ret i64 %ret
 }
 
-; CHECK-LABEL: call_floats1
+; CHECK-LABEL: call_floats1 DS 0H
 ; CHECK: lxr 1,0
 ; CHECK: ldr 0,4
 ; CHECK: lxr 4,1
@@ -145,7 +145,7 @@ entry:
   ret i64 %ret
 }
 
-; CHECK-LABEL: pass_float:
+; CHECK-LABEL: pass_float DS 0H
 ; CHECK: larl  1,L#{{CPI[0-9]+_[0-9]+}}
 ; CHECK: aeb 0,0(1)
 define float @pass_float(float %arg) {
@@ -154,7 +154,7 @@ entry:
   ret float %X
 }
 
-; CHECK-LABEL: pass_double:
+; CHECK-LABEL: pass_double DS 0H
 ; CHECK: larl  1,L#{{CPI[0-9]+_[0-9]+}}
 ; CHECK: adb 0,0(1)
 define double @pass_double(double %arg) {
@@ -163,7 +163,7 @@ entry:
   ret double %X
 }
 
-; CHECK-LABEL: pass_longdouble
+; CHECK-LABEL: pass_longdouble DS 0H
 ; CHECK: larl  1,L#{{CPI[0-9]+_[0-9]+}}
 ; CHECK: lxdb  1,0(1)
 ; CHECK: axbr  0,1
@@ -173,7 +173,7 @@ entry:
   ret fp128 %X
 }
 
-; CHECK-LABEL: pass_floats0
+; CHECK-LABEL: pass_floats0 DS 0H
 ; CHECK: larl  1,L#{{CPI[0-9]+_[0-9]+}}
 ; CHECK: axbr  0,4
 ; CHECK: axbr  1,0
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-02.ll b/llvm/test/CodeGen/SystemZ/call-zos-02.ll
index a7f600ae99db0..4f1013fc8974d 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-02.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-02.ll
@@ -1,4 +1,4 @@
-; RUN: llc --mtriple=s390x-ibm-zos --show-mc-encoding < %s | FileCheck %s
+; RUN: llc --mtriple=s390x-ibm-zos --show-mc-encoding -emit-gnuas-syntax-on-zos=1 < %s | FileCheck %s
 
 define internal signext i32 @caller() {
 entry:
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-i128.ll b/llvm/test/CodeGen/SystemZ/call-zos-i128.ll
index 98c3d84bc8bf9..c12e26184f068 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-i128.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-i128.ll
@@ -2,7 +2,7 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z13 | FileCheck %s
 
-; CHECK-LABEL: call_i128:
+; CHECK-LABEL: call_i128 DS 0H
 ; CHECK-DAG: larl    1,L#CPI0_0
 ; CHECK-DAG: vl      0,0(1),3
 ; CHECK-DAG: vst     0,2256(4),3
@@ -19,7 +19,7 @@ entry:
   ret i128 %retval
 }
 
-; CHECK-LABEL: pass_i128:
+; CHECK-LABEL: pass_i128 DS 0H
 ; CHECK: vl      0,0(3),3
 ; CHECK: vl      1,0(2),3
 ; CHECK: vaq     0,1,0
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
index 72f4d79610e0e..147fbe63f5af4 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
@@ -1,7 +1,7 @@
 ; Test passing variable argument lists in 64-bit calls on z/OS.
 ; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z14 | FileCheck %s -check-prefix=ARCH12
-; CHECK-LABEL: call_vararg_double0:
+; CHECK-LABEL: call_vararg_double0 DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    lg 6,8(5)
@@ -21,7 +21,7 @@ entry:
   ret i64 %retval
 }
 
-; CHECK-LABEL: call_vararg_double1:
+; CHECK-LABEL: call_vararg_double1  DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    llihf 0,1074118262
@@ -44,7 +44,7 @@ entry:
   ret i64 %retval
 }
 
-; CHECK-LABEL: call_vararg_double2:
+; CHECK-LABEL: call_vararg_double2  DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    lg 6,24(5)
@@ -63,7 +63,7 @@ entry:
   ret i64 %retval
 }
 
-; CHECK-LABEL: call_vararg_double3:
+; CHECK-LABEL: call_vararg_double3 DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    llihf 0,1072703839
@@ -89,7 +89,7 @@ entry:
 }
 
 ;; TODO: The extra COPY after LGDR is unnecessary (machine-scheduler introduces the overlap).
-; CHECK-LABEL: call_vararg_both0:
+; CHECK-LABEL: call_vararg_both0 DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    lg 6,40(5)
@@ -107,7 +107,7 @@ define i64 @call_vararg_both0(i64 %arg0, double %arg1) {
   ret i64 %retval
 }
 
-; CHECK-LABEL: call_vararg_long_double0:
+; CHECK-LABEL: call_vararg_long_double0 DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    larl 1,L#CPI5_0
@@ -131,7 +131,7 @@ entry:
   ret i64 %retval
 }
 
-; CHECK-LABEL: call_vararg_long_double1:
+; CHECK-LABEL: call_vararg_long_double1 DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    lg 6,8(5)
@@ -152,8 +152,7 @@ entry:
   ret i64 %retval
 }
 
-; CHECK-LABEL: call_vararg_long_double2
-; CHECK-LABEL: call_vararg_long_double2:
+; CHECK-LABEL: call_vararg_long_double2 DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    std 4,2208(4)
@@ -176,7 +175,7 @@ entry:
   ret i64 %retval
 }
 
-; CHECK-LABEL: call_vararg_long_double3:
+; CHECK-LABEL: call_vararg_long_double3 DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    lg 6,40(5)
@@ -194,7 +193,7 @@ entry:
   ret i64 %retval
 }
 
-; ARCH12-LABEL: call_vec_vararg_test0
+; ARCH12-LABEL: call_vec_vararg_test0 DS 0H
 ; ARCH12: vlgvg 3,24,1
 ; ARCH12: vlgvg 2,24,0
 ; ARCH12: lghi  1,1
@@ -203,7 +202,7 @@ define void @call_vec_vararg_test0(<2 x double> %v) {
   ret void
 }
 
-; ARCH12-LABEL: call_vec_vararg_test1
+; ARCH12-LABEL: call_vec_vararg_test1 DS 0H
 ; ARCH12: larl  1,L#CPI10_0
 ; ARCH12: vl    0,0(1),3
 ; ARCH12: vlgvg 3,24,0
@@ -215,7 +214,7 @@ define void @call_vec_vararg_test1(<4 x i32> %v, <2 x i64> %w) {
   ret void
 }
 
-; ARCH12-LABEL: call_vec_char_vararg_straddle
+; ARCH12-LABEL: call_vec_char_vararg_straddle DS 0H
 ; ARCH12: vlgvg 3,24,0
 ; ARCH12: lghi  1,1
 ; ARCH12: lghi  2,2
@@ -225,7 +224,7 @@ define void @call_vec_char_vararg_straddle(<16 x i8> %v) {
   ret void
 }
 
-; ARCH12-LABEL: call_vec_short_vararg_straddle
+; ARCH12-LABEL: call_vec_short_vararg_straddle DS 0H
 ; ARCH12: vlgvg 3,24,0
 ; ARCH12: lghi  1,1
 ; ARCH12: lghi  2,2
@@ -235,7 +234,7 @@ define void @call_vec_short_vararg_straddle(<8 x i16> %v) {
   ret void
 }
 
-; ARCH12-LABEL: call_vec_int_vararg_straddle
+; ARCH12-LABEL: call_vec_int_vararg_straddle DS 0H
 ; ARCH12: vlgvg 3,24,0
 ; ARCH12: lghi  1,1
 ; ARCH12: lghi  2,2
@@ -245,7 +244,7 @@ define void @call_vec_int_vararg_straddle(<4 x i32> %v) {
   ret void
 }
 
-; ARCH12-LABEL: call_vec_double_vararg_straddle
+; ARCH12-LABEL: call_vec_double_vararg_straddle DS 0H
 ; ARCH12: vlgvg 3,24,0
 ; ARCH12: lghi  1,1
 ; ARCH12: lghi  2,2
@@ -255,7 +254,7 @@ define void @call_vec_double_vararg_straddle(<2 x double> %v) {
   ret void
 }
 
-; CHECK-LABEL: call_vararg_integral0:
+; CHECK-LABEL: call_vararg_integral0 DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    lg 0,2392(4)
@@ -273,7 +272,7 @@ entry:
   ret i64 %retval
 }
 
-; CHECK-LABEL: call_vararg_float0:
+; CHECK-LABEL: call_vararg_float0 DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    lg 6,24(5)
@@ -291,7 +290,7 @@ entry:
   ret i64 %retval
 }
 
-; CHECK-LABEL: call_vararg_float1:
+; CHECK-LABEL: call_vararg_float1 DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    lg 6,72(5)
@@ -325,7 +324,7 @@ entry:
 ;   return ret;
 ; }
 ;
-; CHECK-LABEL: pass_vararg:
+; CHECK-LABEL: pass_vararg DS 0H
 ; CHECK:         stmg 6,7,1904(4)
 ; CHECK-NEXT:    aghi 4,-160
 ; CHECK-NEXT:    stg 2,2344(4)
diff --git a/llvm/test/CodeGen/SystemZ/llvm.sincos.ll b/llvm/test/CodeGen/SystemZ/llvm.sincos.ll
index e47759b188296..964f9b696c1dd 100644
--- a/llvm/test/CodeGen/SystemZ/llvm.sincos.ll
+++ b/llvm/test/CodeGen/SystemZ/llvm.sincos.ll
@@ -183,19 +183,24 @@ define { <2 x fp128>, <2 x fp128> } @test_sincos_v2f128(<2 x fp128> %a) #0 {
   ret { <2 x fp128>, <2 x fp128> } %result
 }
 
-
-; ZOS: .quad	RD(@@FSIN@B)                    * Offset 0 function descriptor of @@FSIN@B
-; ZOS: .quad	VD(@@FSIN@B)
-; ZOS: .quad	RD(@@FCOS@B)                    * Offset 16 function descriptor of @@FCOS@B
-; ZOS: .quad	VD(@@FCOS@B)
-; ZOS: .quad	RD(@@SSIN@B)                    * Offset 32 function descriptor of @@SSIN@B
-; ZOS: .quad	VD(@@SSIN@B)
-; ZOS: .quad	RD(@@SCOS@B)                    * Offset 48 function descriptor of @@SCOS@B
-; ZOS: .quad	VD(@@SCOS@B)
-; ZOS: .quad	RD(@@LSIN@B)                    * Offset 64 function descriptor of @@LSIN@B
-; ZOS: .quad	VD(@@LSIN@B)
-; ZOS: .quad	RD(@@LCOS@B)                    * Offset 80 function descriptor of @@LCOS@B
-; ZOS: .quad	VD(@@LCOS@B)
+; ZOS: * Offset 0 function descriptor of @@FSIN@B
+; ZOS: DC RD(@@FSIN@B)
+; ZOS: DC VD(@@FSIN@B)
+; ZOS: * Offset 16 function descriptor of @@FCOS@B
+; ZOS: DC RD(@@FCOS@B)
+; ZOS: DC VD(@@FCOS@B)
+; ZOS: * Offset 32 function descriptor of @@SSIN@B
+; ZOS: DC RD(@@SSIN@B)
+; ZOS: DC VD(@@SSIN@B)
+; ZOS: * Offset 48 function descriptor of @@SCOS@B
+; ZOS: DC RD(@@SCOS@B)
+; ZOS: DC VD(@@SCOS@B)
+; ZOS: * Offset 64 function descriptor of @@LSIN@B
+; ZOS: DC RD(@@LSIN@B)
+; ZOS: DC VD(@@LSIN@B)
+; ZOS: * Offset 80 function descriptor of @@LCOS@B
+; ZOS: DC RD(@@LCOS@B)
+; ZOS: DC VD(@@LCOS@B)
 
 
 attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
index a95f68b5e118d..ddd6850e54406 100644
--- a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
@@ -103,7 +103,7 @@ declare void @use_foo(ptr)
 
 define void @ptr32_to_ptr(ptr %f, ptr addrspace(1) %i) {
 entry:
-; CHECK-LABEL: ptr32_to_ptr:
+; CHECK-LABEL: ptr32_to_ptr DS 0H
 ; CHECK:       llgtr 0,2
 ; CHECK-NEXT:  stg   0,8(1)
   %0 = addrspacecast ptr addrspace(1) %i to ptr
@@ -115,7 +115,7 @@ entry:
 
 define void @ptr_to_ptr32(ptr %f, ptr %i) {
 entry:
-; CHECK-LABEL: ptr_to_ptr32:
+; CHECK-LABEL: ptr_to_ptr32 DS 0H
 ; CHECK:       nilh 2,32767
 ; CHECK-NEXT:  st   2,0(1)
   %0 = addrspacecast ptr %i to ptr addrspace(1)
@@ -127,7 +127,7 @@ entry:
 
 define void @ptr32_to_ptr32(ptr %f, ptr addrspace(1) %i) {
 entry:
-; CHECK-LABEL: ptr32_to_ptr32:
+; CHECK-LABEL: ptr32_to_ptr32 DS 0H
 ; CHECK:       st 2,0(1)
   %p32 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 0
   store ptr addrspace(1) %i, ptr %p32, align 8
@@ -136,7 +136,7 @@ entry:
 }
 
 define void @ptr_to_ptr(ptr %f, ptr %i) {
-; CHECK-LABEL: ptr_to_ptr:
+; CHECK-LABEL: ptr_to_ptr DS 0H
 ; CHECK:       stg 2,8(1)
   %p64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 1
   store ptr %i, ptr %p64, align 8
@@ -146,7 +146,7 @@ define void @ptr_to_ptr(ptr %f, ptr %i) {
 
 define void @test_indexing(ptr %f) {
 entry:
-; CHECK-LABEL: test_indexing:
+; CHECK-LABEL: test_indexing DS 0H
 ; CHECK:       l     0,1032
 ; CHECK:       llgtr 0,0
 ; CHECK:       stg   0,16(1)
@@ -160,7 +160,7 @@ entry:
 
 define void @test_indexing_2(ptr %f) {
 entry:
-; CHECK-LABEL: test_indexing_2:
+; CHECK-LABEL: test_indexing_2 DS 0H
 ; CHECK:       lhi   0,16
 ; CHECK-NEXT:  a     0,1032
 ; CHECK-NEXT:  llgtr 2,0
@@ -181,7 +181,7 @@ entry:
 
 define ptr @test_misc() {
 entry:
-; CHECK-LABEL: test_misc:
+; CHECK-LABEL: test_misc DS 0H
 ; CHECK:       lhi   0,88
 ; CHECK-NEXT:  a     0,1208
 ; CHECK-NEXT:  llgtr 1,0
@@ -204,7 +204,7 @@ entry:
 
 define ptr addrspace(1) @test_misc_2() {
 entry:
-; CHECK-LABEL: test_misc_2:
+; CHECK-LABEL: test_misc_2 DS 0H
 ; CHECK:       lhi   0,544
 ; CHECK:       a     0,16
 ; CHECK:       llgtr 1,0
@@ -221,7 +221,7 @@ entry:
 
 define zeroext i16 @test_misc_3() {
 entry:
-; CHECK-LABEL: test_misc_3:
+; CHECK-LABEL: test_misc_3 DS 0H
 ; CHECK:       a     0,548
 ; CHECK-NEXT:  llgtr 1,0
 ; CHECK-NEXT:  llgh  3,0(1)
@@ -235,7 +235,7 @@ entry:
 
 define signext i32 @test_misc_4() {
 entry:
-; CHECK-LABEL: test_misc_4:
+; CHECK-LABEL: test_misc_4 DS 0H
 ; CHECK:       lhi   0,88
 ; CHECK-NEXT:  a     0,1208
 ; CHECK-NEXT:  llgtr 1,0
@@ -261,7 +261,7 @@ entry:
 
 define void @test_misc_5(ptr %f) {
 entry:
-; CHECK-LABEL: test_misc_5:
+; CHECK-LABEL: test_misc_5 DS 0H
 ; CHECK:       l     0,548
 ; CHECK-NEXT:  lg  6,8(5)
 ; CHECK-NEXT:  lg  5,0(5)
@@ -277,7 +277,7 @@ entry:
 
 define signext i32 @get_processor_count() {
 entry:
-; CHECK-LABEL: get_processor_count:
+; CHECK-LABEL: get_processor_count DS 0H
 ; CHECK: lhi 0,660
 ; CHECK-NEXT: a 0,16
 ; CHECK-NEXT: llgtr 1,0
@@ -296,7 +296,7 @@ entry:
 
 define void @spill_ptr32_args_to_registers(i8 addrspace(1)* %p) {
 entry:
-; CHECK-LABEL: spill_ptr32_args_to_registers:
+; CHECK-LABEL: spill_ptr32_args_to_registers DS 0H
 ; CHECK:         stmg 6,7,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    lgr 2,1
@@ -327,7 +327,7 @@ declare void @g(i32 signext, ...)
 ; cast to __ptr32, setting the upper 32 bit to zero.
 ;
 define signext i32 @setlength() {
-; CHECK-LABEL: setlength:
+; CHECK-LABEL: setlength DS 0H
 ; CHECK: basr    7,6
 ; CHECK: lgr     [[MALLOC:[0-9]+]],3
 ; CHECK: basr    7,6
@@ -351,7 +351,7 @@ entry:
 ; the function now returns a __ptr32.
 ;
 define signext i32 @setlength2() {
-; CHECK-LABEL: setlength2:
+; CHECK-LABEL: setlength2 DS 0H
 ; CHECK: basr    7,6
 ; CHECK: lgr     [[MALLOC:[0-9]+]],3
 ; CHECK: basr    7,6
diff --git a/llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll b/llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
index 616cb370f6fc8..f3bdf64683bb6 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
@@ -2,7 +2,7 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-ibm-zos | FileCheck %s
 
-; CHECK-LABEL: DoIt:
+; CHECK-LABEL: DoIt DS 0H
 ; CHECK:    stmg    6,7,1840(4)
 ; CHECK:    aghi    4,-224
 ; CHECK:    lg  1,0(5)
@@ -25,7 +25,7 @@ entry:
 declare void @DoFunc()
 declare void @Caller(ptr noundef)
 
-; CHECK-LABEL: get_i:
+; CHECK-LABEL: get_i DS 0H
 ; CHECK:    stmg    6,8,1872(4)
 ; CHECK:    aghi    4,-192
 ; CHECK:    lg  1,24(5)
@@ -56,14 +56,18 @@ entry:
 declare signext i32 @callout(i32 signext)
 
 ; CHECK: stdin#C CSECT
-; CHECK: C_WSA64 CATTR ALIGN(4),FILL(0),DEFLOAD,NOTEXECUTABLE,RMODE(64),PART(stdin#S)
+; CHECK: C_WSA64 CATTR ALIGN(4),FILL(0),DEFLOAD,NOTEXECUTABLE,RMODE(64),PART(stdi
+; CHECK:                in#S)
 ; CHECK: stdin#S XATTR LINKAGE(XPLINK),REFERENCE(DATA),SCOPE(SECTION)
-; CHECK:  .set L#DoFunc@indirect0, DoFunc
-; CHECK:      .indirect_symbol   L#DoFunc@indirect0
-; CHECK:  .quad VD(L#DoFunc@indirect0)         * Offset 0 pointer to function descriptor DoFunc
-; CHECK:  .quad RD(Caller)                     * Offset 8 function descriptor of Caller
-; CHECK:  .quad VD(Caller)
-; CHECK:  .quad AD(i2)                          * Offset 24 pointer to data symbol i2
-; CHECK:  .quad AD(i)                           * Offset 32 pointer to data symbol i
-; CHECK:  .quad RD(callout)                     * Offset 40 function descriptor of callout
-; CHECK:  .quad VD(callout)
+; CHECK: * Offset 0 pointer to function descriptor DoFunc
+; CHECK:  DC VD(L#DoFunc@indirect0)
+; CHECK: * Offset 8 function descriptor of Caller
+; CHECK:  DC RD(Caller)
+; CHECK:  DC VD(Caller)
+; CHECK: * Offset 24 pointer to data symbol i2
+; CHECK:  DC AD(i2)
+; CHECK: * Offset 32 pointer to data symbol i
+; CHECK:  DC AD(i)
+; CHECK: * Offset 40 function descriptor of callout
+; CHECK:  DC RD(callout)
+; CHECK:  DC VD(callout)
diff --git a/llvm/test/CodeGen/SystemZ/zos-ada.ll b/llvm/test/CodeGen/SystemZ/zos-ada.ll
index 8f00f32c1b805..dcdcf2d6c6dc8 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ada.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ada.ll
@@ -2,7 +2,7 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
 
-; CHECK-LABEL: caller:
+; CHECK-LABEL: caller DS 0H
 ; CHECK:         stmg 6,8,1872(4)
 ; CHECK-NEXT:    aghi 4,-192
 ; CHECK-NEXT:    lgr 8,5
diff --git a/llvm/test/CodeGen/SystemZ/zos-alias-unsupported.ll b/llvm/test/CodeGen/SystemZ/zos-alias-unsupported.ll
index 1a01e91d1f8f2..5aeebcd157c84 100644
--- a/llvm/test/CodeGen/SystemZ/zos-alias-unsupported.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-alias-unsupported.ll
@@ -1,6 +1,6 @@
 ; Test aliasing errors on z/OS
 
-; RUN: not llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 2>&1 | FileCheck %s
+; RUN: not llc < %s -mtriple=s390x-ibm-zos 2>&1 | FileCheck %s
 
 ; CHECK: error: Only aliases to functions is supported in GOFF.
 ; CHECK: error: Weak alias/reference not supported on z/OS
diff --git a/llvm/test/CodeGen/SystemZ/zos-dwarf.ll b/llvm/test/CodeGen/SystemZ/zos-dwarf.ll
index 919602c799f7a..372126f5d5737 100644
--- a/llvm/test/CodeGen/SystemZ/zos-dwarf.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-dwarf.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-ibm-zos | FileCheck %s
 
 @fortytwo = hidden global i32 42, align 4, !dbg !0
 
diff --git a/llvm/test/CodeGen/SystemZ/zos-frameaddr.ll b/llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
index f0a8a67041d12..ae5f71e31fc50 100644
--- a/llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
@@ -4,7 +4,7 @@
 ; The current function's frame address is the address of
 ; the optional back chain slot.
 define ptr @fp0() nounwind {
-; CHECK-LABEL: fp0:
+; CHECK-LABEL: fp0 DS 0H
 ; CHECK:         la 3,2048(4)
 ; CHECK-NEXT:    b 2(7)
 entry:
@@ -15,7 +15,7 @@ entry:
 ; Check that the frame address is correct in a presence
 ; of a stack frame.
 define ptr @fp0f() nounwind {
-; CHECK-LABEL: fp0f:
+; CHECK-LABEL: fp0f DS 0H
 ; CHECK:         stmg 6,7,1904(4)
 ; CHECK-NEXT:    aghi 4,-160
 ; CHECK-NEXT:    la 3,2048(4)
@@ -30,7 +30,7 @@ entry:
 
 ; Check the caller's frame address.
 define ptr @fpcaller() nounwind "backchain" {
-; CHECK-LABEL: fpcaller:
+; CHECK-LABEL: fpcaller DS 0H
 ; CHECK:         stmg 4,7,2048(4)
 ; CHECK-NEXT:    lg 3,2048(4)
 ; CHECK-NEXT:    lmg 4,7,2048(4)
@@ -42,7 +42,7 @@ entry:
 
 ; Check the caller's frame address.
 define ptr @fpcallercaller() nounwind "backchain" {
-; CHECK-LABEL: fpcallercaller:
+; CHECK-LABEL: fpcallercaller DS 0H
 ; CHECK:         stmg 4,7,2048(4)
 ; CHECK-NEXT:    lg 1,2048(4)
 ; CHECK-NEXT:    lg 3,0(1)
diff --git a/llvm/test/CodeGen/SystemZ/zos-func-alias.ll b/llvm/test/CodeGen/SystemZ/zos-func-alias.ll
index 7e93570e44534..ee862cafc6776 100644
--- a/llvm/test/CodeGen/SystemZ/zos-func-alias.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-func-alias.ll
@@ -1,6 +1,6 @@
 ; Test function aliasing on z/OS
 ;
-; RUN: llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-ibm-zos | FileCheck %s
 
 ; CHECK:      ENTRY foo
 ; CHECK-NEXT: foo XATTR LINKAGE(XPLINK),REFERENCE(CODE),SCOPE(LIBRARY)
diff --git a/llvm/test/CodeGen/SystemZ/zos-hlasm-out.ll b/llvm/test/CodeGen/SystemZ/zos-hlasm-out.ll
index e3d3b0d8825c1..a10686b85e810 100644
--- a/llvm/test/CodeGen/SystemZ/zos-hlasm-out.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-hlasm-out.ll
@@ -1,6 +1,6 @@
 ; Test the HLASM streamer on z/OS to ensure there's no GNU syntax anywhere
 
-; RUN: llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-ibm-zos | FileCheck %s
 
 @.str = private unnamed_addr constant [10 x i8] c"Hello %s\0A\00", align 2
 @Greeting = global ptr @.str, align 8
diff --git a/llvm/test/CodeGen/SystemZ/zos-intrinsics.ll b/llvm/test/CodeGen/SystemZ/zos-intrinsics.ll
index ccae97888d70c..99cfe8e34d266 100644
--- a/llvm/test/CodeGen/SystemZ/zos-intrinsics.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-intrinsics.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple s390x-zos -emit-gnuas-syntax-on-zos=0 < %s | FileCheck %s
+; RUN: llc -mtriple s390x-zos < %s | FileCheck %s
 
 define float @sqrt_ieee(float %x) {
 entry:
diff --git a/llvm/test/CodeGen/SystemZ/zos-jumptable.ll b/llvm/test/CodeGen/SystemZ/zos-jumptable.ll
index 4b11759874088..4c051306fb975 100644
--- a/llvm/test/CodeGen/SystemZ/zos-jumptable.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-jumptable.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple s390x-zos -emit-gnuas-syntax-on-zos=0 < %s | FileCheck %s
+; RUN: llc -mtriple s390x-zos < %s | FileCheck %s
 
 define void @jumptable(i32 signext %in, ptr %out) {
 ; CHECK-LABEL: jumptable DS 0H
diff --git a/llvm/test/CodeGen/SystemZ/zos-landingpad.ll b/llvm/test/CodeGen/SystemZ/zos-landingpad.ll
index 307f280617619..1ae1751f92634 100644
--- a/llvm/test/CodeGen/SystemZ/zos-landingpad.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-landingpad.ll
@@ -19,7 +19,7 @@ done:
 lpad:
   %0 = landingpad { ptr, i32 } cleanup
 ; The Exception Pointer is %r1; the Exception Selector, %r2.
-; CHECK: L#BB{{[^%]*}} %lpad
+; CHECK: L#BB{{[^%]*}} DS 0H
 ; CHECK-DAG: stg 1,{{.*}}
 ; CHECK-DAG: st 2,{{.*}}
   %1 = extractvalue { ptr, i32 } %0, 0
@@ -31,13 +31,17 @@ lpad:
 }
 
 ; Check that offsets to the FD of the personality routine and LSDA are emitted in PPA1
-; CHECK: .byte 145 {{.*PPA1 Flags}}
-; CHECK: Bit 3: 1 = C++ EH block
-; TODO: Emit the value instead of a dummy value.
-; CHECK: Personality routine
-; CHECK: LSDA location
+; CHECK: * PPA1 Flags 4
+; CHECK: *   Bit 3: 1 = C++ EH block
+; CHECK: *   Bit 7: 1 = Name Length and Name
+; CHECK:  DC XL1'91'
+; CHECK: * Personality routine
+; CHECK:  DC XL8'0000000000000020'
+; CHECK: * LSDA location
+; CHECK:  DC XL8'0000000000000028'
 ; Check that the exception table is emitted into .lsda section.
 ; CHECK:  stdin#C CSECT
-; CHECK:  C_WSA64 CATTR ALIGN(2),FILL(0),NOTEXECUTABLE,RMODE(64),PART(.gcc_exception_table.test1)
-; CHECK:  .gcc_exception_table.test1 XATTR LINKAGE(XPLINK),REFERENCE(DATA),SCOPE(SECTION)
-; CHECK: GCC_except_table0:
+; CHECK: C_WSA64 CATTR ALIGN(2),FILL(0),NOTEXECUTABLE,RMODE(64),PART(.gcc_excepti
+; CHECK:                ion_table.test1)
+; CHECK: .gcc_exception_table.test1 XATTR LINKAGE(XPLINK),REFERENCE(DATA),SCOPE(S
+; CHECK:                SECTION)
diff --git a/llvm/test/CodeGen/SystemZ/zos-lower-constant.ll b/llvm/test/CodeGen/SystemZ/zos-lower-constant.ll
index c91b39f72de08..64a51f8e43582 100644
--- a/llvm/test/CodeGen/SystemZ/zos-lower-constant.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-lower-constant.ll
@@ -1,6 +1,6 @@
 ; Test lowering of constants on z/OS
 ;
-; RUN: llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-ibm-zos | FileCheck %s
 
 ; CHECK: func_s CSECT
 ; CHECK: DC AD(AD({{.*}}#S)+XL8'0')
diff --git a/llvm/test/CodeGen/SystemZ/zos-no-eh-label.ll b/llvm/test/CodeGen/SystemZ/zos-no-eh-label.ll
index 43ac737b29778..b28f0dd17599a 100644
--- a/llvm/test/CodeGen/SystemZ/zos-no-eh-label.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-no-eh-label.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple s390x-ibm-zos -emit-gnuas-syntax-on-zos=false < %s | FileCheck %s
+; RUN: llc -mtriple s390x-ibm-zos < %s | FileCheck %s
 
 define signext i32 @_Z9computeitv() personality ptr @__zos_cxx_personality_v2 {
   ret i32 0
diff --git a/llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll b/llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll
index 511bc46567607..32a59e5ba3ea9 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-ibm-zos | FileCheck %s
 %struct.LargeStruct_t = type { [33 x i32] }
 
 @GlobLargeS = hidden global %struct.LargeStruct_t zeroinitializer, align 4
diff --git a/llvm/test/CodeGen/SystemZ/zos-ppa1.ll b/llvm/test/CodeGen/SystemZ/zos-ppa1.ll
index 78593b9f88d1e..f73edfc6ba42e 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ppa1.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ppa1.ll
@@ -1,33 +1,53 @@
 ; RUN: llc -mtriple s390x-ibm-zos < %s | FileCheck %s
 
-; CHECK: L#EPM_void_test_0: * @void_test
 ; CHECK: * XPLINK Routine Layout Entry
-; CHECK: .long   12779717 * Eyecatcher 0x00C300C500C500
-; CHECK: .short  197
-; CHECK: .byte   0
-; CHECK: .byte   241 * Mark Type C'1'
-; CHECK: .long   8 * DSA Size 0x0
+; CHECK: L#EPM_void_test_0 DS 0H
+; CHECK: * Eyecatcher 0x00C300C500C500
+; CHECK:  DC XL7'00C300C500C500'
+; CHECK: * Mark Type C'1'
+; CHECK:  DC XL1'F1'
+; CHECK: * Offset to PPA1
+; CHECK:  DC AD(L#PPA1_void_test_0-L#EPM_void_test_0)
+; CHECK: * DSA Size 0x0
 ; CHECK: * Entry Flags
 ; CHECK: *   Bit 1: 1 = Leaf function
 ; CHECK: *   Bit 2: 0 = Does not use alloca
-; CHECK: L#func_end0:
+; CHECK:  DC XL4'00000008'
+; CHECK:  ENTRY void_test
+; CHECK: L#func_end0 DS 0H
 ; CHECK: stdin#C CSECT
 ; CHECK: C_CODE64 CATTR
-; CHECK: L#PPA1_void_test_0:                     * PPA1
-; CHECK:        .byte   2                               * Version
-; CHECK:        .byte   206                             * LE Signature X'CE'
-; CHECK:        .short  0                               * Saved GPR Mask
-; CHECK:        .byte   128                             * PPA1 Flags 1
-; CHECK:                                        *   Bit 0: 1 = 64-bit DSA
-; CHECK:        .byte   128                             * PPA1 Flags 2
-; CHECK:                                        *   Bit 0: 1 = External procedure
-; CHECK:                                        *   Bit 3: 0 = STACKPROTECT is not enabled
-; CHECK:         .byte   0                               * PPA1 Flags 3
-; CHECK:        .byte   129                             * PPA1 Flags 4
-; CHECK:        .short  0                               * Length/4 of Parms
-; CHECK:        .long   L#func_end0-L#EPM_void_test_0   * Length of Code
-; CHECK:        .long   L#EPM_void_test_0-L#PPA1_void_test_0
-; CHECK:                                        * -- End function
+; CHECK: * PPA1
+; CHECK: L#PPA1_void_test_0 DS 0H
+; CHECK: * Version
+; CHECK:  DC XL1'02'
+; CHECK: * LE Signature X'CE'
+; CHECK:  DC XL1'CE'
+; CHECK: * Saved GPR Mask
+; CHECK:  DC XL2'0000'
+; CHECK: * Offset to PPA2
+; CHECK:  DC AD(L#PPA2-L#PPA1_void_test_0)
+; CHECK: * PPA1 Flags 1
+; CHECK: *   Bit 0: 1 = 64-bit DSA
+; CHECK:  DC XL1'80'
+; CHECK: * PPA1 Flags 2
+; CHECK: *   Bit 0: 1 = External procedure
+; CHECK: *   Bit 3: 0 = STACKPROTECT is not enabled
+; CHECK:  DC XL1'80'
+; CHECK: * PPA1 Flags 3
+; CHECK:  DC XL1'00'
+; CHECK: * PPA1 Flags 4
+; CHECK: *   Bit 7: 1 = Name Length and Name
+; CHECK:  DC XL1'81'
+; CHECK: * Length/4 of Parms
+; CHECK:  DC XL2'0000'
+; CHECK: * Length of Code
+; CHECK:  DC AD(L#func_end0-L#EPM_void_test_0)
+; CHECK: * Length of Name
+; CHECK:  DC XL2'0009'
+; CHECK: * Name of Function
+; CHECK:  DC XL9'A59689846DA385A2A3'
+; CHECK: DC AD(L#EPM_void_test_0-L#PPA1_void_test_0)
 define void @void_test() {
 entry:
   ret void
diff --git a/llvm/test/CodeGen/SystemZ/zos-ppa2.ll b/llvm/test/CodeGen/SystemZ/zos-ppa2.ll
index bf059f9083df0..a4c1d50df5543 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ppa2.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ppa2.ll
@@ -1,35 +1,44 @@
-; RUN: sed -e 's/!"MODE"/!"ascii"/' -e 's/BYTE/133/' %s > %t.ascii.ll
+; RUN: sed -e 's/!"MODE"/!"ascii"/' -e 's/BYTE/85/' %s > %t.ascii.ll
 ; RUN: llc -mtriple s390x-ibm-zos -mcpu=z15 -asm-verbose=true < %t.ascii.ll | \
 ; RUN: FileCheck %t.ascii.ll
 
-; RUN: sed -e 's/!"MODE"/!"ebcdic"/' -e 's/BYTE/129/' %s > %t.ebcdic.ll
+; RUN: sed -e 's/!"MODE"/!"ebcdic"/' -e 's/BYTE/81/' %s > %t.ebcdic.ll
 ; RUN: llc -mtriple s390x-ibm-zos -mcpu=z15 -asm-verbose=true < %t.ebcdic.ll | \
 ; RUN: FileCheck %t.ebcdic.ll
 
 ; CHECK: C_CODE64 CATTR
-; CHECK: L#PPA2:
-; CHECK:    .byte   3
-; CHECK:    .byte   231
-; CHECK:    .byte   34
-; CHECK:    .byte   4
-; CHECK:    .long   CELQSTRT-L#PPA2
-; CHECK:    .long   0
-; CHECK:    .long   L#DVS-L#PPA2
-; CHECK:    .long   0
-; CHECK:    .byte   BYTE
-; CHECK:    .byte   0
-; CHECK:    .short  0
-; CHECK: L#DVS:
-; CHECK:    .ascii  "\361\371\367\360\360\361\360\361\360\360\360\360\360\360"
-; CHECK:    .short  0
-; CHECK:    .quad   L#PPA2-CELQSTRT                 * A(PPA2-CELQSTRT)
-; CHECK: L#PPA1_void_test_0:
-; CHECK:    .long   L#PPA2-L#PPA1_void_test_0       * Offset to PPA2
-; CHECK: B_IDRL CATTR
-; CHECK:    .byte   0
-; CHECK:    .byte   3
-; CHECK:    .short  30
-; CHECK:    .ascii  "\323\323\345\324@@@@@@{{((\\3[0-7]{2}){4})}}\361\371\367\360\360\361\360\361\360\360\360\360\360\360\360\360"
+; CHECK: L#PPA2 DS 0H
+; CHECK:  DC XL1'03'
+; CHECK:  DC XL1'E7'
+; CHECK:  DC XL1'22'
+; CHECK:  DC XL1'04'
+; CHECK:  DC AD(CELQSTRT-L#PPA2)
+; CHECK:  DC XL4'00000000'
+; CHECK:  DC AD(L#DVS-L#PPA2)
+; CHECK:  DC XL4'00000000'
+; CHECK:  DC XL1'BYTE'
+; CHECK:  DC XL1'00'
+; CHECK:  DC XL2'0000'
+; CHECK: L#DVS DS 0H
+; CHECK:  DC XL14'F1F9F7F0F0F1F0F1F0F0F0F0F0F0'
+; CHECK:  DC XL6'F2F3F0F0F0F0'
+; CHECK:  DC XL2'0000'
+
+; CHECK: C_@@QPPA2 CATTR ALIGN(3),FILL(0),NOTEXECUTABLE,READONLY,RMODE(64),PART(.
+; CHECK:                .&ppa2)
+; CHECK: .&ppa2 XATTR LINKAGE(OS),REFERENCE(DATA),SCOPE(SECTION)
+; CHECK: * A(PPA2-CELQSTRT)
+; CHECK:  DC AD(L#PPA2-CELQSTRT)
+
+; CHECK: L#EPM_void_test_0 DS 0H
+; CHECK: * Offset to PPA1
+; CHECK:  DC AD(L#PPA1_void_test_0-L#EPM_void_test_0)
+ 
+; CHECK: B_IDRL CATTR ALIGN(3),FILL(0),NOLOAD,READONLY,RMODE(64)
+; CHECK:  DC XL1'00'
+; CHECK:  DC XL1'03'
+; CHECK:  DC XL2'001E'
+; CHECK:  DC XL30'D3D3E5D4404040404040{{([[:xdigit:]]{8})}}F1F9F7F0F0F1F0F1F0F0F0F0F0F0F0F0'
 
 !llvm.module.flags = !{!0}
 !0 = !{i32 1, !"zos_le_char_mode", !"MODE"}
diff --git a/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll b/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
index 458b27460763f..ecf778a36755b 100644
--- a/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
@@ -5,7 +5,7 @@
 ; Test prolog/epilog for non-XPLEAF.
 
 ; Small stack frame.
-; CHECK-LABEL: func0
+; CHECK-LABEL: func0 DS 0H
 ; CHECK64: stmg  6,7,1872(4)
 ; stmg instruction's displacement field must be 2064-dsa_size
 ; as per ABI
@@ -15,15 +15,16 @@
 ; CHECK64: aghi  4,192
 ; CHECK64: b 2(7)
 
-; CHECK64: L#PPA1_func0_0:
-; CHECK64: .short	0  * Length/4 of Parms
+; CHECK64: L#PPA1_func0_0 DS 0H
+; CHECK64: * Length/4 of Parms
+; CHECK64:  DC XL2'0000'
 define void @func0() {
   call i64 (i64) @fun(i64 10) 
   ret void
 }
 
 ; Spill all GPR CSRs
-; CHECK-LABEL: func1
+; CHECK-LABEL: func1 DS 0H
 ; CHECK64: stmg 6,15,1904(4)
 ; CHECK64: aghi  4,-160
 
@@ -31,8 +32,9 @@ define void @func0() {
 ; CHECK64: aghi  4,160
 ; CHECK64: b 2(7)
 
-; CHECK64: L#PPA1_func1_0:
-; CHECK64: .short	2  * Length/4 of Parms
+; CHECK64: L#PPA1_func1_0 DS 0H
+; CHECK64: * Length/4 of Parms
+; CHECK64:  DC XL2'0002'
 define void @func1(ptr %ptr) {
   %l01 = load volatile i64, ptr %ptr
   %l02 = load volatile i64, ptr %ptr
@@ -84,42 +86,42 @@ define void @func1(ptr %ptr) {
 
 
 ; Spill all FPRs and VRs
-; CHECK-LABEL: func2
+; CHECK-LABEL: func2 DS 0H
 ; CHECK64: stmg	6,7,1744(4)
 ; CHECK64: aghi  4,-320
-; CHECK64: vst  16,{{[0-9]+}}(4),4                   * 16-byte Spill
-; CHECK64: vst  17,{{[0-9]+}}(4),4                   * 16-byte Spill
-; CHECK64: vst  18,{{[0-9]+}}(4),4                   * 16-byte Spill
-; CHECK64: vst  19,{{[0-9]+}}(4),4                   * 16-byte Spill
-; CHECK64: vst  20,{{[0-9]+}}(4),4                   * 16-byte Spill
-; CHECK64: vst  21,{{[0-9]+}}(4),4                   * 16-byte Spill
-; CHECK64: vst  22,{{[0-9]+}}(4),4                   * 16-byte Spill
-; CHECK64: vst  23,{{[0-9]+}}(4),4                   * 16-byte Spill
-; CHECK64: std	8,{{[0-9]+}}(4)                       * 8-byte Spill
-; CHECK64: std	9,{{[0-9]+}}(4)                       * 8-byte Spill
-; CHECK64: std	10,{{[0-9]+}}(4)                      * 8-byte Spill
-; CHECK64: std	11,{{[0-9]+}}(4)                      * 8-byte Spill
-; CHECK64: std	12,{{[0-9]+}}(4)                      * 8-byte Spill
-; CHECK64: std	13,{{[0-9]+}}(4)                      * 8-byte Spill
-; CHECK64: std	14,{{[0-9]+}}(4)                      * 8-byte Spill
-; CHECK64: std	15,{{[0-9]+}}(4)                      * 8-byte Spill
+; CHECK64: vst  16,{{[0-9]+}}(4),4
+; CHECK64: vst  17,{{[0-9]+}}(4),4
+; CHECK64: vst  18,{{[0-9]+}}(4),4
+; CHECK64: vst  19,{{[0-9]+}}(4),4
+; CHECK64: vst  20,{{[0-9]+}}(4),4
+; CHECK64: vst  21,{{[0-9]+}}(4),4
+; CHECK64: vst  22,{{[0-9]+}}(4),4
+; CHECK64: vst  23,{{[0-9]+}}(4),4
+; CHECK64: std	8,{{[0-9]+}}(4)
+; CHECK64: std	9,{{[0-9]+}}(4)
+; CHECK64: std	10,{{[0-9]+}}(4)
+; CHECK64: std	11,{{[0-9]+}}(4)
+; CHECK64: std	12,{{[0-9]+}}(4)
+; CHECK64: std	13,{{[0-9]+}}(4)
+; CHECK64: std	14,{{[0-9]+}}(4)
+; CHECK64: std	15,{{[0-9]+}}(4)
 
-; CHECK64: vl   16,{{[0-9]+}}(4),4                   * 16-byte Reload
-; CHECK64: vl   17,{{[0-9]+}}(4),4                   * 16-byte Reload
-; CHECK64: vl   18,{{[0-9]+}}(4),4                   * 16-byte Reload
-; CHECK64: vl   19,{{[0-9]+}}(4),4                   * 16-byte Reload
-; CHECK64: vl   20,{{[0-9]+}}(4),4                   * 16-byte Reload
-; CHECK64: vl   21,{{[0-9]+}}(4),4                   * 16-byte Reload
-; CHECK64: vl   22,{{[0-9]+}}(4),4                   * 16-byte Reload
-; CHECK64: vl   23,{{[0-9]+}}(4),4                   * 16-byte Reload
-; CHECK64: ld	8,{{[0-9]+}}(4)                       * 8-byte Reload
-; CHECK64: ld	9,{{[0-9]+}}(4)                       * 8-byte Reload
-; CHECK64: ld	10,{{[0-9]+}}(4)                      * 8-byte Reload
-; CHECK64: ld	11,{{[0-9]+}}(4)                      * 8-byte Reload
-; CHECK64: ld	12,{{[0-9]+}}(4)                      * 8-byte Reload
-; CHECK64: ld	13,{{[0-9]+}}(4)                      * 8-byte Reload
-; CHECK64: ld	14,{{[0-9]+}}(4)                      * 8-byte Reload
-; CHECK64: ld	15,{{[0-9]+}}(4)                      * 8-byte Reload
+; CHECK64: vl   16,{{[0-9]+}}(4),4
+; CHECK64: vl   17,{{[0-9]+}}(4),4
+; CHECK64: vl   18,{{[0-9]+}}(4),4
+; CHECK64: vl   19,{{[0-9]+}}(4),4
+; CHECK64: vl   20,{{[0-9]+}}(4),4
+; CHECK64: vl   21,{{[0-9]+}}(4),4
+; CHECK64: vl   22,{{[0-9]+}}(4),4
+; CHECK64: vl   23,{{[0-9]+}}(4),4
+; CHECK64: ld	8,{{[0-9]+}}(4)
+; CHECK64: ld	9,{{[0-9]+}}(4)
+; CHECK64: ld	10,{{[0-9]+}}(4)
+; CHECK64: ld	11,{{[0-9]+}}(4)
+; CHECK64: ld	12,{{[0-9]+}}(4)
+; CHECK64: ld	13,{{[0-9]+}}(4)
+; CHECK64: ld	14,{{[0-9]+}}(4)
+; CHECK64: ld	15,{{[0-9]+}}(4)
 ; CHECK64: lg  7,2072(4)
 ; CHECK64: aghi  4,320
 ; CHECK64: b 2(7)
@@ -342,7 +344,6 @@ bb3:
 ; CHECK64-NEXT: llgt  3,1208
 ; CHECK64-NEXT: cg  4,64(3)
 ; CHECK64-NEXT: jhe
-; CHECK64: * %bb.1:
 ; CHECK64: lg  3,72(3)
 ; CHECK64: basr  3,3
 ; CHECK64: stmg  6,7,2064(4)
@@ -352,22 +353,22 @@ define void @large_stack0() {
   ret void
 }
 
-; CHECK-LABEL: large_stack1
+; CHECK-LABEL: large_stack1 DS 0H
 ; CHECK64: agfi  4,-1048800
 ; CHECK64: lgr 0,3
 ; CHECK64: llgt  3,1208
 ; CHECK64: cg  4,64(3)
 ; CHECK64: jhe L#BB8_2
-; CHECK64: %bb.1:
 ; CHECK64: lg  3,72(3)
 ; CHECK64: basr  3,3
 ; CHECK64: bcr 0,7
-; CHECK64: L#BB8_2:
+; CHECK64: L#BB8_2 DS 0H
 ; CHECK64: stmg  6,7,2064(4)
 ; CHECK64: lgr 3,0
 
-; CHECK64: L#PPA1_large_stack1_0:
-; CHECK64: .short	6  * Length/4 of Parms
+; CHECK64: L#PPA1_large_stack1_0 DS 0H
+; CHECK64: * Length/4 of Parms
+; CHECK64:  DC XL2'0006'
 define void @large_stack1(i64 %n1, i64 %n2, i64 %n3) {
   %arr = alloca [131072 x i64], align 8
   call i64 (ptr, i64, i64, i64) @fun3(ptr %arr,
@@ -383,11 +384,10 @@ define void @large_stack1(i64 %n1, i64 %n2, i64 %n3) {
 ; CHECK64: llgt  3,1208
 ; CHECK64: cg  4,64(3)
 ; CHECK64: jhe L#BB9_2
-; CHECK64: %bb.1:
 ; CHECK64: lg  3,72(3)
 ; CHECK64: basr  3,3
 ; CHECK64: bcr 0,7
-; CHECK64: L#BB9_2:
+; CHECK64: L#BB9_2 DS 0H
 ; CHECK64: lgr 3,0
 ; CHECK64: lg  3,2192(3)
 ; CHECK64: stmg  4,12,2048(4)
@@ -400,11 +400,13 @@ define void @large_stack2(i64 %n1, i64 %n2, i64 %n3) {
   ret void
 }
 
-; CHECK-LABEL: leaf_func
-; CHECK: .long	8 * DSA Size 0x0
-; CHECK-NEXT:     * Entry Flags
-; CHECK-NEXT:     *   Bit 1: 1 = Leaf function
-; CHECK-NEXT:     *   Bit 2: 0 = Does not use alloca
+; CHECK-LABEL: L#EPM_leaf_func0_0 DS 0H
+; CHECK: * DSA Size 0x0
+; CHECK: * Entry Flags
+; CHECK: *   Bit 1: 1 = Leaf function
+; CHECK: *   Bit 2: 0 = Does not use alloca
+; CHECK:  DC XL4'00000008'
+; CHECK-LABEL: leaf_func0 DS 0H
 ; CHECK-NOT: aghi  4,
 ; CHECK-NOT: stmg
 ; CHECK: agr	1,2
@@ -423,17 +425,18 @@ define i64 @leaf_func0(i64 %a, i64 %b, i64 %c) {
 ; =============================
 ;     Tests for PPA1 Fields
 ; =============================
-; CHECK-LABEL: named_func
-; CHECK: .byte	129  * PPA1 Flags 4
+; CHECK-LABEL: named_func DS 0H
+; CHECK:      * PPA1 Flags 4
 ; CHECK-NEXT: *   Bit 7: 1 = Name Length and Name
+; CHECK-NEXT:  DC XL1'81'
 define i64 @named_func(i64 %arg) {
   %sum = add i64 1, %arg
   ret i64 %sum
 }
 
-; CHECK-LABEL: __unnamed_1
-; CHECK: .byte	128  * PPA1 Flags 4
-; CHECK-NOT: *   Bit 7: 1 = Name Length and Name
+; CHECK-LABEL: __unnamed_1 DS 0H
+; CHECK:      * PPA1 Flags 4
+; CHECK-NEXT:  DC XL1'80'
 define void @""(ptr %p) {
   call i64 (ptr) @fun1(ptr %p)
   ret void
diff --git a/llvm/test/CodeGen/SystemZ/zos-ret-addr.ll b/llvm/test/CodeGen/SystemZ/zos-ret-addr.ll
index 483376051a872..ce59020dda4b2 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ret-addr.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ret-addr.ll
@@ -3,7 +3,7 @@
 
 ; The current function's return address is in the link register.
 define ptr @rt0() norecurse nounwind readnone {
-; CHECK-LABEL: rt0:
+; CHECK-LABEL: rt0 DS 0H
 ; CHECK:         lgr 3,7
 ; CHECK-NEXT:    b 2(7)
 entry:
@@ -13,7 +13,7 @@ entry:
 
 ; Check the caller's return address.
 define ptr @rtcaller() nounwind "backchain" {
-; CHECK-LABEL: rtcaller:
+; CHECK-LABEL: rtcaller DS 0H
 ; CHECK:         stmg 4,7,2048(4)
 ; CHECK-NEXT:    lg 1,2048(4)
 ; CHECK-NEXT:    lg 3,24(1)
@@ -26,7 +26,7 @@ entry:
 
 ; Check the caller's caller's return address.
 define ptr @rtcallercaller() nounwind "backchain" {
-; CHECK-LABEL: rtcallercaller:
+; CHECK-LABEL: rtcallercaller DS 0H
 ; CHECK:         stmg 4,7,2048(4)
 ; CHECK-NEXT:    lg 1,2048(4)
 ; CHECK-NEXT:    lg 1,0(1)
diff --git a/llvm/test/CodeGen/SystemZ/zos-simple-test.ll b/llvm/test/CodeGen/SystemZ/zos-simple-test.ll
index f1f7cee8268f7..a185fc7016a07 100644
--- a/llvm/test/CodeGen/SystemZ/zos-simple-test.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-simple-test.ll
@@ -7,11 +7,10 @@
 define signext i32 @main() {
 ; CHECK: stdin#C CSECT
 ; CHECK: C_CODE64 CATTR ALIGN(3),FILL(0),READONLY,RMODE(64)
-; CHECK: main:
+; CHECK: main DS 0H
 ; CHECK: stdin#C CSECT
 ; CHECK: C_WSA64 CATTR ALIGN(2),FILL(0),DEFLOAD,NOTEXECUTABLE,RMODE(64),PART(a)
 ; CHECK: a XATTR LINKAGE(XPLINK),REFERENCE(DATA),SCOPE(EXPORT)
-; CHECK: a:
 entry:
   ret i32 0
 }
diff --git a/llvm/test/CodeGen/SystemZ/zos-stackpointer.ll b/llvm/test/CodeGen/SystemZ/zos-stackpointer.ll
index 4f4f650f51a77..d40933cd8d1d8 100644
--- a/llvm/test/CodeGen/SystemZ/zos-stackpointer.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-stackpointer.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=s390x-ibm-zos | FileCheck %s
 
-; CHECK-LABEL: get_stack:
+; CHECK-LABEL: get_stack DS 0H
 ; CHECK: lgr   3,4
 ; CHECK: b 2(7)
 
diff --git a/llvm/test/CodeGen/SystemZ/zos-symbol-1.ll b/llvm/test/CodeGen/SystemZ/zos-symbol-1.ll
index 92cb6371a7c50..3e737dd66c514 100644
--- a/llvm/test/CodeGen/SystemZ/zos-symbol-1.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-symbol-1.ll
@@ -1,4 +1,4 @@
-; RUN: llc <%s --mtriple s390x-ibm-zos -emit-gnuas-syntax-on-zos=false | FileCheck %s
+; RUN: llc <%s --mtriple s390x-ibm-zos | FileCheck %s
 
 declare extern_weak void @other1(...)
 declare void @other2(...)
diff --git a/llvm/test/CodeGen/SystemZ/zos-symbol-2.ll b/llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
index ffea210fa9c7b..663c01ccd80dc 100644
--- a/llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
@@ -1,4 +1,4 @@
-; RUN: llc <%s --mtriple s390x-ibm-zos -emit-gnuas-syntax-on-zos=false | FileCheck %s
+; RUN: llc <%s --mtriple s390x-ibm-zos | FileCheck %s
 ; RUN: llc <%s --mtriple s390x-ibm-zos --filetype=obj | \
 ; RUN:   od -Ax -tx1 -v | FileCheck --check-prefix=CHECKREL --ignore-case %s
 
diff --git a/llvm/test/CodeGen/SystemZ/zos_sinit.ll b/llvm/test/CodeGen/SystemZ/zos_sinit.ll
index 447dec345e175..4b154d6597090 100644
--- a/llvm/test/CodeGen/SystemZ/zos_sinit.ll
+++ b/llvm/test/CodeGen/SystemZ/zos_sinit.ll
@@ -1,4 +1,4 @@
-; RUN: llc -emit-gnuas-syntax-on-zos=false < %s -mtriple=s390x-ibm-zos | \
+; RUN: llc < %s -mtriple=s390x-ibm-zos | \
 ; RUN: FileCheck --check-prefixes=CHECK %s
 
 @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 22, ptr @cfuncctor, ptr null }]
diff --git a/llvm/test/MC/SystemZ/insn-good-zos-pcrel.s b/llvm/test/MC/SystemZ/insn-good-zos-pcrel.s
index 0acbe26d75b15..07bf680f48b1d 100644
--- a/llvm/test/MC/SystemZ/insn-good-zos-pcrel.s
+++ b/llvm/test/MC/SystemZ/insn-good-zos-pcrel.s
@@ -1,5 +1,5 @@
 * For z10 and above.
-* RUN: llvm-mc -triple s390x-ibm-zos -show-encoding %s | FileCheck %s
+* RUN: llvm-mc -triple s390x-ibm-zos -show-encoding -emit-gnuas-syntax-on-zos=1 %s | FileCheck %s
 
 *CHECK: brcl	0, FOO                  * encoding: [0xc0,0x04,A,A,A,A]
 *CHECK:  fixup A - offset: 2, value: FOO+2, kind: FK_390_PC32DBL