diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 9a85634c82626..5eb8928761f68 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -1428,8 +1428,9 @@ unsigned SPIRVGlobalRegistry::getNumScalarOrVectorTotalBitWidth(
     Type = getSPIRVTypeForVReg(Type->getOperand(1).getReg());
   }
   return Type->getOpcode() == SPIRV::OpTypeInt ||
-                 Type->getOpcode() == SPIRV::OpTypeFloat
-             ? NumElements * Type->getOperand(1).getImm()
+                 Type->getOpcode() == SPIRV::OpTypeFloat ||
+                 Type->getOpcode() == SPIRV::OpTypeBool
+             ? NumElements * getScalarOrVectorBitWidth(Type)
              : 0;
 }
 
diff --git a/llvm/test/CodeGen/SPIRV/masked-store-bool-mask.ll b/llvm/test/CodeGen/SPIRV/masked-store-bool-mask.ll
new file mode 100644
index 0000000000000..8ff60ba68af60
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/masked-store-bool-mask.ll
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+define void @kernelAddConstant(<8 x i1> %0) {
+; CHECK-LABEL: kernelAddConstant
+; CHECK:       %44 = OpFunction %20 None %21 ; -- Begin function kernelAddConstant
+; CHECK-NEXT:    %45 = OpFunctionParameter %19
+; CHECK-NEXT:    %78 = OpLabel
+; CHECK-NEXT:    %46 = OpBitcast %24 %45
+; CHECK-NEXT:    %47 = OpBitwiseAnd %24 %46 %43
+; CHECK-NEXT:    %48 = OpINotEqual %18 %47 %42
+; CHECK-NEXT:    %49 = OpBitcast %23 %41
+; CHECK-NEXT:    %50 = OpInBoundsPtrAccessChain %23 %49 %40
+; CHECK-NEXT:    %51 = OpBitcast %23 %41
+; CHECK-NEXT:    %52 = OpInBoundsPtrAccessChain %23 %51 %39
+; CHECK-NEXT:    %53 = OpBitcast %23 %41
+; CHECK-NEXT:    %54 = OpInBoundsPtrAccessChain %23 %53 %38
+; CHECK-NEXT:    %55 = OpBitcast %23 %41
+; CHECK-NEXT:    %56 = OpInBoundsPtrAccessChain %23 %55 %37
+; CHECK-NEXT:    %57 = OpBitcast %23 %41
+; CHECK-NEXT:    %58 = OpInBoundsPtrAccessChain %23 %57 %36
+; CHECK-NEXT:    %59 = OpBitcast %23 %41
+; CHECK-NEXT:    %60 = OpInBoundsPtrAccessChain %23 %59 %35
+; CHECK-NEXT:    %61 = OpBitcast %23 %41
+; CHECK-NEXT:    %62 = OpInBoundsPtrAccessChain %23 %61 %34
+; CHECK-NEXT:    OpBranchConditional %48 %2 %3
+; CHECK-NEXT:    %2 = OpLabel
+; CHECK-NEXT:    %63 = OpBitcast %23 %41
+; CHECK-NEXT:    OpStore %63 %33 Aligned 1
+; CHECK-NEXT:    OpBranch %3
+; CHECK-NEXT:    %3 = OpLabel
+; CHECK-NEXT:    %64 = OpBitwiseAnd %24 %46 %32
+; CHECK-NEXT:    %65 = OpINotEqual %18 %64 %42
+; CHECK-NEXT:    OpBranchConditional %65 %4 %5
+; CHECK-NEXT:    %4 = OpLabel
+; CHECK-NEXT:    OpStore %50 %33 Aligned 1
+; CHECK-NEXT:    OpBranch %5
+; CHECK-NEXT:    %5 = OpLabel
+; CHECK-NEXT:    %66 = OpBitwiseAnd %24 %46 %31
+; CHECK-NEXT:    %67 = OpINotEqual %18 %66 %42
+; CHECK-NEXT:    OpBranchConditional %67 %6 %7
+; CHECK-NEXT:    %6 = OpLabel
+; CHECK-NEXT:    OpStore %52 %33 Aligned 1
+; CHECK-NEXT:    OpBranch %7
+; CHECK-NEXT:    %7 = OpLabel
+; CHECK-NEXT:    %68 = OpBitwiseAnd %24 %46 %30
+; CHECK-NEXT:    %69 = OpINotEqual %18 %68 %42
+; CHECK-NEXT:    OpBranchConditional %69 %8 %9
+; CHECK-NEXT:    %8 = OpLabel
+; CHECK-NEXT:    OpStore %54 %33 Aligned 1
+; CHECK-NEXT:    OpBranch %9
+; CHECK-NEXT:    %9 = OpLabel
+; CHECK-NEXT:    %70 = OpBitwiseAnd %24 %46 %29
+; CHECK-NEXT:    %71 = OpINotEqual %18 %70 %42
+; CHECK-NEXT:    OpBranchConditional %71 %10 %11
+; CHECK-NEXT:    %10 = OpLabel
+; CHECK-NEXT:    OpStore %56 %33 Aligned 1
+; CHECK-NEXT:    OpBranch %11
+; CHECK-NEXT:    %11 = OpLabel
+; CHECK-NEXT:    %72 = OpBitwiseAnd %24 %46 %28
+; CHECK-NEXT:    %73 = OpINotEqual %18 %72 %42
+; CHECK-NEXT:    OpBranchConditional %73 %12 %13
+; CHECK-NEXT:    %12 = OpLabel
+; CHECK-NEXT:    OpStore %58 %33 Aligned 1
+; CHECK-NEXT:    OpBranch %13
+; CHECK-NEXT:    %13 = OpLabel
+; CHECK-NEXT:    %74 = OpBitwiseAnd %24 %46 %27
+; CHECK-NEXT:    %75 = OpINotEqual %18 %74 %42
+; CHECK-NEXT:    OpBranchConditional %75 %14 %15
+; CHECK-NEXT:    %14 = OpLabel
+; CHECK-NEXT:    OpStore %60 %33 Aligned 1
+; CHECK-NEXT:    OpBranch %15
+; CHECK-NEXT:    %15 = OpLabel
+; CHECK-NEXT:    %76 = OpBitwiseAnd %24 %46 %26
+; CHECK-NEXT:    %77 = OpINotEqual %18 %76 %42
+; CHECK-NEXT:    OpBranchConditional %77 %16 %17
+; CHECK-NEXT:    %16 = OpLabel
+; CHECK-NEXT:    OpStore %62 %33 Aligned 1
+; CHECK-NEXT:    OpBranch %17
+; CHECK-NEXT:    %17 = OpLabel
+; CHECK-NEXT:    OpReturn
+; CHECK-NEXT:    OpFunctionEnd
+  call void @llvm.masked.store.v8i32.p1(<8 x i32> zeroinitializer, ptr addrspace(1) null, <8 x i1> %0)
+  ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
+declare void @llvm.masked.store.v8i32.p1(<8 x i32>, ptr addrspace(1) captures(none), <8 x i1>) #0
+
+attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }